2 SPCE061AnSPTMI/OPLLCTCA/DD/ALVD/LVRSIOUART

2.1 nSPTM

1nSPTMSR: NZSC4 DS CSNbit15=1N=1ZS=1C/

216 16 () nSP16 16 MUL 16 MULS (signed signed) (unsigned signed) MUL 12 MULS 10n+6 n MR=[R2]*[R1] 44 MULS46104+6=46nSPMR=[Rd]* [Rs] {,ss} {,n}MR=((Rd))((Rs))+ ((Rd+1))((Rs+1))+ ((Rd+2))((Rs+2)) +

3[2.1]: R1=32767R2=32767R1 0xFFFE R1=32767 //N=0Z=0S=0C=1R1=0x7FFF R2=32767 //N=0Z=0S=0C=1R2=0x7FFF R1+=R2 //N=1Z=0S=0C=0R1=0xFFFE C0 N!=S S0 2.2]: R1=-12345R2=-1R1 0xCFC6 R1=-12345 //N=1Z=0S=0C=1 R1=0xCFC7 R2=-1 //N=1Z=0S=0C=1 R2=0xFFFF R1+=R2 //N=1Z=0S=1C=1 R1=0xCFC6 C1 N=SS1 [2.3]R1=32767R2=-12345R1 0xB038 R1=32767 //N=0Z=0S=0C=1 R1=0x7FFF R2=-12345 //N=1Z=0S=0C=1 R2=0xC7C7 R1-=R2 //N=1Z=0S=0C=0 R1=0xB038 C0N!=SS0

S=N=C=Z=

2.2 ROMEPROMEPROMFLASHSRAMSPCE061ASRAM2KWFLASH32KW

SPCE061A2KW SRAMI/O32K FALSH ROM0x000000 0x0007FF 0x000800

0x006FFF0x007000

0x007FFF0x008000

0x00FFF50x00FFF60x00FFFF

SPCE061A0x07FF*0x0000SPSPSRAM11SP0x07FF(SP)

0x07FF*0x0000(SP)

SP-1SP+1SPCE061A

1234

FLASHFlashSRAMFlashSPCE061A 32K (32K16 )32K 128 256 0x8000

FLASH1 SRAM 2 1. 2. 20mS3

FLASH[2.4] //================================================//FLASH.asm //1 //================================================ .INCLUDE hardware.inc .DEFINE C_FLASH_SIZE 0x8000 //flash 32K .DEFINE C_FLASH_BLOCK_SIZE 0x0100 //256 .DEFINE C_FLASH_MATCH 0xAAAA .DEFINE C_FLASH_PAGE_ERASE 0x5511 // .DEFINE C_FLASH_1WORD_PGM 0x5533 // .DEFINE C_FLASH_SEQUENT_PGM 0x5544 // .CODE//===================================================// : F_FlashWrite1Word() //FLASH //1Flash 2 // //=================================================== .public _F_FlashWrite1Word .DEFINE P_Flash_Ctrl 0x7555 _F_FlashWrite1Word: .proc PUSH BP TO [SP] //BP BP = SP + 1 //BPSP+1 R1 = C_FLASH_MATCH //AAAA [P_Flash_Ctrl] = R1 R1 = C_FLASH_1WORD_PGM //5533 [P_Flash_Ctrl] = R1 R1 = [BP+3] //Flash R2 = [BP+4] // [R1] = R2 // POP BP FROM [SP] //BP RETF // .ENDPFLASHSRPCBPSPBP=SP+1//========================================================= // F_FlashWrite() // //1Flash 23 // //========================================================= .public _F_FlashWrite _F_FlashWrite: .proc // PUSH BP TO [SP] //BP BP = SP + 1 //BPSP+1 R1 = [BP+3] //Flash R2 = [BP+4] // R3 = [BP+5] //N R4 = C_FLASH_MATCH //AAAA [P_Flash_Ctrl] = R4 L_FlashWriteLoop: R4 = C_FLASH_SEQUENT_PGM //5544 [P_Flash_Ctrl] = R4 R4 = [R2++] // [R1++] = R4 R3 -= 1 // JNZ L_FlashWriteLoop //0 [P_Flash_Ctrl] = R3 // POP BP FROM [SP] //BP RETF // .ENDP//===================================================// F_FlashErase() //256 //:1 //=================================================== .public _F_FlashErase _F_FlashErase: .proc // PUSH BP TO [SP] //BP BP = SP + 1 R1 = C_FLASH_MATCH //AAAA [P_Flash_Ctrl] = R1 R1 = C_FLASH_PAGE_ERASE //5511 [P_Flash_Ctrl] = R1 R1 = [BP+3] // [R1] = R1 // POP BP FROM [SP] //BP RETF // .ENDP

2.3SPCE061A

CPUI/OI/OLCD

1I/OI/O>0.1~5mA25mAI/OI/OI/OI/OI/OI/O

SPCE061A I/OI/O8I/OI/O2~3mA20mAI/OCPUI/O(P_IOA_Data)I/O(P_IOA_Buffer)

2SPCE061A I/O16PIOAPIOBI/O816I/OPIOB0~10

IO

IO

P_IOA_Data7000H/CPUP_IOA_Buffer7001H/CPUBufferP_IOA_Dir7002H/IO=0=1P_IOA_Attrib7003H/IO=0/=1 =0P_IOA_Latch7004HAIOA 0~7P_IOB_Data7005H/AP_IOB_Buffer7006H/AP_IOB_Dir7007H/AP_IOB_Attrib7008H/AP_FeedBack7009HBB

IO

_Dir_Attrib_Data000001010011100101110111

I/OI/O

PIOIOA[0] LEDP_IOA_Data[0]___P_IOA_Data[0]___P_IOA_Buffer[0]___ LEDIOA[0]P_IOA_Data[0]P_IOA_Buffer[0]IOA[0]

[2.5] IO IO IOA[3~0] IOA[7~4]IOA[11~8]IOA[15~12] R1 = 0x0FF0 //A IOA0~IOA3 IOA12~IOA15 [P_IOA_Data] = R1 //IOA4~IOA7 IOA8~IOA11 R1 = 0xFF00 //A IOA0~IOA8 [P_IOA_Attrib] = R1 // IOA12~IOA15 R1 = 0xFF00 //A IOA0~IOA8 [P_IOA_Dir] = R1 // IOA12~IOA15

Bit1514131211109876543210_Dir1100_Attrib1100_Data0110

111111110000

111111111111

000000001111

000000000000

[2.6] A VDDR2R3 .INCLUDE hadware.inc // .CODE .PUBLIC _main // _main: R1=0x0000 //A [P_IOA_Data]=R1 //A [P_IOA_Attrib]=R1 //A [P_IOA_Dir]=R1 //A //************A **************// R3=[P_IOA_Data] //P_IOA_Data R3 R2=[P_IOA_Buffer] //P_IOA_Buffer R2 WAIT: JMP WAIT //IOA[15..8] : 60~53IOA[7..0] : 48~41

[2.7]I/OB1I/OBR3.DEFINE P_IOB_Data 0x7005 .DEFINE P_IOB_Dir 0x7007 .DEFINE P_IOB_Attrib 0x7008 .DEFINE P_IOB_Buffer 0x7006 .CODE .PUBLIC _main // _main: R1=0xFFFF //B [P_IOB_Dir]=R1 //3 [P_IOB_Data]=R1 R1=0x0000 [P_IOB_ Attrib]=R1 R1=0x0000 //0x0000 [P_IOB_Data]=R1 //****************B****************// R3=[P_IOB_Buffer] // Buffer 0x0000 LOOP: JMP LOOP //IOB0.IOB15

P73 678

[2.8]A 8 B 8 Key1 B0 ?//**************A B **************// R1 = 0x0000 // R1 0x0000 [P_IOA_Dir] = R1 //A [P_IOA_Attrib] = R1 //A R1 = 0x00FF [P_IOA_Data] = R1 //A R2 = 0X00FF // R2 0x00FF [P_IOB_Dir] = R2 //B [P_IOB_Attrib] = R2 //B [P_IOB_Data] = R2 //B //*********** ***********// R1 = [keycode] //R1 CMP R10x0000 //0 JE _MAIN CMP R1 0x0001 // JE LOOP1 //LOOP1 CMP R1 0x0002 // JE LOOP2 //LOOP2 CMP R1 0x0040 // JE LOOP7 //LOOP7 R2=[P_IOA_Data] //IOB7 R2&=0x0080 [P_IOB_Data]=R2 //IOB7 JMP _MAIN // LOOP1 R2=[P_IOA_Data] //IOB0 R2&=0x0001 //IOB0 [P_IOB_Data]=R2 JMP _MAIN LOOP2 R2=[P_IOA_Data] //IOB1 R2&=0x0002 //IOB1 [P_IOB_Data]=R2 JMP _MAIN LOOP7 R2=[P_IOA_Data] //IOB6 R2&=0x0040 //IOB6 [P_IOB_Data]=R2 JMP _MAIN

[2.8]OK!

B

IOB0SCKIOB1SDAIOB2EXT11IO2FeedBack_Output1IOB4RCEXT1EXT1IOB3EXT22IO3FeedBack_Output2IOB5RCEXT2EXT2IOB4FeedBack_Input1IOB5FeedBack_Input2IOB6IRRxIOB7RxIOB8APWMOAPWMIRTxIOB9BPWMOBPWMIOB10Tx

P_FeedBack($7009H)**

b15~b4b3b2b1b0FBKEN3FBKEN21IOB3IOB5 0IOB3IOB5 I/O() 1IOB2IOB4 0IOB2IOB4I/O()

[2.9] IOB2 IOB4 RC //IOB4 IOB2 R1=0x0004 [P_IOB_Dir]=R1 //0000000000000100 R1=0x0010 //0000000000010000 [P_IOB_Attrib]=R1 [P_IOB_Data]=R1 // P_FeedBack IOB2IOB4 R1=0x0004 [P_FeedBack]=R1

SPCE061A I/OSPCE061ASPCE061A

2.4 C1 20pfC2 20pf32768HzOSC32IOSC32O1V

2.5PLLPhase Lock LoopP_SystemClock(7013H)

b15~8b7~5b4b3b2~0PLL3276832768CPU132768Hz0 32768Hz1 32768Hz0 32768Hz

PLLFosc/nn=1,2,4,8,16,32,64b2~032768HzfoscCPUCLK b2~0=111CPUb7~5P_System_Clock

b2b1b0n0001001201040118100161013211064111

b7b6b5fOSC (MHz)00024.57600120.4801032.76801140.961xx49.152

[2.11] 1mS R1=0x0023//Fosc20MHzCPUCLKFosc/8=2.56MHz [P_System_Clock]=R1 R3=0x0000DELAY: R2=0x0000LOOP1://3+3+521 1/2560000=0.000090234375S R2+=1//3100S CMP R221//3 JB LOOP1//

2.6

P_INT_Ctrlb2~6 32 10 CLKB32HzCTCCTCP_TimeBase_Stup R1=0x0002 [P_TimeBase_Stup]=R1 CTCIRQ456

P_TimeBase_Setup($700EH)P452.112.12P_TimeBase_Clear($700FH)

2.7HCMOS2.5V1.8VCPUCPUVA

SPCEOSCnormal mode auto-power saving mode.OSCnormal modeauto-power save mode10uASystem clock auto-power saving mode auto-power saving mode7.57.5auto-power saving modenormal mode

CPUI/OCPU CPU

SPCE061A320.7s3.3V30~50mA3.3V2mA3.3V2A

SPCE061ACPUCPUCPUCPUSPCE061AIRQ3_KEYFIQIRQ1~6UART_IRQ

[2.12]CPU//R1=0x0000[P_IOA_Attrib]=R1[P_IOA_Dir]=R1[P_IOA_Data]=R1//INT OFFR1=0x0080//[P_Int_Ctrl]=R1INT IRQ//P_IOA_LatchIOA[7-0]R1=[P_ IOA_Latch]//P_SystemClock2~01114//0R1=0x0007[P_SystemClock]=R1//IRQ3.TEXT.PUBLIC _IRQ3_IRQ3R1=0x0100TEST R1 [P_Int_Ctrl] //1JNZ L_IRQ3_Ext1R1=0x0200TEST R1 [P_Int_Ctrl] //2JNZ L_IRQ3_Ext2L_IRQ3_KeyChange_WakeUp//R1=0x0080 //[P_Int_Clear]=R1

CPU,:IOA[7-0]P_IOA_LatchP_SystemClock2011140

P73 16

2.8

2.8 PWM V/P / CTC

/

CTC EXT1EXT2 [P_TimerA_Data][P_TimerB_Data]

CTCA AB1 A016/ EXT1EXT2 IOB2IOB3 TMB1TA_TimeOut_INT 4=APWMO TAOUT? FTAOUT/2?

CTCB

CTCP_TimerA_Ctrl$700BH)P_TimerB_Ctrl$700DH)TBON b9~6TA/BON=1

b2~0A000Fosc/2001Fosc/25601032768Hz0118192Hz1004096Hz10111100111EXT1

b3~5B0002048Hz0011024Hz010256Hz011TMB11004Hz1012Hz1101111EXT2

b9~6APWMOTAON0000OFF000011/16100102 /16100113 /16101004 /16101015 /16101106 /16101117 /161

b9~6APWMOTAON10008/16110019 /161101010 /161101111 /161110012 /161110113 /161111014 /1611111TAOUT1

:

[2.13]R1=0x0005[P_TimerA_ctrl]=R11S,?0.5S,?

//2048HzR1=0xFBFF [P_TimerA_ctrl]=R1//10240.5S

CTC [P_TimerA/B_Ctrl] P_TimerA_Ctrl 5~0/2~0 P_TimerB_Ctrl 2~0PWM PWMP_TimerA/B_Ctrl 9~6 [P_TimerA/B_Data]1 =FFFFH-CTC=/=1/ PWMPWM16 =

R1=0x0100 //IOB8 _Dir=1 _Attrib=0[P_IOB_Dir]=R1[P_IOB_Attrib]=R1R1=0x0000[P_IOB_Data]=R1R1=0xFDFF //=65535-512=65023[P_TimerA_Data]=R1R1=0x00F0 //ClkAfosc/2ClkB1=3/16[P_TimerA_Ctrl]=R1APWMO fAPWMO=12.288MHz/512/16=1.5KHz

P_TimerA_Ctrlb15~10b9~6b5~3b2~0PWM011B110A000

P73 18

2.9 A/DADCADC

A/D-A/DADCADCADC-ADCDSPADC

SPCE061AADCA/D 3ADC380~2V(2-0)/8=250mV102mV 1.3V1011.25V0.05V1.45V0.25V

ADC$7015H ( P_ADC_Ctrl )DAC0DAR0SAR + -|AGCMIC_INSHEADECOMPRDYAUTO0110LINEIOA[06]AGCEP_ADC$7014H)P_ADC_MUX _Ctrl bit2~0 DAC0MIC_IN

b15b14b8b7b6b4b3b2b1b0MICRDY=1COMP =1DAC0-02V1 01VRTPADVREF2DAC=03mA/3V=12mA/3VAUTO 01SHE =1=0AGCE 0AGC 1AGCLINE=0MIC=1LINE_INADE 01A/D

1000000000> 1100000000> 11100000000100000000> 0110000000> 01110000001010000000> 1011000000> 1011100000NNNNNN

P_ADC_MUX _Ctrl7015H10 P_ADC(7014H)MIC P_ADC_MUX_Data(702CH)LINEA/DP_DAC_Ctrl b43

b15b14b13~3b2~0Ready_MUX ()FAIL()Channel_Sel(/)0 LINE_IN AD1LINE_IN AD0MICLINELINEMIC FAIL1MIC0000MIC001LINE_IN1010LINE_IN2011LINE_IN3100LINE_IN4101LINE_IN5110LINE_IN6111LINE_IN7

ADC

FOSC/32/1620.48 MHz24.576MHz32.768MHz40.96 MHz49.152MHz40KHz48KHz64KHz80KHz96KHz

LINE_INP_ADC_MUX_Data 10A/DRDY'0'A/DP_ADC_MUX_Data RDY'1'A/D.DEFINE P_IOB_DATA 0x7005 .DEFINE P_IOB_DIR 0x7007 .DEFINE P_IOB_Attrib 0x7008 .DEFINE P_INT_Ctrl 0x7010 .DEFINE P_INT_CLEAR 0x7011 .DEFINE P_ADC_Ctrl 0x7015 .DEFINE P_ADC_MUX_Ctrl 0x702b .DEFINE P_ADC_MUX_DATA 0x702C .DEFINE P_DAC_Ctrl 0x702A .CODE .PUBLIC _main // _main: R1=0xffff //r10xffff [P_IOB_Attrib]=r1 //IOB // [P_IOB_DIR]=r1 R1=0x0000 [P_IOB_DATA]=r1;R1=0x0001 //LINE_INIOA0 LINE_IN1[P_ADC_MUX_Ctrl]=R1R1 = 0x0013 //P_ADC_CtrlA/D[P_ADC_Ctrl] = R1 NOP // NOP NOPNOPNOP_AD: R2=[P_ADC_MUX_Ctrl] //[P_ADC_MUX_Ctrl] //b15AD TEST R2,0x8000JZ _AD //READYR1=[P_ADC_MUX_DATA] //[P_ADC_MUX_DATA] //A/D [P_IOB_Data]=R1; //IOB JMP _AD //_AD MICADC[P_ADC]CTC[P_DAC_Ctrl]43LINE [P_ADC _ LINE _ Data] ADC

b15b14b8b7b6b4b3b2b1b0MICRDY=1COMP =1DAC0-02V1 01VRTPADVREF2DAC=03mA/3V=12mA/3VAUTO 01SHE =1=0AGCE 0AGC 1AGCLINE=0MIC=1LINE_INADE 01A/D

2.10 DAC&PWMDAC/PWMD/A

DAC DAR1DAC110P_DAC1P_DAC_Ctrl 8 7 DAR2DAC210P_DAC2P_DAC_Ctrl 6 5 PWMP_DAC2PWM_LatchPWM_Mode0011AUD1AUD2DAC/PWMDAC1IOB8IOB9DAC2TAON1001TBON[P_Timer_Ctrl]9-6 =0000TAON=0=1

[P_DAC_Ctrl](,702AH)PWM_Mode 0 1DAC/PWM 0DAC 1PWMPWM_Latch 0PWM1PWMPWMADC _Latch00P _ ADCADC01TimerAADC10TimerBADC11TimerATimerBADCDAC2 _Latch00DAR2DAC201TimerADAR2DAC210TimerBDAR2DAC211TimerATimerBDAR2DAC2DAC1 _Latch00DAR1DAC101TimerADAR1DAC110TimerBDAR1DAC111TimerATimerBDAR1DAC1

b15~9b87b65b43b2b1b0DAC1_LatchDAC2_LatchADC_LatchPWM_LatchDAC/PWMPWM_Mode

DACP_DAC1DAR1D/ADAR1P_DAC2PWM D/A

ADCDAC MIC8KHzPWM//.DEFINEP_TimerA_data0x700a;.DEFINEP_TimerA_ctrl0x700b;.DEFINEP_INT_ctrl0x7010;.DEFINEP_INT_clear0x7011;.DEFINEP_WATCHDOG_clear0x7012;.DEFINEP_ADC 0x7014;.DEFINEP_ADC_ctrl0x7015;.DEFINEP_DAC2 0x7016;.DEFINEP_DAC1 0x7017;.DEFINEP_DAC_ctrl0x702a;.RAM.CODE//ADCDAC//TimerA//----------------------------------------------------------.PUBLIC_main//MAIN_main//MAININTOFFr1=0xFFFF; //=8KHzr1-=0x05DC;// Fosc = 24.576MHz 65535-1500[P_TimerA_data]=r1;// 8KHz =Fosc/2/1500r1=0x0030;//CLKA=Fosc/2CLKB=1[P_TimerA_ctrl]=r1;//APWMO=OFFr1=0x0015;//MICAGC[P_ADC_ctrl]=r1;r1=0x0002;//PWMPWM[P_DAC_ctrl]=r1;//P _ ADCADCr1=0x1000;//TimerAIRQ1[P_INT_ctrl]=r1;INTIRQ;ENDLOOP:r1=0x0001;[P_WATCHDOG_clear]=r1;//jmpENDLOOP//----------------------------------------------------------.PUBLICIRQ;//IRQ1_IRQ1:push r1,r5 to [sp];[P_INT_clear]=r1;r1=[P_ADC];//P _ ADCADC[P_DAC2]=r1;pop r1,r5 from [sp];reti;R1=

P73 1921

211

SPCE061A2.2VSPCE061A2.2V4FOSC

P_LVD_Ctrlb15b14~2b10Result_of_LVDLVD_level_defineVLVD0VDD>VLVD1VDD

I/OLVRI/OCPU

SPCE061AfOSC = 24.576MHzCPUCLK=fOSC /8CPU32768HzAD2VAGCADC DAC3mAPC=FFF7HPIOABI/OACTCabP65

PFUSE5VPVINGND1sCPUREADDOWNLOADDEBUG

WatchDogWatchdog_Reset=1SWatchdog_Clear= 0.75SClearWatchDogSPCE061AWatchDog WatchDog

P_WatchDog_Clear(7012H)b 15~1b 00WatchDog1WatchDog

2.12 SIOSIO-Serial I/O interfaceI/O-SPII2 CCPUI/O LCDFLASHSPCE061AIOB0IOB1SCKSDA

GSM13281LCD

SIO P_SIO_Ctrl($701EH)CPUCLK/4

SIOP_SIO_Data($701AH)/SIO8/P_SIO_Addr_LOW($701BH)P_SIO_Addr_Mid($701CH)P_SIO_Addr_High($701DH)SIOP_SIO_Start($701FH)/ SIOSIOb7Busy=1SIOP_SIO_Stop($7020H) SIOSIO

SIO1

SIO 400H10SPRS512

B7b6b5b4b3b2b1b0SIO_ConfigR/WR/W_ENClock_SelAddr_Select11001011IOB0SCKIOB1SDACPUCLK/424

2.13 UART

UARTUniversal Asynchronous Receiver TransmitterRx Tx GND SPCE061AIOB7RxIOB10TxRS23212VEIA

SPCE061AURAT222

UART1 P_UART_Data$7023H2

P_UART_Command1

P_UART_Command1(7021H00H76543210RxIntEnTxIntEnI_ResetParityP_Check1UARTRxRDY01UARTTxRDY0101010

P_UART_Command2

P_UART_Command27033HB7B6B5B4B3B2~B0RxPinEN1TxPinEN1 ----RxRDY=1TxRDY=1FE=1OE=1PE=1-

UARTFE ()TXRX1. 2. OE ()RXTXRX1. 2. PE ()

P_UART_BaudScalarLow($7024H) P_UART_BaudScalarHigh($7025H)bps=/=fosc/2/n

fosc=24.567MHzbpsN15001FHFFH8192240014H00H512048000AH00H2560960005H00H12801920002H80H6403840001H40H3204800001H00H2565120000HF0H2405760000HD6H21310240000H78H12011520000H6BH107

[2.21]: UARTPCRS232UART82816SRAM R1=0x0480 //IOB10IOB7[P_IOB_Attrib]=R1 R1=0x0400 [P_IOB_Dir]=R1R1=0x006b //= 12.288MHz/107 = 114.84Kbps[P_UART_BaudScalarLow]=R1 //115.2KbpsR1=0x00[P_UART_BaudScalarHigh]=R1//********UART_command1UART_command2******************//R1=0xC0[P_UART_Command1]=R1[P_UART_Command2]=R1//*****************************************************************//L_begin_loopR4=0 // SRAML_loopR2=0R2=R2 LSL 4 //SBCALL F_UART_RECVR1=R1 LSL 4 //8R1=R1 LSL 4R3=R1R3=R3 and 0xFF00 //R3 =8R2=0R2=R2 LSL 4 //CALL F_UART_RECVR1=R1 and 0x00FF //R1 =8R1=R1 or R3 //R1=UART[R4++]=R1 //SRAMCMP R40x800 //SRAM2048 JNE L_loopJMP L_begin_loop//************************* UART***************************//F_UART_RECVPUSH R2R3 to [SP]L_RxRDYR2= 0x0080 //RxRDY1TEST R2 [P_UART_Command2]JZ L_RxRDY //0R1 = [P_UART_Data] //POP R2R3 from [SP]RETF //

P93 26

I/OSPCE061AI/OI/O

P_IOA4P_IOA12