SungKyunKwan Univ.

1VADA Lab.

목 차� 1. 분할 (partitioning)

� 2. Scheduling

� 3. Resource Sharing

� 4. High-Level Synthesis

SungKyunKwan Univ.

2VADA Lab.

시스템수준 solution◆Precompute physical capacitance of interconnect switching activity

◆ Supply Voltage Scaling : Lowering reduces energy, but increase delays

◆

SungKyunKwan Univ.

3VADA Lab.

Partitioning Algorithms• Graph partitioning is an NP hard problem with numerous applications. It appears in various forms in parallel computing, sparse matrix reordering, circuit placement and other important disciplines. I've worked with Rob Leland for several years on

heuristic methods for partitioning graphs, with a particular focus on parallel computing applications. Our contributions include:

• Development of multilevel graph partitioning. This widely imitated approach has become the premiere algorithm combining very high quality with short calculation times. Extension of spectral partitioning to enable the use of 2 or 3 Laplacian eigenvectors to quadrisect of octasect a graph. 뷛eneralization of the Kernighan-Lin/Fiduccia-Mattheyses algorithm to handle weighted graphs, arbitrary number of sets and lazy initiation. 뷗evelopment of terminal propagation to improve the mapping of a graph onto a target parallel architecture. 뷪he widely used Chaco partitioning tool which includes multilevel, spectral, geometric and other algorithms.

SungKyunKwan Univ.

4VADA Lab.

Chaco

• We have developed a widely used graph partitioning tool called Chaco. Unfort

unately, due to our employer's commercial interest in the software, we can only release it under a licensing arrangement (there is no fee for academic researchers). Despite these constraints, the code is used at over 150 institutions for parallel computing, sparse matrix reordering, circuit placement and a range of other applications. More information about Chaco can be found here. If you are interested in licensing the code, send your professional address and affiliation to me at bah@cs.sandia.gov

SungKyunKwan Univ.

5VADA Lab.

hMETIS• hMETIS is a set of programs for partitioning hypergraphs such as those corres

ponding to VLSI circuits. The algorithms implemented by hMETIS are based on the multilevel hypergraph partitioning scheme described in [KAKS97].

• hMETIS produces bisections that cut 10% to 300% fewer hyperedges than those cut by other popular algorithms such as PARABOLI, PROP, and CLIP-PROP, especially for circuits with over 100,000 cells, and circuits with non-unit cell areaIt is extremely fast!A single run of hMETIS is faster than a single run of simpler schemes such as FM, KL, or CLIP. Furthermore, because of its very good average cut characteristics, it produces high quality partitionings in significantly fewer runs. It can bisect circuits with over 100,000 vertices in a couple of minutes on Pentium-class workstations.

• The performance of hMETIS on the new ISPD98 benchmark suite can be found in the paper by Chuck Alpert.

http://www.users.cs.umn.edu/~karypis/metis/metis.html

SungKyunKwan Univ.

6VADA Lab.

HDL 소개 및 설계방법◈ Modeling Guidelines for HDLs

In order to achieve effcient hardware synthesis, we need to match the model of the language to that of the underlying target architecture.

Combinational Designs• Hardware design is composed of an interconnection of logic gat

es. (Boolean VHDL operators)

Functional Designs

SungKyunKwan Univ.

7VADA Lab.

HDL 소개 및 설계방법• Function designs are characterized by a mixture of synchronous a

nd asynchronous behavior, in which asynchronous event may override synchronous operation.

☞ Illustrate a functional design using an up/down counter with asynchronous set and reset

Register-Transfer Designs• RT designs correspond to the FSMD model.

• RT designs have an implicit notion of states and state transitions

Behavioral Designs• Design behavior is typically expressed in a sequential language st

yle using sequential assignment statement

SungKyunKwan Univ.

8VADA Lab.

◈ 효율적인 모델링 기법대규모 설계를 위해서는 동작적 모델링 .연산 순서를 조정한 모델링

HDL 소개 및 설계방법

+ + MUX MUX

+MUX

a adcb dbc

out out

SungKyunKwan Univ.

9VADA Lab.

HDL 소개 및 설계방법 연산수행을 줄이는 모델링

++ +

+

a adcb dbc

out

+

+

out

out = a+ b+ c + d out = (a+ b)+ (c + d)

같은 연산은 한번에 수행process(a,b,c,d) process(a,b,c,d)

begin begin

y1 <= a+b; y1 <= a+b;

y2 <= a+b+d; y2 <= y1+d;

y3 <= a+c; y3 <= a+c;

end process; end process;

SungKyunKwan Univ.

10VADA Lab.

How good is Recursive Bisection?• Horst D. Simon and Shang-Hua Teng

• Report RNR-93-012, August 1993

• The most commonly used p-way partitioning method is recursive bisection. It first "optimally" divides the graph (mesh) into two equal sized pieces and then recursively divides the two pieces.We show that,due to the greedy nature and the lack of global information,recursive bisection, in the worst case,may produce a partition that is very far from the optimal one. Our negative result is complemented by two positive ones.First, we show that for some important classes of graphs that occur in practical applications,such as well shaped finite element and finite difference meshes,recursive bisection is normally within a constant factor of the optimal one. Secondly,we show that if the balanced condition is relaxed so that each block in the partition is bounded by (1+e)n/p,then there exists a approximately balanced recursive partitioning acheme that finds a partition whose cost is within an 0(log p) factor of the cost of the optimal p-way partition.

SungKyunKwan Univ.

11VADA Lab.

SungKyunKwan Univ.

12VADA Lab.

참고문헌 VHDL 기초와 응용

– 이대영 , 조원경 , 정연모 , 오재곤 공저– 홍릉과학출판사

디지털시스템 설계 및 응용– 양오 저– 복두출판사

아날로그와 디지탈통신– 진년강 저– 청문각

전자통신– 강창언 저– 복두출판사