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數數數數數數 Experiment on Digital System Lab06: Verilog HDL and FPGA (2) 負負負負 負負負 ： stanley

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Page 1: 數位系統實驗 Experiment on Digital System Lab06: Verilog HDL and FPGA (2) 負責助教：葉俊顯 stanley

數位系統實驗Experiment on Digital System

Lab06:

Verilog HDL and FPGA (2)

負責助教：葉俊顯 stanley

Page 2: 數位系統實驗 Experiment on Digital System Lab06: Verilog HDL and FPGA (2) 負責助教：葉俊顯 stanley

112/04/20 2

Outline

Introduction to VeriLite

Programming VeriLite

Verification using VeriInstrument

Lab

Page 3: 數位系統實驗 Experiment on Digital System Lab06: Verilog HDL and FPGA (2) 負責助教：葉俊顯 stanley

112/04/20 3

Outline

Introduction to VeriLite

Programming VeriLite

Verification using VeriInstrument

Lab

Page 4: 數位系統實驗 Experiment on Digital System Lab06: Verilog HDL and FPGA (2) 負責助教：葉俊顯 stanley

112/04/20 4

Introduction to VeriLite

JTAG電源線 Reset

USB

開關

Page 5: 數位系統實驗 Experiment on Digital System Lab06: Verilog HDL and FPGA (2) 負責助教：葉俊顯 stanley

112/04/20 5

Introduction to VeriLite

Page 6: 數位系統實驗 Experiment on Digital System Lab06: Verilog HDL and FPGA (2) 負責助教：葉俊顯 stanley

112/04/20 6

Introduction to VeriLite

虛擬元件

利用 USB 溝通

Page 7: 數位系統實驗 Experiment on Digital System Lab06: Verilog HDL and FPGA (2) 負責助教：葉俊顯 stanley

112/04/20 7

Outline

Introduction to VeriLite

Programming VeriLite

Verification using VeriInstrument

Lab

Page 8: 數位系統實驗 Experiment on Digital System Lab06: Verilog HDL and FPGA (2) 負責助教：葉俊顯 stanley

112/04/20 8

Programming VeriLite

一般組合電路不會有 clk 訊號出現， clk 只會在循序電路出現

備註：此 FPGA 板子需要額外的 clk 訊號腳位設定才可以動作，所以務必記得加入

Page 9: 數位系統實驗 Experiment on Digital System Lab06: Verilog HDL and FPGA (2) 負責助教：葉俊顯 stanley

112/04/20 9

Programming VeriLite

Start compilation

Page 10: 數位系統實驗 Experiment on Digital System Lab06: Verilog HDL and FPGA (2) 負責助教：葉俊顯 stanley

112/04/20 10

Programming VeriLite

Open Assignment editor

Page 11: 數位系統實驗 Experiment on Digital System Lab06: Verilog HDL and FPGA (2) 負責助教：葉俊顯 stanley

112/04/20 11

Programming VeriLite

Show input and output pins

Page 12: 數位系統實驗 Experiment on Digital System Lab06: Verilog HDL and FPGA (2) 負責助教：葉俊顯 stanley

112/04/20 12

Programming VeriLite

Pin assignment

Double click

Page 13: 數位系統實驗 Experiment on Digital System Lab06: Verilog HDL and FPGA (2) 負責助教：葉俊顯 stanley

112/04/20 13

Programming VeriLite

Assign pin location to all inputs and outputs and add Clk

Please refer to pin.xls for pin location assignment Clock must be assigned to location Pin_28

Page 14: 數位系統實驗 Experiment on Digital System Lab06: Verilog HDL and FPGA (2) 負責助教：葉俊顯 stanley

112/04/20 14

Programming VeriLite

Start compilation

Page 15: 數位系統實驗 Experiment on Digital System Lab06: Verilog HDL and FPGA (2) 負責助教：葉俊顯 stanley

112/04/20 15

Programming VeriLite

Programming device

Page 16: 數位系統實驗 Experiment on Digital System Lab06: Verilog HDL and FPGA (2) 負責助教：葉俊顯 stanley

112/04/20 16

Programming VeriLite

Hardware setup: add USB-Blaster

Page 17: 數位系統實驗 Experiment on Digital System Lab06: Verilog HDL and FPGA (2) 負責助教：葉俊顯 stanley

112/04/20 17

Programming VeriLite

Programming device

Page 18: 數位系統實驗 Experiment on Digital System Lab06: Verilog HDL and FPGA (2) 負責助教：葉俊顯 stanley

112/04/20 18

Outline

Introduction to VeriLite

Programming VeriLite

Verification using VeriInstrument

Lab

Page 19: 數位系統實驗 Experiment on Digital System Lab06: Verilog HDL and FPGA (2) 負責助教：葉俊顯 stanley

112/04/20 19

Verification using VeriInstrument

一定要先確認 !!!

Page 20: 數位系統實驗 Experiment on Digital System Lab06: Verilog HDL and FPGA (2) 負責助教：葉俊顯 stanley

112/04/20 20

Verification using VeriInstrument

Specify the name of project file and the pin information file (*.qsf) generated by QuartusII

Page 21: 數位系統實驗 Experiment on Digital System Lab06: Verilog HDL and FPGA (2) 負責助教：葉俊顯 stanley

112/04/20 21

Verification using VeriInstrument

Check pin assignment

Page 22: 數位系統實驗 Experiment on Digital System Lab06: Verilog HDL and FPGA (2) 負責助教：葉俊顯 stanley

112/04/20 22

Verification using VeriInstrument

Add I/O device

Page 23: 數位系統實驗 Experiment on Digital System Lab06: Verilog HDL and FPGA (2) 負責助教：葉俊顯 stanley

112/04/20 23

Verification using VeriInstrument

Add I/O device

Drag here

Page 24: 數位系統實驗 Experiment on Digital System Lab06: Verilog HDL and FPGA (2) 負責助教：葉俊顯 stanley

112/04/20 24

Verification using VeriInstrument

Assign user pins

Drag here

Page 25: 數位系統實驗 Experiment on Digital System Lab06: Verilog HDL and FPGA (2) 負責助教：葉俊顯 stanley

112/04/20 25

Verification using VeriInstrument

Run FPGA

Page 26: 數位系統實驗 Experiment on Digital System Lab06: Verilog HDL and FPGA (2) 負責助教：葉俊顯 stanley

112/04/20 26

Outline

Introduction to VeriLite

Programming VeriLite

Verification using VeriInstrument

Lab

Page 27: 數位系統實驗 Experiment on Digital System Lab06: Verilog HDL and FPGA (2) 負責助教：葉俊顯 stanley

Lab

2-Bit by 2-Bit Binary MultiplierB0B1

A0

B0B1

A1

HAHA

C0C1C2C3

A1 A0

B1 B0

A0B0A0B1A1B0A1B1

C0C1C2C3

x

+

Four input, B1,B0, A1,A0

Four output, C3, C2, C1, C0

Page 28: 數位系統實驗 Experiment on Digital System Lab06: Verilog HDL and FPGA (2) 負責助教：葉俊顯 stanley

Lab

Page 29: 數位系統實驗 Experiment on Digital System Lab06: Verilog HDL and FPGA (2) 負責助教：葉俊顯 stanley

Hint

xor xor01(s, x, y);

and and01(c, x, y);

x

y

S

C

assign s=x^y;assign c=x&y;

reg s,c;

always @(x or y)

begins=x^y;c=x&y;

end

Page 30: 數位系統實驗 Experiment on Digital System Lab06: Verilog HDL and FPGA (2) 負責助教：葉俊顯 stanley

Notice

請勿在桌面建立 Project 及請勿命名中文資料夾

Device family 請確認與 FPGA Chip 符合 (EP1C6Q240C8)

Top module name & Project name 需要一致

確認 module … endmodule 為 keyword 變成藍色字體

30


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