경종민 [email protected] 1 ip & soc verification
TRANSCRIPT
2
Contents• IP Verification
– Cycle-level– Transaction Level– Testbench build-up– Hardware debugging – An example (iPROVE)
• SoC Verification– Design Flow– Multi-level, multi-lingual verification– Multiple-FPGA set-up– Debugging– An example (iSAVE)
3
IP verification• Important issues
– IP reuse– Testbench reuse– Debuggability
• Testbench issues– Various testbench support
• HLL: C/C++• HDL: Verilog and VHDL• De facto standards: SCE-MI, SystemC, OpenVera and so on
– Various levels of testbench• Transaction-level: control by command level, e.g., read/write• Cycle-level: control over pin-by-pin• Abstract-bus-level: standard on-chip networks
4
Cycle-level verification• Cycle-level verification
PCIController
DUTPCIChannel
Testbench
Testbench(C/HDL)
DUT(HDL)
FPGA part
DeviceDriver
S/W simulation part
Buffer/Pin SignalGenerator
5
Cycle-level verification• SW: Testbench
– Modeled with HDL or C language– Generate stimulus at every clock cycle– Check the result of DUT at every clock cycle
• HW: DUT– Mapped on FPGA– Stimulus are transferred through a system bus, e.g., PCI.– All signals are assigned to DUT concurrently after they are transferre
d from the SW test bench.• Operating speed
– Faster than SW simulation due to the acceleration of HDL or C model of DUT in FPGA.
– Determined by the interface requirement (number and bandwidth of signals to be transferred), and bandwidth of the interface (PCI)
6
Transaction-level verification
• Transaction-level verification
PCIController
DUTDMAChannel
Testbench
Testbench DUT
FPGA part
DeviceDriver
S/W simulation part
Tra
nsa
ctor
MainMemory
7
Transaction-level verification• SW: Testbench
– Modelled with C language– Generate stimulus and check the result of DUT– Only information enough to form the transaction is transferred to DU
T.• i.e., command, address and data
• HW: DUT and transactor– Mapped on FPGA– Transactor knows how to interpret the transaction and thence gener
ates all signals necessary for DUT.• Operating speed
– HW and SW parts are operated independently.– Faster than cycle-level verification as well as SW simulation.
8
Testbench automation• Overview
– SCE-MI– VERA– Test Builder
9
SCE-API (MI)• Standard Co-Emulation API (Modeling Interface)
– SW part implemented as C or C++, with recommendation on HW implementation
– Based on IKOS’ multi-channel co-modeling technology: TIP (Transaction Interface Portal)
– SCE-API Consortium• Founded June 2000• Aptix, CoWare, IKOS, Mentor, STMicroelectronics, Synopsys, TransEDA
– SCE-API version 1.0 modeling interface• SCE-MI v1.0 released through Open SystemC Initiative (http://www.systemc.org), April 2001
– Accellera’s Interface Technical Committee• Merged into ITC, Oct. 2001
– SCE-DI (Debug Interface) & SCE-CI (Control Interface) on progress
10
Vera• Vera
– Functional verification language for testbench description– Language specification can be obtained from OpenVera site (http://
www.opera-vera.com)– Vera Language
• Object-oriented language• Includes HDL features
– Waiting clock event– Bit data type, bit operation (extraction, concatenation)– Data expectation (‘do something when the expectation is hit’)
» 0,100 bus.ack == 1; // ack must be 1 in at least 100 cycles
– Vera Verification Environment• Commercial product from Synopsys• Vera source codes are compiled and runs with HDL simulator in which D
UT is simulated.• Additional features
– Automatic stimulus generation, Coverage analysis
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DUTVeraShell
VeraPLI
HDL Simulator
.vrl – Vera List
.vro – Vera Object
.vr – Vera Source
.vrh – Vera Header
VeraCompiler
Automatically generated by Vera compiler
Supplied by User
Vera
12
TestBuilder• Transaction-Based Verification
Functional verification in higher level of abstractionEngineer develops tests from a system level perspective– Advantages
• Enhance reusability of each component in the testbenches• Improve debugging and overage analysis
DesignDesignTVMTVM
(Transactor)(Transactor)TestsTests
Signal Signal LevelLevel
Transaction Transaction LevelLevel
TVM: Transaction Verification TVM: Transaction Verification ModelModel
13
TestBuilder• How TestBuilder Operates
Signal Signal LevelLevel
Transaction Transaction LevelLevel
TestsTests TVMTVM DUVDUV
While(){
Tx.send_packet(..);
Mem.expect_write(..);
..
}
Tx.send_packet(..){
header = “hd”;
address = 0xff0011;
data = 0xff0011;
}
C/C++/TestBuilderC/C++/TestBuilder Implementable usImplementable usinging
TestBuilder/HDLTestBuilder/HDL
HDLHDL
HDL HDL SimulationSimulation
C library (PLI/FLI)C library (PLI/FLI)
14
Specman• Functional Testbench Automation Tool by Verisity (http:
//www.verisity.com)– Its concept is similar to Vera, but starts earlier and more wid
ely used.
• Describe user specification with e language
DUT
AutomaticTestbenchGeneration
Data & TemporalChecking
CoverageAnalysis
Interface Spec & Test Plan by e
Legacy codein C/VHDL/Verilog
Specman Elite
15
Debugging feature Built-In Logic Analyzer
(BILA) DUT boundary – ports DUT internal – internal
nodes
PC
PCI iPROVE
Board
16
Hardware debugging schemes
• Low speed scheme– Operating speed: < 10MHz– There is no dedicated storage element in the device.– All debugging information is transferred to main memory or la
rge storage device at every cycle.– Readback scheme of Xilinx device is a typical example.– Usually, the scheme needs only a small number of IO pins.
• JTAG interface: 4 pins (TCK, TDI, TMS, TDO)• 8-bit parallel interface (CLK, INIT, CS, RW, D[7:0])
17
Hardware debugging scheme
• High speed scheme– Operating speed: < 100MHz– There is several dedicated elements which can be internal m
emories or external memories.– All debugging information is stored in the dedicated elements.– Typical example
• Xilinx: ChipScope• Altera: SignalTap-II
18
What is iPROVE• iPROVE is a small scale desi
gn verification tool by enabling C/C++, HDL and de facto standards interfacing API’s.
• API– Proprietary C/C++ API– Proprietary Verilog API– SCE-API/MI
Testbenchand/or
rest blocksin C, HDL
and/or SystemC
IP in
HDL/EDIF
PCI busPCI bus
19
iPROVE tool positioningRunning Speed
10Hz
100Hz
1KHz
10KHz
100KHz
1MHz
10MHz
100MHz
SW Simulator
Investment
HW Emulator
Rapid Prototype
Real Silicon
HW Accelerator
iPROVE
20
iPROVE typical usage: IP verification
DUTTransactorsTest
Transactions Signals
Transaction-based verification
IP verification without prototyping
DUT
Test
Signal information Signals
Cycle-level verification
Automaticallygenerated
module
DUT
BFM
Test
Abstract-bus-based verification
DUT
bu
s
PC
TestbechPCI
iPROVE
IPDPP
InteractiveIO
21
iPROVE typical usage: DPP
PC
Large sizedata PCI
iPROVE
DPPMulti-media
board
22
iPROVE structure• User design
– Verilog, VHDL• User testbench
– C/C++, Verilog, VHDL• OS
– Windows 2000 or XP– Linux
• De facto standards– SCE-MI/API– SystemC– OpenVera– TestBuilder
• API– C/C++
• Visual C• Borland C• GNU GCC under Cygwin
– Verilog
GUI
User application & testbench & design
SystemC OpenVera TestBuilderHDL
Simulator
iPROVE API
iPROVEDevice Driver
OS
Host Computer + PCI Card
23
iPROVE design flowTestbench
or remainingblocks of
user design
User designunder test
(HDL)
3rd PartySynthesizer
Design in EDIF
iPROVEhardware
library
iPROVE builder
3rd PartyP&R
Downloaderwith trigger
setting
Downloadabledata
3rd PartyWaveform
Viewer
Signal data inVCD format
iPROVEsetting and
BILAinformation
PCI bus
iPR
OVE
board
APIinserteddesign
iPROVE software library
24
iPROVE design flowTestbench
or remainingblocks of
user design
User designunder test
(HDL)
3rd PartySynthesizer
Design in EDIF
iPROVEhardware
library
iPROVE builder
3rd PartyP&R
Downloaderwith trigger
setting
Downloadabledata
3rd PartyWaveform
Viewer
Signal data inVCD format
iPROVEsetting and
BILAinformation
PCI bus
iPR
OVE
board
APIinserteddesign
iPROVE software library
compilation
synthesis
P&R
Mapping by running test
bench
execution Debugging with BILA
25
Cycle-level with Verilog (1/3)• A simple ALU example
alu_sim
alu
arithmetic
cmd
src1
src2
cin
result
flags
logical
cmd
src1
src2
result
flags
cmd
src1
src2
cin
clk
resetb
result
cf
vf
nf
zf
stimulus
cmd
op1
op2
carryclk
resetb
checker
cmd
op1
op2
carryclk
resetb
result
cf
vf
nf
zf
26
Cycle-level with Verilog (2/3)• Step 1: Start with EDIF of the ALU – need synthesizer• Step 2: make FPGA mapping data • Step 3: modify testbench by inserting PLI’s for iPROVE• Step 4: run the ALU with iPROVE and HDL simulator
alu_sim
alu
arithmetic
cmd
src1
src2
cin
result
flags
logical
cmd
src1
src2
result
flags
cmd
src1
src2
cin
clk
resetb
result
cf
vf
nf
zf
stimulus
cmd
op1
op2
carryclk
resetb
checker
cmd
op1
op2
carryclk
resetb
result
cf
vf
nf
zf
DUT goes to iPROVE
Testbench runs at host computer
27
Testbench example(Cycle-level)
`define CARD_ID 0
module alu_top(); // inputs and outputs … always #5 clk = ~clk;
`ifdef iPROVE alu_proxy(…)`else alu(…)`endif alu_sim(.resetb(resetb), .clk(clk), .cmd(cmd),
.src1(op1), .src2(op2), .cin(carry),
.result(result), .cf(cf), .vf(vf),
.nf(nf), .zf(zf));// other thestbench codes
Automatically generated by iPROVE
software
initial begin
$dumpfile("alu.vcd");$dumpvars();
`ifdef iPROVE$iProveOpenCard(`CARD_ID);$iProveInitCard(`CARD_ID, “ALU.tcf");$iProveLoadModuleInfoFile(`CARD_ID, "ALU.mit");$iProveCycLoadSignalInfoFile("alu", “ALU.pin");
`endifclk = 1'b0;resetb = 1'b1;repeat (2) @ (posedge clk);resetb = 1'b0;repeat (2) @ (posedge clk);resetb = 1'b1;// other testbench codes
`ifdef iPROVE$iProveCloseCard(`CARD_ID);
`endif$stop;
endendmodule
$iProveCycSignalWrite(modhl_alu, sighdl_reset,reset);$iProveCycSignalWrite(modhl_alu, sighdl_cmd,cmd);…$iProveCycClockAdvanceByModule(modhl_alu, sighdl_clk);$iProveCycSignalRead(modhl_alu, sighdl_cf, cf);$iProveCycSignalRead(modhl_alu, sighdl_vf, vf);…
*alu-proxy is image of ALU mapped on FPGA
$iProve…; system task for iProve defined as PLI routine
28
Transaction-level with C (1/3)
• A simple SSRAM example
SSRAMclk
A[7:0]
DI[31:0]
DO[31:0]
CE
OE
WE
SSRAM_TR
dut_clk
dut_addr[7:0]
dut_dw[31:0]
dut_dr[31:0]
dut_ce
dut_oe
dut_we
ifp_resetb
ifp_clk
iwp_clk
iwp_cmd_valid
iwp_cmd_read
iwp_cmd_data[31:0]
iwp_wr_wrble
iwp_wr_wr
iwp_wr_data[31:0]
iwp_rd_rdble
iwp_rd_read
iwp_rd_data[31:0]
Use
r’s
test
ben
ch in
C
iPRO
VE A
PI
and D
evic
eD
rive
r La
yer
iPRO
VE P
CI
Inte
rfac
eLa
yer
DUT
TRANSACTOR
29
Transaction-level with C (2/3)
• Step 1: Start with EDIF of the SSRAM – need synthesizer• Step 2: make FPGA mapping data • Step 3: modify testbench by inserting PLI’s for iPROVE• Step 4: run the SSRAM with iPROVE and HDL simulator
SSRAMclk
A[7:0]
DI[31:0]
DO[31:0]
CE
OE
WE
SSRAM_TR
dut_clk
dut_addr[7:0]
dut_dw[31:0]
dut_dr[31:0]
dut_ce
dut_oe
dut_we
ifp_resetb
ifp_clk
iwp_clk
iwp_cmd_valid
iwp_cmd_read
iwp_cmd_data[31:0]
iwp_wr_wrble
iwp_wr_wr
iwp_wr_data[31:0]
iwp_rd_rdble
iwp_rd_read
iwp_rd_data[31:0]
Use
r’s
test
ben
ch in
C
iPRO
VE A
PI
and D
evic
eD
rive
r La
yer
iPRO
VE P
CI
Inte
rfac
eLa
yer
DUT
TRANSACTOR
DUT & transactor goes to iPROVE
Testbench runs at host computer
30
Testbench example(Transaction-level)
#include “iprove.h”int main(int argc, char** argv) { // other codes
iProveOpenCard(card_id); iProveInitCard(card_id, tcf); iProveLoadModuleInfoFile(card_id, mit); iProveGetModuleHandle(instance_name, &module_handle); iProveAllocReadBuffer(module_handle, sbm_size); iProveAllocWriteBuffer(module_handle, sbm_size);#ifdef BILA iProveBILAConfig(card_id, trg); iProveBILATrigOn(card_id);#endif iProveStart(card_id); TestBench();#ifdef BILA iProveBILAUpload(card_id, dmp); bila_info.cid = card_id; bila_info.dump_filename = dmp; bila_info.signallist_filename = lst; WithCheck(iProveDump2Vcd(&bila_info, 1, vcd);#endif iProveStop(card_id); iProveCloseCard(card_id); return 0;}
void TestBench(void) { // other codes
iProveCmdWrite(module_handle, &cmd, 1); iProveDataWrite(module_handle, pbuf, num, &tmp); // other codes
iProveCmdWrite(module_handle, &cmd, 1); iProveDataRead(module_handle, pbuf, num, &tmp); // other codes
}
31
Performance comparisonsSpeed improvement of iPROVE
1 1 1 1
2.95
28.1338.35
47.05
9.39
48.4557.21
68.94
1161.4
648.9
1393.45
2053.2
1
10
100
1000
10000
IDCT FPACC0 FPACC1 FPACC2
Sp
eed
up
in lo
g-s
cale
ModelSim
iPROVE with ModelSim
iPROVE with Cycle API
iPROVE with TransactionAPI
IDCT: 59K gatesFPACC0: 56K gatesFPACC1: 104K gatesFPACC2: 208K gates
32
iPROVE performance• iPROVE provides outstanding s
peed-up over x2000.• Example
– FPACC2 (Floating-point number calculation IP)
– Gate count: 208,479– Logic usage: 99% of XCV1000E
x47 x69
x2053
x1
ModelSim iPROVE iPROVE iPROVEwith ModelSim with Cycle-
Level C-API
with Transaction-Level C-API
33
iPROVE-Summary• Easy to use and fast setup ti
me to emulation– No or minor source modifica
tion– The same testbench for sim
ulation and emulation• Various verification mode
– Cycle, transaction and abstract bus modes
• Powerful debugging– BILA (Built-in Logic Analyzer)
as a real hardware logic analyzer
• High-performance interface to S/W side– High-speed DMA feature– High to low level languages
such as C/C++, Verilog and VHDL
• Open interface system– API layer provides easy-to-int
erface mechanism to de facto standards
• Scalability – Multiple iPROVE cards as we
ll as various gate count options
34
SoC Verification• Key technologies in SoC Verification• Early/Consistent Verification Environment• Progressive Refinement• Multi-level, Multi-lingual Verification
35
ASIC Verification MethodsRunning Speed
10Hz
100Hz
1KHz
10KHz
100KHz
1MHz
10MHz
100MHz
SW Simulator
Investment
HW Emulator
Rapid Prototype
Real Silicon
HW Accelerator
Ideal VerificationIdeal Verification
SolutionSolution
Make it fasterMake it faster
Make it cheaperMake it cheaper
36
What’s the point in SoC Verification?
• Mixture of SW and HW– Make it easier to cooperate with Processor Model such as IS
S or BFM
• Mixture of pre-verified, not-verified components– Make it easier to utilize legacy IPs already verified
• Mixture of different language, different abstraction level– Provide common interface structure between SoC component
s
37
Canonical SoC design flowSystemSpec.
SystemDesign
HW/SWPartitioning
HWDevelopment
SWDevelopment
HW refinement(UT->T->RTL)
Gate
HW IP
SW IP
SoftwareVerification
FunctionalVerification
Gate-LevelVerification
HW-SWCo-Design
HW-SWCo-
Verification
SW refinement(RTOS
mapping)
Final code• Emulator
– In-system emulator– HW-SW co-debugging
38
Tools for HW-SW Co-Verification
– HW-SW co-simulation– ISS– RTOS simulator
HW/SWPartitioning
HWDevelopment
SWDevelopment
HW refinement(UT->T->RTL)
SoftwareVerification
FunctionalVerification
Co-Verification
SW refinement(RTOS
mapping)
HW-SW
– High-level synthesis– Testbench automation– IP accelerator
SystemSpec.
SystemDesign
HW/SW
HW IP
SW IP
39
Tools for System-level
• System-level design (Performance analysis tools)– Hot-spot analyzer– High-level cycle count estimation– High-level power analysis– High-level chip area estimation– On-chip-bus traffic estimation
SystemSpec.
SystemDesign
HW/SWPartitioning
HW IP
SW IP
HW-SWCo-Design
40
Verification Environment• Early test-bench setup
– Accurate and fast test-bench setup in early design stage greatly reduces verification time and efforts
• Consistent test-bench utilization– Once the test-bench is built up, it must be consistently reuse
d in the following design steps
• In-system test bench– The test bench must be switchable between SW simulation a
nd in-system verification to cover all corner cases.
41
In-System Verification
spec.spec. RTLRTL gategatesiliconsilicon
boardboard
design synthesis manufacture
functional verification formal verification test pattern
In-System Behavioral Level VerificationIn-System Behavioral Level Verification
Integrationtest
In-System Gate Level VerificationIn-System Gate Level Verification
42
Flexible Verification Environment
C TestBench
C Model
In-SystemTest Bench
C Model
HDL TestBench
HDL Design
HDL TestBench
Gate LevelDesign
Gate LevelDesign
In-SystemTest Bench
C TestBench
C Model
HDL TestBench
HDL DesignGate Level
Design
In-SystemTest Bench
Conventional
VerificationEnvironmen
t
FlexibleVerificationEnvironme
nt
43
Progressive refinement• With the advent of design reuse methodology for System-On-a-C
hip designs, a mixture of C, HDL, EDIF netlist and IP core blocks is required to be verified together as one system.
• For a large design, it is necessary to verify each design blocks/modules one after another until whole design is verified.
• IP has to be prepared in various abstraction levels in order to support progressive refinement process.
uPCore
SRAM
FLASH
D-Cache USB
MPEG
SRAM
FIFO
Logic
A typical SoC chip
UTF
TFIncremental/progressiverefinement
BCA
RTL
EDIF
44
Multi-Level & Multi-Lingual
UT
BCA
CA
TA
EDIF(gate-level
netlist)
HDL(VeilogVHDL)
SystemC(HW)
C/C++(HW)
gate
RTL
Behavioral
AlgorithmFunctional
C/C++(SW)
Mem
ory
(20
~5
0%
)
MultipleProgrammable
Cores (20%)
other IPs(>20%)
Customcontents(15~20%)
level ofabstraction
UT: untimed, BCA: bus cycle accurateCA: cycle accurate, TA: timing accurateRTL: register transfer level
45
Supporting Multi-Language • Simulation Vehicle
– HDL Simulator– User C process ( C/C++/SystemC model for HW or SW )– ISS for embedded processor core– Test description language (Vera, TestBuilder)
• Emulation Vehicle– FPGA containing one or more IP’s (enables gate-level IP verification)– FPGA interfacing with target system (enables in-system verification)
• Communication channel between vehicles– IPC (inter-process communication) for designs simulated in multiple pr
ocesses– Dedicated device driver for designs mapped in FPGAs
46
Supporting Multi-Level • Bridging abstraction gap
– Using transactor
– Using cycle-level transactor
TransactorTransaction
-LevelC/HDL Model
CycleAccurate
HDL/EDIF Model
Cycle-LevelTransactor
CycleAccurate
C/HDL Model
CycleAccurate
Model
Read Channel
Write Channel
Read Channel
Write Channel
CycleAccurate
API
47
TIE
EDIF sessions
HDL sessionsC sessions
Designin EDIF
Designin EDIF
Transactor Transactor
Target board
I/F protocol I/F protocol
Inter-Lingual Communication
Designin C
Designin SystemC
Transactor Transactor
Designin Verilog
Designin VHDL
Multi-Level & Multi-Lingual
48
iSAVE-MP & MPEG2/4iSAVE-MP main iSAVE-MP TIM
MPEG Board
Decoded image
GUI windows
49
SoC model with ARM CCM
ARMCCM
ARMCCM
Memorymodel
Memorymodel
IPmodels
IPmodels
AMBAmodel
AMBAmodel Address DecoderAddress Decoder
IPin HDL
IPin HDL
Buswrapper
Buswrapper
Debugger
ILC(Inter-lingual Communication)ILC(Inter-lingual Communication)
50
Using Multiple FPGA’s• Using multiple FPGAs
– Partitioning into multiple FPGAs– Bus split
IP0IP0 IP1IP1 IP2IP2 IP3IP3
TransactorTransactor
ARM ISSARM ISS Memory ModelMemory Model
TransactorTransactor
Host Processor
FPGA1 FPGA2
Bus SplitLogic
51
Debugging in Multi-Level• Traditional debugging tools
– Design in emulation vehicle• Logic analyzer
– Design in simulation vehicle• Source-level debugger• Waveform viewer
• Challenges in SoC– How to manage waveforms from different
abstraction level– How to manage trigger conditions– How to probe out internal signals of designs in
emulation vehicles
52
Debugging in Multi-Level• Built-in logic analyzer
– Built-in logic analyzer enables the designer to watch what is actually going on.
– Built-in logic analyzer samples the states of the DUT and stores them in the external dump memory. (non-intrusive)
FPGA
DesignUnderTest
External Dump Memory VCD
Post Processing
Upload
Download Trigger
Configure FPGA
RunBuilt-InLogic
Analyzer
53
Debugging in Multi-Level• Built-in logic analyzer
– Triggering condition is dynamically configured.– After the emulation is over, the dump data in the
external memory is read and processed to generate VCD file.
$dateFri Dec 6 22:50:56 2002
$end$version
4.10$end$timescale
100ps$end$scope module BILA $end$var reg 32 ! user_data $end$var reg 1 “ write_en $end$var reg 4 $ mode $end…
VCD file
Waveformviewer
54
Debugging in Multi-Level• Probing internal nodes
– Sometimes the designer wants to watch internal nodes in his design.
– Internal node probing enables this by wiring-out the internal nodes to the boundary of the DUT top block.
DUTBuilt-InLogic
Analyzer
Top block
Sub-block
Internal nodeExternalDump
Memory
55
Debugging in Multi-Level• Monitoring software variables
– Software dump data is merged with hardware dump data (Built-In Logic Analyzer) to generate unified waveform.
– The waveform contains both hardware and software debugging information.
Built-In Logic AnalyzerDump data
with timing information
Software variableDump data
with timing information
dump2vcdVCD with both
Hardware and softwareDebugging information
56
UnifiedVCD
dump2vcd
Using Multiple FPGAs• Synchronous Built-In Logic Analyzer
– When the design is partitioned into multiple FPGAs, Built-In Logic Analyzer(BILA) in each FPGA samples the internal state of each FPGA.
– All the dump data are merged to provide the user a unified and synchronized waveform.
Dump data#n
Dump data#3Dump data
#2Dump data
#1
FPGA #n
DUT BILAFPGA #3
DUT BILAFPGA #2
DUT BILAFPGA #1
DUT BILA
57
Using Multiple FPGAs• Multiple FPGAs with multiple Processes
– BILA in each FPGA samples FPGA states.– SVA in each process samples program states.– All of the dump data are merged
58
UnifiedVCD
Using Multiple FPGAs
dump2vcd
Dump data#n
Dump data#3Dump data
#2Dump data
#1
FPGA #n
DUT BILAFPGA #3
DUT BILAFPGA #2
DUT BILAFPGA #1
DUT BILA
• Multiple FPGAs with multiple Processes
Dump data#n
Dump data#3Dump data
#2Dump data
#1
Process #m
SVAProcess #3
SVAProcess #2
SVAProcess #1
SVA