MMUhttp://10.1.4.123mmu.pdf

C y=a*(b+c) ARMADR R4,b LDR R0,[R4] ADR r4,c LDR r1,[r4] ADD r2,r0,r1 ADR r4,a LDR r0,[r4] MUL r2,r2,r0 ADR r4,y STR r2,[r4]

ARM Load/Store ARM ARM ARM ARM XScale

5.2.2 ARMARM{cond}CPSR ARMNZCV

5.2.3 Load/Store Load/Store Load/Store Load/Store Load/Store PLD

Load/Store

ARM(8)(32): 1zero offset LDR | STR {}{B}{T} Rd ,[Rn ] ((Rn))Rd Rn 2pre-indexed offset LDR | STR{} {B} Rd , [Rn , < offset >] {!} ;Rn+ offsetRd RnRnRnR15 3programrelative LDR | STR{} Rd , LABEL LABELRd PCPCRn 4post-indexed offset LDR | STR{} {B} {T} Rd , [Rn ], < offset > RnRnRnRnR15LDR Rd , [Rn ] , offset ((Rn))Rd(Rn)+offsetRn

1) R0 LDR R1 , UARTADD ; UARTR1 STRB R0 , [R1] UARTADD & &1000000 UART 2) LDR R8[R10] (( R10))R8 LDRNE R2[R5#960] Z1((R5)+960)R2(R5)+960R5 STR R2[R9#consta-struc] ; consta-struc1~4095 STRB R0[R3-R8ASR #2] R0(R3-R8/4)R0R3R8 STR R5[R7]#-8 R5(R7) R7-8R7 LDR R0localdata ; lacaldata

Load/Store ARM168 1zero offset LDR | STR{} H | SH | SB Rd,[Rn]2pre-indexed offsetLDR | STR{} H | SH | SB Rd , [Rn , ] {!}3pregramrelatveLDR | STR{} H | SH | SB Rd , LABEL4post-indexed offsetLDR | STR{}H | SH | SB Rd , [Rn ], H | SH | SB SH LDR H SB LDR

LDREQSH R11[R6] R11[R6]1632 LDRH R1[R0#22] R1[R0+22]1632 STRH R4[R0+R1] R0+R1R0 LDRSB R6constf constf

Load/Store ARM(64) 1zero offset LDR | STR{} D Rd,[Rn]2pre-indexed offsetLDR | STR{} D Rd , [Rn , ] {!}3pregramrelatveLDR | STR{} D Rd , LABEL4post-indexed offsetLDR | STR{} D Rd , [Rn ],

Load/Store R0~R15 1 LDM | STM{} Rn{!} , 2SPSRCPSRPC LDM {}< mode > Rn{!} , ^ 3PC LDM | STM{}< mode > Rn , ^

1 STMFD R13! , {R0-R2 , R14} LDMFD R13! , {R0-R2 , PC} 2 LDMIA R8{R0R2R9} ; ((R8))R0 ; ((R8)+4)R2 ; ((R8)+8)R9 STMDB R1{R3R6R11R12} ; (R3)R1- 4 ; (R4)R1- 8 ; (R5)R1- 12 ; (R6)R1- 16 ; (R11)R1- 20 ; (R12)R1- 24 ; (R1)- 24R1 STMFD R13{R0R4-R7LR} LDMFD R13{R0R4-R7PC} ; 3 SUB1 STMFD SP! , {R0-R2 , R14} R0~R2 ; BL label ; ; LDMFD SP! , {R0-R2 , R15} R0~R2

PLD Cache PLDPreLoaDPLDPLD [Rn{offset}]Rn Offset Rn PLD [R9#-2481]

SWP{} {B} Rd , Rm , Rn ((Rn))Rd , (Rm)Rn; nm ,d , ;d=m, ,Rm((Rn))

5.2.4 ARM QADDQSUBQDADDQDSUB

ARMflexible second operandOperand2

1# immed-8r 8pattern3202482628300xFF0xFF0000xF000000F0x1010xFF040xFF0030xFFFFFFFF 2Rm {, shift} Rm ARMRm Shift Rm

32 { } {S} Rd , Rn , Operand2 ADDSUBRSBADCSBCRSCANDORREORBIC MOVMVNCMPCMNTSTTEQ

1 ADD R2,R1,R3 R1+(R3)R2 2 SUBSR2, R2, #1 ; R2-1R2 BEQ LABEL ; 0LABEL 3 R05ADD R0, R0, R0, LSL #2 ; (R0)*5R0 4 R010 ADD R0, R0, R0, LSL #2 ; (R0)*10R0 MOV R0, R0, LSL #1

CLZCount Leading ZerosRmleading zerosRd032[31]10 CLZ {} Rd , Rm RdARMRdR15 Rm

QADDQSUBQDADDQDSUB DSP22 {} Rd, Rm, RnQADDQSUBQDADDQDSUB Rd Rm,Rn

DSP//-231~231-1//231-1231-1/-231-231 QDADDQDSUBSATRm+SATRn*2QSAT

QADD R0R1R9 ;SAT(R1+R9)R0QDSUBLT R9R0R1 ;SAT(R0-SAT((R9)*2))R9

5.2.5ARMARMARMThumbBBLBXBLX /BXBLX

/ BBL32MBLR14 B{L} {} Label

BLBranch and LinkR14LRLabelBLL=1 , PCR14,PC+offset PC BBL22532MLabel

1) CMP R0 , #5 ; R05 BLT SUB1 SUB1 BGE SUB2 SUB2 2) BL SUB SUB ; SUB . ; MOV PC , R14 ; 3) MOV R0 , #10 ; LOOP SUBS R0 , #1 ; 1 BNE LOOP ; 0 , . ;

BXBLX BXBLXThumbARMThumbThumbARM 1 B{L}X {} Rm 2 BLX RmRm[0]Rm[0]1CPSRTThumbRm[0]0[1]1

1 BX R0 ; R0 ; R0[0]1 Thumb : 2 ThumbCODE32 ARM BLX TSUB ; Thumb TSUBCODE16 ; Thumb TSUB ;Thumb TSUB BX R14 ; ARM

5.2.6ARM ARMCPU

ARM16 ARM CDP MRC ARM MCRARM LDC STC

CDPCDP2(CDPCoprocessor Data operation) CDP {} CP#, opcodel, CRd, CRn, CRm{,opcode2} CDP2 CP#, opcodel, CRd, CRn, CRm{,opcode2} CP# pnn0~15 Opcodel CRn,CRm,CRn opcode2

CDP p1,10,c1,c2,c3 ;1C2C310 C1

CDPEQ p2,5,c1,c2,c3,2 ;Z12C2C352C1

LDCSTC 1 LDC | STC{} {L} , CRd , [Rn ] 2 LDC | STC{} {L} , CRd , [Rn , #offset ]{!} LDC2 | STC2 , CRd , [Rn , #offset ]{!} 3 LDC | STC{} {L} , CRd , [Rn] , #offset LDC2 |STC2 , CRd , [Rn] , #offset

1 LDC p6 , CR1 , [R4] ; 6CR1 R4 2 LDC p6 , CR4 , [R2 , 4] ; 6CR4R2+4 3 STC p8 , CR8 , [R2 , #4] ! ; 8CR8R2+4 R2=R2+4 4 STC p6 , CR9 , [R2] , #-16 ; 6CR9 R2 R2=R2-16

MRCMRC2 MCRMCR2 ARM 1ARM MRC{} , , Rd , CRn , CRm { , } MRC2 < CP#> , , Rd , CRn , CRm { , } 2ARM MCR{} < CP#> , , Rd , CRn , CRm { , } MCR2 < CP#> , , Rd , CRn , CRm { , }CDPCDP2

1 MRC p15 , 5, R4 , C0 , C2, 3 ; 15C0C253CPU42 MCR p14 , 1, R7 , C7 , C12, 6 ; 14CPU7 1614C12

MCRRMRRC 2ARM MRRC{} < CP#>, , Rd, CRn, CRmMCRR{} < CP#>, , Rd, CRn, CRm

5.2.7ARM SWI (v5T)

MRS{} Rd , CPSR | SPSR RdRdR15R=0CPSRR=1SPSR MRSMSRPSRQSPSR

MRS R0 , CPSR CPSRR0 MRS R3, SPSR SPSRR3

MSR{} CPSR_f | SPSR_f , < #immed_8r > MSR{} CPSR_ | SPSR_ , RmC: PSR07X: PSR815SPSR1623F: PSR2431immed_8r832Rm

1 NZCV MSR CPSR_f , #&f0000000 80 2 CNZV MRS R0 , CPSR CPSRR0 ORR R0 , R0 , #&20000000 ; R029 MSR CPSR_f , R0 R0CPSR

3 IRQ MRS R0 , CPSR ; CPSRR0 BIC R0 , R0 , #&1f R05 ORR R0 , R0 , #&12 IRQ MSR CPSR_c , R0 R0CPSR

SWI SWI{} immed_24immed_240-224-124 SWI0x08CPSRSPSRSWI

(v5T)BKPT immed_16 immed_160~6553616 BKPTARM v5

5.2.8XScale MIA MIAPH MIAxy MARMRA

MIA MIAMLAMIAacc0 MIA {} acc0 , Rm , Rs Rs Rm acc0 0

MIAPH MIAPH321616acc0 MIA {} acc0 , Rm , Rs Rs Rm acc0 0

MIAxy MIAxy16x=1Rm16x=0Rm16y=1Rs16y=0Rs16 MIAxy{} acc0 , Rm , Rs Rs Rm xy 00 MIABB 01 MIABT 10 MIATB 11 MIATT acc0 0

MARMRA ARM2MAR{} acc0 , RdLo , RdHi MRA{} RdLo , RdHi , acc0 RdHi RdLo acc0 0MAR RdLo acc0[310]RdHiacc0[3932]MRA acc0[310] RdLoacc0[3932]RdHi

ARM ARM ARM Thumb ARM

5.3 Thumb 015310ADDS r2,r2,#1ADD r2,#132-bit ARM 16-bit Thumb Thumb 16-bit ARM65% ARM ThumbARMThumbBX

ARMThumbTThumbARM7TDMICPSRTThumbARMThumbARMARMARMThumbBXThumbThumbARMThumb BXARMThumbARMThumbARMThumbARMThumbR0~R7R13R14R15PCThumbR8~R15CPSR