VHDL 3.1 VHDL3.2 VHDL3.3 VHDL3.4 VHDL3.5 VHDL

3.1.1 VHDLData ObjectsConstant width: integer := 7;Constant Vcc: REAL:=5.0; Constant D2:Std_Logic_Vector(width Downto 0):= 0000;LibraryEntityArchitectureProcess1ConstantConstant = 3.1 VHDL

2 Signal [=] Signal A : Std_logic_vector(3 Down to 0) := 0000;

3 Variable [=] Variable a: integer := 0; := a := b and c;

Signal clk: std_logic; Variable data: std_logic_vector(7 downto 0);Constant width: integer :=7 ;clk

Architecture abc of example is signal tmp:std_logic;Begin process(a,b,c) begin tmp

3.1.2 VHDL 1 1Boolean stdstandard FALSETRUE 2Bit stdstandard 01

3Bit_Vector stdstandard Signal A: bit_vector(0 to 7);Signal B: bit_vector(7 downto 0); A

4Std_Logic IEEEstd_logic_1164 Library IEEE;Use IEEE.std_logic_1164.all;

bitVHDLBIT

UX0011ZWL0H1-

5Std_Logic_vector ieeestd_logic_1164 Bit_VectorStd_Logic_vectorBIT01Std_LogicSignal A: STD_LOGIC_VECTOR(0 to 7);Signal B: STD_LOGIC_VECTOR (7 downto 0); A

Variable a , b : std_logic;Signal data : std_logic_vector(0 to 3);a: = 1;b: = 0;data

2. Signal data : std_logic_vector(0 to 3);data(1 to 2)

1Integer

stdstandard-231~231

Signal day: integer range 0 to 31;

Variable a,b,c: interger;

C=a+b;

0

0

Unsigned(0110) +6+ 10Unsigned(1010)signed(0110)+6signed(1010)-22UnsignedSignedSignedUnsignedIEEEstd_logic_arith

(STRING)

VARIABLE string_yin : STRING (1 TO 7 ) ;string_yin := "a b c d" (CHARACTER)A a

Aa

(TIME)TYPE time IS RANGE 2147483647 TO 2147483647 units fs ; -- VHDL ps = 1000 fs ; -- ns = 1000 ps ; -- us = 1000 ns ; -- ms = 1000 us ; -- sec = 1000 ms ; -- min = 60 sec ; -- hr = 60 min ; -- end units ;Q

TYPE 1TYPE IS(12);TYPE week IS (sun,mon,tue,wed,thu,fri,sat);2 TYPE IS ARRAY OF TYPE word IS ARRAY (0 TO 7) OF STD_LOGIC;

3Record TypesC Type iocell is record Enable :bit; Data :bit_vector(7 downto 0); end record; singal bus : iocell; bus.Enable

SUBTYPE IS SUBTYPE data IS STD_LOGIC_VECTOR(7 DOWNTO 0); SUBTYPE digit IS INTEGER RANGE 0 TO 9;

bitbit_vectorboolean std_logicstd_logic_vector3.1.3 VHDLoperator

=

/=

=

AND

BITBOOLEANSTD_LOGIC

OR

BITBOOLEANSTD_LOGIC

NAND

BITBOOLEANSTD_LOGIC

NOR

BITBOOLEANSTD_LOGIC

XOR

BITBOOLEANSTD_LOGIC

XNOR

BITBOOLEANSTD_LOGIC

NOT

BITBOOLEANSTD_LOGIC

+

signal d1,d2,s : integer; SIGNAL a bc : STD_LOGIC_VECTOR (3 DOWNTO 0) SIGNAL defg : STD_LOGIC_VECTOR (1 DOWNTO 0) SIGNAL hIjk : STD_LOGIC SIGNAL lmnop : BOOLEAN ... s

/

=

/=

=

AND

BITBOOLEANSTD_LOGIC

OR

BITBOOLEANSTD_LOGIC

NAND

BITBOOLEANSTD_LOGIC

NOR

BITBOOLEANSTD_LOGIC

XOR

BITBOOLEANSTD_LOGIC

XNOR

BITBOOLEANSTD_LOGIC

NOT

BITBOOLEANSTD_LOGIC

+

+

&

*

()

/

()

MOD

REM

SLL

BIT

SRL

BIT

SLA

BIT

SRA

BIT

ROL

BIT

ROR

BIT

**

ABS

Variabe data: std_logic_vector(3 donto 0) :=1011;Data SLL 1;--0110Data SRL 3;--0001Data ROL 1;--0111

c

ENTITY IS [GENERIC] [PORT]END ENTITY ENTITY or2 IS PORTabIN STD_LOGIC; C: OUT STD_LOGIC); END ENTITY or2 3.2 VHDL3.2.1

ENTITY ISEND ENTITY I/OI/OGENERICGENERIC [CONSTANT] [IN] [:= ]]

GENERIC trisetfallTIME:=1ns; Addrwidth:INTEGER:=16);PORT(a0, a1 : IN STD_LOGIC; Add_bus:OUT STD_LOGIC_VECTOR(addrwidth-1 DOWNTO 0); trisetfallAddrwidthAddrwidth

PORT PORT

clk DA 1IN loadresetenableclkaddress

2OUT 3INOUT

4BUFFER

OutBufferEntity test1 is port(a: in std_logic; b,c: out std_logic );end test1;

architecture a of test1 is begin b

VHDLPCI/DMA

3.2.2 ARCHITECTURE OF IS []BEGIN []END ;

(behavioral)(dataflow)(structural)

PROCESSArchitecture behavioral of eqcomp4 is begincomp: process (a,b) beginif a=b then equal

RTL

ab

Architecture dataflow2 of eqcomp4 is beginequal

:

Component [ IS ] [ Port ]End Component ;

: Port Map

1 Port Map1, 2,;architecture struct of eqcomp4 isCOMPONENT XNOR2PORT(A,B:IN STD_LOGIC; C:OUT STD_LOGIC);END COMPONENT;COMPONENT and4PORT(a,b,c,d:IN STD_LOGIC; q:OUT STD_LOGIC);END COMPONENT; SIGNAL X:STD_LOGIC_VECTOR(0 TO 3);begin U0:xnor2 port map(a(0),b(0),x(0)); U1:xnor2 port map(a(1),b(1),x(1)); U2:xnor2 port map(a(2),b(2),x(2)); U3:xnor2 port map(a(3),b(3),x(3)); U4:and4 port map(x(0),x(1),x(2),x(3),equal);end struct;

1 Port MapA=>A1, B=>B1,;architecture struct of eqcomp4 isCOMPONENT XNOR2PORT(A,B:IN STD_LOGIC; C:OUT STD_LOGIC);END COMPONENT;COMPONENT and4PORT(a,b,c,d:IN STD_LOGIC; q:OUT STD_LOGIC);END COMPONENT; SIGNAL X:STD_LOGIC_VECTOR(0 TO 3);begin U0:xnor2 port map(A=>a(0),B=>b(0),C=>x(0)); U1:xnor2 port map(B=>b(1),A=>a(1),C=>x(1)); U2:xnor2 port map(A=>a(2),B=>b(2),C=>x(2)); U3:xnor2 port map(A=>a(3),B=>b(3),C=>x(3)); U4:and4 port ap(a=>x(0),b=>x(1),c=>x(2),d=>x(3),q=>equal);end struct;

processProcess [:] Process [()] []Begin

End Process [];(Sensitivity list)

architecture m2 of examle isbegin

A:Processa,bbegin c

3.2.3 VHDL Procedure Function

PACKAGE IS[]END ;PACKAGE BODY IS[]END

(Function)Function Return Function Return IS Begin END Function

LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;PACKAGE hanshu IS -- FUNCTION max( a,b : IN STD_LOGIC_VECTOR) -- RETURN STD_LOGIC_VECTOR ; FUNCTION func1 ( a,b,c : REAL ) -- RETURN REAL ; FUNCTION "*" ( a ,b : INTEGER ) -- RETURN INTEGER ;END ;PACKAGE BODY hanshu IS FUNCTION max( a,b : IN STD_LOGIC_VECTOR) -- RETURN STD_LOGIC_VECTOR IS BEGIN IF a > b THEN RETURN a; ELSE RETURN b; END IF; END FUNCTION max; --FUNCTIONEND; --PACKAGE BODY

LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE WORK.hanshu.ALL ; ENTITY axamp IS PORT(dat1,dat2 : IN STD_LOGIC_VECTOR(3 DOWNTO 0); dat3,dat4 : IN STD_LOGIC_VECTOR(3 DOWNTO 0); out1,out2 : OUT STD_LOGIC_VECTOR(3 DOWNTO 0) ); END; ARCHITECTURE bhv OF axamp IS BEGIN out1

ProcedureProcedure Procedure IS Begin END Procedure

LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;PACKAGE hanshu IS -- procedure max( signal a,b: IN STD_LOGIC_VECTOR; signal c: out std_logic_vector)--END ;PACKAGE BODY hanshu IS procedure max( signal a,b: IN STD_LOGIC_VECTOR)-- signal c: out std_logic_vector) is BEGINc

LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE WORK.hanshu.ALL ; ENTITY axamp IS PORT(dat1,dat2 : IN STD_LOGIC_VECTOR(3 DOWNTO 0); dat3,dat4 : IN STD_LOGIC_VECTOR(3 DOWNTO 0); out1,out2 : OUT STD_LOGIC_VECTOR(3 DOWNTO 0) ); END;ARCHITECTURE bhv OF axamp IS BEGINmax(dat1,dat2,out1);max(dat3,dat4,out2);END;

INOUTINOUTIN()

VHDL

ARCHITECTUREPROCESSFUNCTIONPROCEDURE3.3 VHDL

3.3.1 VHDLProcessFunctionProcedureCASEIFLOOP

VHDL1

VHDLarchitecture abc of example issignal c :STD_LOGIC;beginPROCESS(a,b)beginc

VHDL2

:=

VHDLarchitecture abc of example isbeginPROCESS(a,b)variable tmp:std_logic;begintmp:=a and b;out

VHDL3CASE

Case Is WHEN =>; WHEN =>; WHEN OTHERS =>; End case;CASECASEOTHERS

architecture abc of example is signal sel:std_logic_vector(1 downto 0);beginsel f f f f null;end case;end process;end abc;others? VHDL

VHDL4IF1IF THEN END IF2IF THEN ELSE END IF3IF 1 THEN ELSIF 2 THEN ELSE END IFIF

architecture abc of example is signal sel:std_logic_vector(1 downto 0);beginsel

VHDL5LOOPFOR

FOR IN LOOPEND LOOPLOOPLOOP

VHDL 8architecture abc of example isbeginPROCESS(a)variable tmp:std_logic;begintmp:=0;FOR i IN 0 to 7 LOOPtmp:=tmp XOR a(i);END LOOP;Y

VHDL5LOOPWHILE

WHILE LOOPEND LOOP

VHDL 8architecture abc of example isbeginPROCESS(a)variable tmp:std_logic;begintmp:=0;i:=0;WHILE (i

3.3.2 VHDLBLOCK

VHDL1PROCESS

PROCESS12 []BEGINEND PROCESS

VHDLarchitecture abc of example issignal c :STD_LOGIC;beginJC1:PROCESS(a,b)begin c

Library ieee;Use ieee.std_logic_1164.all;Entity example isport(a,b:in std_logicc,d:out std_logic);End example;architecture m2 of examle isbegin

Processa,bbegin

c

architecture m2 of examle isbegin

A:Processa,bbegin c

Library ieee;Use ieee.std_logic_1164.all;Entity example isport(a,b:in std_logicc,d:out std_logic);End example;architecture m2 of examle isbegin

Processa,bvariable tmp1,tmp2:std_logic;begintmp1:=a and b;tmp2:=a or b;c

Process(sel,a,b)Beginf

8Library ieee;Use ieee.std_logic_1164.all;Entity jojy is port(a:in std_logic_vector(0 to 7);q:out std_logic);End jojy;Architecture behave of jojy isBeginprocess(a)variable tmp:std_logic;begintmp:=0;for i in 0 to 7 loop tmp:= tmp xor a(i);end loop;q

VHDL2

VHDLarchitecture abc of example issignal c :STD_LOGIC;beginx

VHDL3

VHDL 8-3architecture abc of example isbeginout

VHDL4

WITH SELECT

VHDL 41architecture abc of example isbeginsel

VHDL5BLOCK

BLOCKBEGINEND BLOCK

VHDLarchitecture abc of example isbegin a1:BLOCK signal x:std_logic;beginx