VHDL3.1 3.2 VHDL 3.3 VHDL3.4 VHDL3.5 VHDL3.6

3.1 VHDLHDL: Hardware Description LanguageVHDL VHSIC Hardware Description Language Very High Speed Integrated CircuitIEEEIEEE std 1076-1987, 1076-1993, 2 VHDL-AMS ( AMS -- Analog and Mixed Signal )

VHDL: C CSystemC, SpecC RTL: AHPL, DDL, CDL LDL: GFHL, ndl, : Splice: Spice: CIF, LEF, DEFVHDLVERILOGEDIFVHDL-AMS

3.2 VHDL 3.2.1 1+ Entity; Architecture 2 1 1 EntityArchitectures

3.1 1. entity)entity Half_Adder is port ( X: in bit ; Y: in Bit ; Sum : out bit ; Carry : Out bit) ; end Half_adder;

Architecture A1 of Half_Adder isBeginProcess(x,y) begin if x=0 and y=0 then sum

3. A2Architecture A2 of Half_Adder is component XOR2 port ( I1, I2: in BIT; Out1: out BIT); end component; component AND2 port ( I1, I2: BIT; Out1: out BIT); end component;begin A: XOR2 port map (X, Y, Sum); B: AND2 port map (X, Y, Carry);end A2;

4. A3Architecture A3 of Half_Adder is begin Sum

1. VHDL Entity Architecture Configuration LibraryPackage 3.2.2 VHDL

2. VHDL

3. 3.2VHDL D3 D2 D1 D0 Y S1 S0

VHDL LIBRARY IEEE IEEE USE IEEE.STD_LOGIC_1164.ALL -- USE IEEE.STD_LOGIC_ARITH.ALL USE IEEE.STD_LOGIC_UNSIGNED.ALL ENTITY mux41 IS -- PORT ( S1, S0: IN STD_LOGIC -- D3, D2, D1, D0: IN STD_LOGIC Y: OUT STD_LOGIC -- ) END mux41 ARCHITECTURE behaveior OF mux41 IS -- BEGIN -- Y

4. VHDL VHDL VHDL ENTITYEND ARCHITECTUREEND

3.2.3 entity is [] [] end 1.

2. VHDL

Port ({} {} )generic (=

IN OUTINOUTBUFFER

(generic)

entity mux is port(in1,in2,sel: in bit ; output : out bit ); generic (delay : time:=5 ns); end mux ;

3.2.4 VHDL VHDL

3.2.4 VHDL

3.2.4 VHDL

1. ARCHITECTURE OF IS [] BEGIN [] END [ARCHITECTURE] [] 3.2.4 VHDL

2. SIGNAL TYPE CONSTANT COMPONENT FUNCTION PROCEDURE 3.2.4 VHDL

3. 3.2.4 VHDL

3. BLOCK PROCESS SIGNAL 3.2.4 VHDL

3. PROCEDUREFUNCTION COMPONENT 3.2.4 VHDL

architecture behaviour of mux is begin if sel=1then output

3.3 VHDL3.3.1 VHDL3.3.2 VHDL3.3.3

type is

type byte is range 127 to 127;type num is integer range 0 to 9;type resistance is range 1 to 10e8 units ohm; kohm=1000 ohm; end units3.3.1 VHDL

210E6 , 16#D2# 357.6, 8#43.2#e+5 a sd89 B110111 , O712 , X8BD 1 kohm , 5 ns

type is (......;

type boolean is (false,true); type two_level_logic is (0,1);

type is record ........ end record;type pctbus is record adder : std_logic_vector(31 downto 0); data : std_logic_vector (0 to 31); end record;

type is array of type word is array (15 downto 1) of bit

type is array rangeof type bit_vector is array (natural range) of bit; type string is array (positive range) of character;

subtype is subtype lower_letter is character range a to z; subtype register is bit_vector (0 to 7); subtype ascii is character;

STANDARDVHDL() 2. VHDL

1BOOLEAN FALSETRUE IF A>BA>BTRUEFALSE TYPE BOOLEAN IS FALSETRUE 2. VHDL

2BIT 01 TYPE BIT IS 01 2. VHDL

3BIT_VECTOR TYPE BIT VECTOR IS ARRAY (NATURAL RANGE < >) OF BIT 1011X00EA SIGNAL b: BIT VECTOR0 TO 7 bb(0)~b(7)b(0)b(7) 2. VHDL

4CHARACTER TYPE CHARACTER ISASCII ASCIIXy63 ASCII 2. VHDL

5STRING TYPE STRING IS ARRAY(POSITIVE RANGE < >) OF CHARACTER A BOY.10101011 2. VHDL

6INTEGER TYPE INTEGER IS RANGE -2147483647 TO +2147483647 32-(231-1)~+(231-1) -2147483647 ~ +2147483647 1510E316#D5#2#11011010#8#653# 2. VHDL

7POSITIVE SUBTYPE POSITIVE IS INTEGER RANGE 1 TO INTEGERHIGH 0 321~(231-1) 1~2147483647 INTEGERHIGH, 231-1 2. VHDL

8NATURAL SUBTYPE NATURAL IS INTEGER RANGE 0 TO INTEGERHIGH 0 2. VHDL

9REAL TYPE REAL IS RANGE -1.0E38 TO +1.0E38 -1.0E+38 ~ +1.0E+38 -2.5-1.0E8 2. VHDL

10TIME TYPE TIME IS RANGE 2147483647 TO 2147483647 55 ms20 ns 2. VHDL

10TIME units fs --10-15S ps=1000fs --ns=1000ps --us=1000ns --ms=1000us --sec=1000ms--min=60sec --hr=60min -- END units 2. VHDL

11SEVERITY_LEVEL TYPE severity_level ISnotewarningerrorfailure NOTEWARNING ERRORFAILURE 4 2. VHDL

3. IEEE IEEESTD_LOGIC_1164 STD_LOGIC STD_LOGIC_VECTOR IEEESTD_LOGIC_1164 LIBRARY IEEE USE IEEE.STD_LOGIC_1164.ALL

1STD_LOGIC IEEE11649BIT STD_LOGIC9 U--X-- 0--0 1--1 Z-- W-- L--0 H--1 --- TYPE STD LOGIC ISUX01Z WLH- 3. IEEE

2STD_LOGIC_VECTOR STD_LOGIC STD_LOGIC TYPE STD LOGIC VECTOR IS ARRAYNATURAL RANGE< >OF STD LOGIC 3. IEEE

4. IEEESTD_LOGIC_ARITHIEEE UNSIGNED SIGNED IEEESTD_LOGIC_ARITH LIBRARY IEEE USE IEEE.STD_LOGIC_ARITH.ALL TYPE UNSIGNED IS ARRAYNATURAL RANGE< >OF STD LOGIC TYPE SIGNED IS ARRAYNATURAL RANGE< >OF STD LOGIC

STD_LOGIC SIGNEDINTEGER SIGNAL DATA: UNSIGNED( 3 DOWNTO 0) DATA

VARIABLE DATA1,DATA2: SIGNED (3 DOWNTO 0) DATA1

3.3.2 VHDL VHDL VHDL

1. ()

1. BITBOOLEANSTD_LOGICBIT_VECTORSTD_LOGIC_VECTOR

ANDORXOR NOT Y1

2.

3. BOOLEANTRUEFALSE

4. +- (+) (-)

+ -

5. VHDL93VHDL87

5. BIT_VECTORSTD_LOGIC_VECTORBITBOOLEAN X

: SLLSLLA2A1A00 SRL SRL0A3A2A1 5.

: SLASLAA2A1A0A0 SRASRAA3A3A2A1 5.

: ROLROLA2A1A0A3 ROR RORA0A3A2A1 5.

6.

3.3.3 VHDL VHDL

VHDL

3.3.3 VHDL

EVENTTRUEFALSE 1. CLK CLKEVENTCLK CLKEVENT AND CLK=1CLK CLKEVENT AND CLK=0CLK

IEEESTD_LOGIC_1164 1. RISING_EDGE(CLK) CLKEVENT AND CLK=1 FALLING_EDGE(CLK) CLKEVENT AND CLK=0

() LEFT()RIGHT()HIGH()LOW() 2. num190-- H1 = 9-- H2 = 0-- H3 = 9-- H4 = 0 TYPE num1 IS INTEGER RANGE 9 DOWNTO 0 VARIABLE H1, H2, H3, H4: INTEGER H1: = num1LEFT H2: = num1RIGTH H3: = num1HIGH H4: = num1LOW

3. -- WTH = 16 TYPE num2 IS ARRAY0 TO 15 OF BIT VARIABLE WTH: INTEGER WTH: = num2LENGTH

4. RANGEREVERSE_RANGE data_bus SIGNAL data_bus: STD_LOGIC_VECTOR15 DOWNTO 0 data_busdata_busRANGE=15 DOWNTO 0

4. VARIABLE byte: BIT_VECTOR7 DOWNTO 0 bity byteLEFT=7byteRIGHT=0 byteHIGH=7byteLOW=0 byteLENGTH=8 byteRANGE=7 DOWNTO 0 byteREVERSE_RANGE=0 TO 7

3.3.3 VHDL constant =

constant vcc:real:=5.0; constant delay:time:=100 ns; constant fbus:bit_vector:=0101;

variable =variable x,y :integer ; variable count:integer range 0 to 255:=10 ; tmp3:=tmp1 after 5 ns

signal =: signal sys_clk:bit=0; signal ground:bit:=0;

=, ( ) =

4.5.2 LIBRARY IEEE USE IEEE.STD_LOGIC_1164.ALL USE IEEE.STD_LOGIC_UNSIGNED.ALL ENTITY adder8 IS PORT ( ci: IN STD_LOGIC a, b: IN STD_LOGIC_VECTOR( 7 DOWNTO 0 ) s: OUT STD_LOGIC_VECTOR( 7 DOWNTO 0 ) co: OUT STD_LOGIC ) END adder8 abcisco

ARCHITECTURE behavior OF adder8 IS SIGNAL ss: STD_LOGIC_VECTOR ( 8 DOWNTO 0 ) SIGNAL aa, bb: STD_LOGIC_VECTOR ( 8 DOWNTO 0 ) BEGIN aa

3.4 VHDL() ()

[]process [] begin [] end process;

. = < =

variable a ,b :std_logic ;signal c :std_logic_vector(1 to 4);a := 1;b := 0;c

signal a,b :std_logic_vector(0 to 3);signal i : integer range 0 to 3;Signal y : std_logic ;a

variable a,b;std_logic_vector(1 to 4);a(1to 2) :=10;a( 1 to 4):=0101;

signal a,b,c,d: std_logic;signal s : std_logic_vector(1 to 4);s c,2=>b,1=>d)

. ifcaseloopnextexit

1. if

if then elsif then . elsif then else end if ;

.

IF d1d0sy ARCHITECTURE example1 OF mux2 IS BEGIN PROCESSd1, d0, s BEGIN IF ( s =0) THEN y

.

CASE (2) CASE CASE IS WHEN => WHEN => WHEN OTHERS => END CASE =>THEN

CASE 5 1 TO 3) 4 | 646

CASE CASEWHEN WHEN CASEOTHERS ,OTHERS; =>THEN CASE

CASE ARCHITECTURE example3 OF mux4 IS SIGNAL s: STD_LOGIC_VECTOR1 DOWNTO 0 BEGIN syyyyy

LOOP3 VHDL 3LOOP LOOP FOR_LOOP WHILE_LOOP LOOP

FOR_LOOP 3 VHDL FOR_LOOP [:] FOR IN TO LOOP END LOOP [] [:] FOR IN DOWNTO LOOP END LOOP []

13 VHDL FOR_LOOP = |-|+1

FOR_LOOP 3 VHDL X8X1Y=1Y=0 FOR_LOOPX n 07

3 VHDL LIBRARY IEEE USE IEEE.STD_LOGIC_1164.ALL ENTITY loop1 IS PORTX: IN STD_LOGIC_VECTOR7 DOWNTO 0 Y: OUT STD_LOGIC END loop1 ARCHITECTURE example4 OF loop1 IS BEGIN PROCESS ( X ) VARIABLE temp: STD_LOGIC BEGIN temp :=0 FOR n IN 7 DOWNTO 0 LOOP temp := temp XOR X( n ) END LOOP Y

WHILE_LOOP 3 VHDL WHILE_LOOP [:] WHILE LOOP END LOOP [] ,

WHILE_LOOP 3 VHDL ARCHITECTURE example5 OF loop2 IS BEGIN PROCESS ( X ) VARIABLE temp: STD_LOGIC VARIABLE n: INTEGER BEGIN temp :=0 n := 0 WHILE n < 8 LOOP temp := temp XOR X( n ) n := n+1 END LOOP Y

LOOPNEXTEXIT 3 VHDL LOOP [ : ] LOOP END LOOP [] LOOP L2: LOOP A := A+1 EXIT L2 WHEN A>10 END LOOP L2-- A 10

NEXTLOOP 3 VHDL 4NEXT NEXT [ ] [ WHEN ]

NEXT 3 VHDL 4NEXT 1 NEXT 2 NEXT 3 NEXT WHEN

NEXT_WHEN 3 VHDL ARCHITECTURE example6 OF NEXT_WHEN1 IS BEGIN PROCESS ( s ) VARIABLE i: INTEGER BEGIN L1: FOR i IN 7 DOWNTO 0 LOOP y( i )

3 VHDL LIBRARY IEEE USE IEEE.STD_LOGIC_1164.ALL ENTITY NEXT_WHEN2 IS PORT ( d: IN STD_LOGIC_VECTOR ( 0 TO 31) y: OUT STD_LOGIC_VECTOR ( 0 TO 3 ) ) END NEXT_WHEN2 ARCHITECTURE example7 OF NEXT_WHEN2 IS BEGIN PROCESS ( d ) VARIABLE i,k,j: INTEGER VARIABLE tmp: STD_LOGIC d[0..31]y[0..3]1y[i]=1y[i]=0

3 VHDL BEGIN k: = 0L1: FOR i IN 0 TO 3 LOOP y( i )

EXITNEXTLOOP3 VHDL 5EXIT EXIT [ ] [ WHEN ]

EXIT 3 VHDL 5EXIT 1 EXIT ,END LOOP 2 EXIT 3 EXIT WHEN

EXIT 3 VHDL PROCESS ( X, Y ) BEGIN Z

EXIT_WHEN 3 VHDL PROCESS ( X, Y ) BEGIN Z

WAIT 3 VHDL 3. WAIT [ON ] [UNTIL ] [FOR ] WAIT

WAIT 3 VHDL 1 WAIT 2 WAIT ON SIGNAL ab STD LOGIC PROCESS WAIT ON ab END PROCESS-- ab 3.

3 VHDL 3 WAIT UNTIL WAIT UNTIL clk =1AND clkEVENT z

3 VHDL 4 WAIT FOR WAIT WAIT FOR 25ns z

NULLNOP 3 VHDL 4. NULL CASE sel IS WHEN 00 => y y y NULL END CASE --

3.4.2 VHDL VHDL VHDL

3.4.2 VHDL VHDL VHDL

PROCESS VHDL 1.

VHDL 1 [:] PROCESS [()] [IS][] BEGIN END PROCESS []

VHDL 2

VHDL 2

VHDL 2 PROCESSWAIT IFCASELOOPNULL NEXTEXIT

VHDL clkclr=0Q=0clr=1 PROCESS ( clk, clr ) BEGIN IF clr =0 THEN Q

VHDL clr PROCESS ( clk) BEGIN IF ( clk =1AND clkEVENT ) THEN IF clr =0 THEN Q

, VHDL 2.

VHDL VHDL 1

IF VHDL 2

VHDL ARCHITECTURE example5 OF mux41 IS SIGNAL s: STD_LOGIC_VECTOR( 1 DOWNTO 0 ) BEGIN s

CASE VHDL 3 WITH SELECT

VHDL ARCHITECTURE example6 OF mux41 IS SIGNAL s: STD_LOGIC_VECTOR( 1 DOWNTO 0 ) BEGIN s

BLOCK VHDL 3.

VHDL 1 BLOCK BEGIN END BLOCK

VHDL 2

ABSUMSUBCOBO VHDL LIBRARY IEEE USE IEEE.STD LOGIC 1164.ALL USE IEEE.STD_LOGIC_UNSIGNED.ALL ENTITY add_sub IS PORTA, B: IN STD LOGIC_VECTOR7 DOWNTO 0 SUM, SUB: OUT STD LOGIC_VECTOR7 DOWNTO 0 CO, BO: OUT STD LOGIC END add_sub

VHDL ARCHITECTURE example12 OF add_sub IS SIGNAL AA,BB,SM,SB: STD_LOGIC_VECTOR(1 DOWNTO 0) BEGIN AA

VHDL SUBTRACTER BLOCK BEGIN SB

VHDL 4. COMPONENT IS GENERIC PORT END COMPONENT PORT MAP

GENERICPORT VHDL 4. PORT MAP

VHDL YD0 D1D2 D3S1S0AB

VHDL LIBRARY IEEE USE IEEE.STD_LOGIC_1164.ALL ENTITY mux4 IS PORT ( D0, D1, D2, D3: IN STD_LOGIC S0, S1: IN STD_LOGIC Y: OUT STD_LOGIC ) END mux4 ARCHITECTURE example13 OF mux4 IS COMPONENT mux2 PORT ( a, b, s: IN STD_LOGIC y: OUT STD_LOGIC ) END COMPONENT SIGNAL A, B: STD_LOGIC BEGIN U1: mux2 PORT MAP ( D0, D1, S0, A ) U2: mux2 PORT MAP ( a => D2, b => D3, s => S0, y => B ) U3: mux2 PORT MAP ( A, B, S1, y => Y ) END exmple13-- ---- -- --

VHDL LIBRARY IEEE USE IEEE.STD_LOGIC_1164.ALL ENTITY mux2 IS PORT ( a, b, s: IN STD_LOGIC y: OUT STD_LOGIC) END mux2 ARCHITECTURE example13 OF mux2 IS BEGIN y

VHDL 4. PORT MAP ( )COMPONENTPORT U1: mux2 PORT MAP (D0, D1, S0, A ) D0D1S0Aabsy =>PORT MAP ( ) U2: mux2 PORT MAP (a=>D2,b=>D3,s=>S0,y=>B) PORT MAP( ) U3: mux2 PORT MAP (A,B,S1,y=>Y)

: xycincoutsumxycincoutsumEntity full _adder is port (x ,y, cin :in bit; sum ,cout : out bit);End full _adder;u1u2c1s1c2

GENERATE VHDL 5.

VHDL 5. 1 [:] FOR IN GENERATE BEGIN END GENERATE []

VHDL 5. 2 [:] IF GENERATE BEGIN END GENERATE []

FORIF VHDL 5.

D VHDL 1D LIBRARY IEEE USE IEEE.STD_LOGIC_1164.ALL ENTITY ff_d IS PORT ( d, cp: IN STD_LOGIC q: OUT STD_LOGIC ) END ff_d ARCHITECTURE example14 OF ff_d IS BEGIN PROCESScp BEGIN IF cp =1'AND cpEVENT THEN q

VHDL 1D LIBRARY IEEE USE IEEE.STD_LOGIC_1164.ALL ENTITY shift_reg_8 IS PORT ( Din, CLK: IN STD_LOGIC Dout: OUT STD_LOGIC ) Q: BUFFER STD_LOGIC_VECTOR ( 7 DOWNTO 0 )) END shift_reg_8 ARCHITECTURE example14 OF shift_reg_8 IS COMPONENT ff_d PORT ( d, cp: IN STD_LOGIC q: IN STD_LOGIC ) END COMPONENT SIGNAL d: STD_LOGIC_VECTOR ( 0 TO 8 ) --

VHDL 1D BEGIN d(0)

ASSERTVHDL VHDL 6. ASSERT [REPORT ] [SEVERITY ]

NOTEWARNINGERRORFAILURE VHDL 6. RSRS1 ASSERT S =1 AND R =1 REPORT S =1and R = 1 SEVERITY ERROR

3.4.3 VHDL VHDL VHDL PROCEDURE FUNCTION

VHDL 1. 1

VHDL 1 ,INOUTINOUT PROCEDURE PROCEDURE IS [] BEGIN END PROCEDURE

VHDL 2 => =>

VHDL 2

VHDL LIBRARY IEEE USE IEEE.STD_LOGIC_1164.ALL USE IEEE.STD_LOGIC_ARITH.ALL USE IEEE.STD_LOGIC_UNSIGNED.ALL ENTITY add IS PORT ( A, B, C: IN STD_LOGIC_VECTOR( 3 DOWNTO 0 ) CLK, SET: IN STD_LOGIC S: OUT STD_LOGIC_VECTOR ( 3 DOWNTO 0 )) END add ARCHITECTURE example15 OF add IS PROCEDURE add_1 ( VARIABLE data1,data2,data3: IN STD_LOGIC_VECTOR VARIABLE dataout: OUT STD_LOGIC_VECTOR IS BEGIN dataout:= data1 + data2 + data3 END add_1 --

VHDL BEGIN PROCESSCLK VARIABLE tmp: STD_LOGIC_VECTOR( 3 DOWNTO 0 ) BEGIN IF CLK =1AND CLKEVENT THEN IF SET =1 THEN tmp:=0000 ELSE add_1A, B, C, tmp END IF END IF S

VHDL 2. 1 FUNCTION RETURN

VHDL 2 FUNCTION RETURN IS [] BEGIN RETURN [] END FUNCTION []

VHDL 3 => =>

VHDL FUNCTION LIBRARY IEEE USE IEEE.STD_LOGIC_1164.ALL ENTITY min IS PORT ( A, B: IN STD_LOGIC_VECTOR ( 7 DOWNTO 0 ) Y: OUT STD_LOGIC_VECTOR ( 7 DOWNTO 0 )) END min

VHDL FUNCTION ARCHITECTURE example16 OF min IS FUNCTION min ( a, b: IN STD_LOGIC_VECTOR) RETURN STD_LOGIC_VECTOR FUNCTION min ( a, b: IN STD_LOGIC_VECTOR RETURN STD_LOGIC_VECTOR IS BEGIN IF ( a < b) THEN RETURN a ELSE RETURN b END IF END min BEGIN Y

VHDL 3. 1 RETURN 2 RETURN

3.5

IEEESTD, ASIC,WORK, IEEE STD_LOGIC_1164 STD_LOGIC_arith STD_LOGIC_unsigned STD_LOGIC_signed

STD standard : textio : /

ASIC ASIC

Work

library use .. use .. all library ieee ; use ieee.std_logic_1164.all

VHDL

PACKAGE IS END PACKAGE BODY IS END

PACKAGE logic ISTYPE three_level_logic IS (0,1,z);CONSTANT unkown_value : three_level_logic :=0;FUNCTION invert ( input : three_level_logic ) RETURN three_level_logic ;END logic;PACKAGE BODY logic ISFUNCTION invert (input : three_level_logic )RETURN three_level_logic ISBEGIN CASE input IS WHEN 0=> RETURN1; WHEN 1=> RETURN 0 ; WHENz=> RETURN zEND CASE ;END invert ;END logic ;

LIBRARY IEEE; USE IEEE STD-LOGIC-1164.ALL; PACKAGE UPAC IS CONSTANT K:=INTEGER:=4; SUBTYPE CPU-BUS IS STD-LOGIC-VECTOR(K-1 DOWNTO 0); END UPAC;

USE logic. Three _ level_ logic USE logic. invert USE logic.all ;logic+

:

::,:

: xycincoutsumxycincoutsumEntity full _adder is port (x ,y, cin :in bit; sum ,cout : out bit);End full _adder;u1u2c1s1c2

Architecture describ1 of full_adder is component half_adder generic (tpd:time:=2 ns); port(a,b: in bit; s,c: out bit); end component; component or_gate port(o1,o2: in bit; o3: out bit); end component; signal c1,s1,c2:bit; for u1: half_adder use entity half_adder(a1); for u2: half_adder use entity half_adder(a2); begin u1: half_adder generic map (4 ns) port map (x,y,s1,c1); u2: half_adder generic map (4 ns) port map (s1,cin,sum,c2); u3: or_gate port map (c1,c2,cout) ;End describ1;u1,u2,u3

Configuration config1 of full_adder is for describ2 for u1: half_adder use entity half_adder(a1); end for; for u2: half_adder use entity half_adder(a2); end for; end forend config1: configuration of is for []; end for; end ;

Architecture describ3 of full_adder issignal c1,s1,c2:bit;begin u1: entity half_adder(a1) generic map (4 ns) port map (x,y,s1,c1); u2: entity half_adder(a2) generic map (4 ns) port map (s1,cin,sum,c2); u3: entity or_gate port map (c1,c2,cout) ;End describ3;

::entity [.][()] [generic map()] port map();

VHDL

VHDL

Block

block [] begin [] end block

blockENTITY latch ISPORT(d,clk : IN BIT; q,qb : OUT BIT ) ;END latch ;ARCHITECTURE latch_guard OF latch ISBEGIN g1: BLOCK(clk=1) BEGIN q

[]process12. [] begin [] end process;

ENTITY mux IS PORT(d0,d1,sel:IN BIT ; q:OUT BIT);ENDARCHITECTURE connect OF mux ISBEGIN cale:PROCESS(d0,d1,sel) VARIABLE tmp1,tmp2,tmp3 : BIT; BEGIN tmp1:= d0 and sel; tmp2:= d1 and (not sel); tmp3:= tmp1 or tmp2; q

procedure 12.....is [] begin [] end

LIBRARY IEEE ;USE IEEE.STD_LOGIC_1164.ALL;ENTITY procedure1 ISPORT(din1, din2 : IN INTEGER RANGE 0 TO 31; dout : OUT INTEGER RANGE 0 TO 31);END;ARCHITECTURE a OF procedure1 IS PROCEDURE jfq (d1,d2 : IN INTEGER RANGE 0 TO 31; VARIABLE fout : OUT INTEGER RANGE 0 TO 31 ) IS BEGIN fout : = d1 + d2 ; END;BEGIN PROCESS VARIABLE fo : INTEGER RANGE 0 TO 31 ; BEGIN jfq(din1,din2,fo); dout

function 12 return is [] begin [] Return []; End []

LIBRARY IEEE ;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_SIGNED.ALL;ENTITY function1 IS PORT(din1, din2 : IN STD_LOGIC_ VECTOR (0 TO 3); dout : OUT STD_LOGIC_ VECTOR (0 TO 3));END;ARCHITECTURE a OF function1 IS FUNCTION ls_xj (d1,d2 : STD_LOGIC_ VECTOR (0 TO 3)) RETURN STD_LOGIC_ VECTOR IS VARIABLE temp : STD_LOGIC_ VECTOR (0 TO 3) ; BEGIN temp : = d1 + d2 ; RETURN temp; END;BEGIN dout

inin,out,inoutininout,inout

3.6 TYPETYPETYPE IS OF ;TYPE IS ;

TYPE st1 IS ARRAY ( 0 TO 15 ) OF STD_LOGIC ;TYPE week IS (sunmontuewedthufrisat) ;

TYPE m_state IS ( st0st1st2st3st4st5 ) ; SIGNAL present_statenext_state : m_state ;

TYPE BOOLEAN IS FALSETRUE TYPE my_logic IS ( '1' 'Z' 'U' '0' ) ; SIGNAL s1 : my_logic ; s1

SUBTYPE

SUBTYPE IS RANGE ;

SUBTYPE digits IS INTEGER RANGE 0 to 9 ;

VHDL

1. 2. ARCHITECTURE ...IS TYPE FSM_ST IS (s0s1s2s3); SIGNAL current_state, next_state; FSM_ST; ...

3. next_statenext_state

LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY s_machine IS PORT ( clk,reset : IN STD_LOGIC; state_inputs : IN STD_LOGIC_VECTOR (0 TO 1); comb_outputs : OUT INTEGER RANGE 0 TO 15 );END s_machine;ARCHITECTURE behv OF s_machine IS TYPE FSM_ST IS (s0, s1, s2, s3); SIGNAL current_state, next_state: FSM_ST;BEGIN REG: PROCESS (reset,clk) BEGIN IF reset = '1' THEN current_state

BEGIN CASE current_state IS WHEN s0 => comb_outputs

MooreMoore MealyMealy

ClockNo Clock

3.6.2 Moore ADC0809ADC0809+FPGA

ADC0809

ADC0809

LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY ADCINT IS PORT(D : IN STD_LOGIC_VECTOR(7 DOWNTO 0); --08098CLK : IN STD_LOGIC; --EOC : IN STD_LOGIC; --ALE : OUT STD_LOGIC; --8START : OUT STD_LOGIC; --OE : OUT STD_LOGIC; --3ADDA : OUT STD_LOGIC; --LOCK0 : OUT STD_LOGIC; --Q : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)); --8END ADCINT;ARCHITECTURE behav OF ADCINT ISTYPE states IS (st0, st1, st2, st3,st4) ; -- SIGNAL current_state, next_state: states :=st0 ; SIGNAL REGL : STD_LOGIC_VECTOR(7 DOWNTO 0); SIGNAL LOCK : STD_LOGIC; --

BEGINADDA

END PROCESS COM ; REG: PROCESS (CLK) BEGIN IF (CLK'EVENT AND CLK='1') THEN current_state

ADC0809

COMCOM1COM2 COM1: PROCESS(current_state,EOC) BEGIN CASE current_state IS WHEN st0=> next_state next_state IF (EOC='1') THEN next_state

WHEN st3=>ALE

MooreLIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY MOORE1 IS PORT (DATAIN :IN STD_LOGIC_VECTOR(1 DOWNTO 0); CLK,RST : IN STD_LOGIC; Q : OUT STD_LOGIC_VECTOR(3 DOWNTO 0));END MOORE1;ARCHITECTURE behav OF MOORE1 IS TYPE ST_TYPE IS (ST0, ST1, ST2, ST3,ST4); SIGNAL C_ST : ST_TYPE ; BEGIN PROCESS(CLK,RST) BEGIN IF RST ='1' THEN C_ST

CASE C_ST IS WHEN ST0 => IF DATAIN ="10" THEN C_ST

RTLSynplify

1.0s

2.0s

3.0s

4.0s

5.0s

6.0s

7.0s

8.0s

3.6.3 Mealy LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL;ENTITY MEALY1 ISPORT ( CLK ,DATAIN,RESET : IN STD_LOGIC; Q : OUT STD_LOGIC_VECTOR(4 DOWNTO 0));END MEALY1;ARCHITECTURE behav OF MEALY1 IS TYPE states IS (st0, st1, st2, st3,st4); SIGNAL STX : states ; BEGIN COMREG : PROCESS(CLK,RESET) BEGIN -- IF RESET ='1' THEN STX

CASE STX IS WHEN st0 => IF DATAIN = '1' THEN STX IF DATAIN = '0' THEN STX IF DATAIN = '1' THEN STX IF DATAIN = '0' THEN STX IF DATAIN = '1' THEN STX STX IF DATAIN = '1' THEN Q

WHEN st4=> IF DATAIN = '1' THEN Q

MEALY2 LIBRARY IEEE; --MEALY FSMUSE IEEE.STD_LOGIC_1164.ALL;ENTITY MEALY2 IS PORT ( CLK ,DATAIN,RESET : IN STD_LOGIC; Q : OUT STD_LOGIC_VECTOR(4 DOWNTO 0));END MEALY2;ARCHITECTURE behav OF MEALY2 IS TYPE states IS (st0, st1, st2, st3,st4); SIGNAL STX : states ; SIGNAL Q1 : STD_LOGIC_VECTOR(4 DOWNTO 0); BEGIN COMREG : PROCESS(CLK,RESET) -- BEGIN IF RESET ='1' THEN STX

END IF; END PROCESS COMREG ;COM1: PROCESS(STX,DATAIN,CLK) -- VARIABLE Q2 : STD_LOGIC_VECTOR(4 DOWNTO 0);BEGIN CASE STX IS WHEN st0 => IF DATAIN = '1' THEN Q2 := "10000" ; ELSE Q2 := "01010" ; END IF ; WHEN st1 => IF DATAIN = '0' THEN Q2 := "10111" ; ELSE Q2:="10100" ; END IF ; WHEN st2 => IF DATAIN = '1' THEN Q2 := "10101" ; ELSE Q2:="10011" ; END IF ; WHEN st3=> IF DATAIN = '0' THEN Q2 := "11011" ; ELSE Q2:="01001" ; END IF ; WHEN st4=> IF DATAIN = '1' THEN Q2 := "11101" ; ELSE Q2:="01101" ; END IF ; WHEN OTHERS => Q2:="00000" ; END CASE ;

IF CLK'EVENT AND CLK = '1' THEN Q1

3.6.4 START = current_state4 ALE = current_state3 OE = current_state2 LOCK = current_state1

LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY AD574A IS PORT ( D : IN STD_LOGIC_VECTOR(11 DOWNTO 0); CLK ,STATUS : IN STD_LOGIC; OUT4 : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); Q : OUT STD_LOGIC_VECTOR(11 DOWNTO 0) );END AD574A;ARCHITECTURE behav OF AD574A ISSIGNAL current_state, next_state: STD_LOGIC_VECTOR(4 DOWNTO 0 ); CONSTANT st0 : STD_LOGIC_VECTOR(4 DOWNTO 0) := "11100" ; CONSTANT st1 : STD_LOGIC_VECTOR(4 DOWNTO 0) := "00001" ; CONSTANT st2 : STD_LOGIC_VECTOR(4 DOWNTO 0) := "00000" ; CONSTANT st3 : STD_LOGIC_VECTOR(4 DOWNTO 0) := "00100" ; CONSTANT st4 : STD_LOGIC_VECTOR(4 DOWNTO 0) := "00110" ; SIGNAL REGL : STD_LOGIC_VECTOR(11 DOWNTO 0); SIGNAL LK : STD_LOGIC; BEGIN COM1: PROCESS(current_state,STATUS) --

BEGIN CASE current_state IS WHEN st0 => next_state next_state IF (STATUS='1') THEN next_state

END IF; END PROCESS ; Q

...SIGNAL CRURRENT_STATE,NEXT_STATE: STD_LOGIC_VECTOR(2 DOWNTO 0 );CONSTANT ST0 : STD_LOGIC_VECTOR(2 DOWNTO 0) := "000" ;CONSTANT ST1 : STD_LOGIC_VECTOR(2 DOWNTO 0) := "001" ;CONSTANT ST2 : STD_LOGIC_VECTOR(2 DOWNTO 0) := "010" ;CONSTANT ST3 : STD_LOGIC_VECTOR(2 DOWNTO 0) := "011" ;CONSTANT ST4 : STD_LOGIC_VECTOR(2 DOWNTO 0) := "100" ;

STATE0

000

100000

STATE1

001

010000

STATE2

010

001000

STATE3

011

000100

STATE4

100

000010

STATE5

101

000001

One-hot encoding

3.6.5

st0

000

st1

001

st2

010

st3

011

st4

100

st_ilg1

101

st_ilg2

110

st_ilg3

111

...TYPE states IS (st0, st1,st2,st3st4st_ilg1st_ilg2st_ilg3); SIGNAL current_state, next_state: states;...COMPROCESS(current_state, state_Inputs) -- BEGIN CASE current_state IS -- ... WHEN OTHERS => next_state

One hot Gray Binary

4 : state0, state1, state2, state3 :(2 bits : 00 01 10 11 (Binary)(4 bits : 1000 0100 0010 0001 (One Hot)(2 bits : 00 01 11 10 (Grey Code

FPGACycloneSpantan-3ECPLDMAX3000AXC9500XLCPLD

Sample State Machinelibrary ieee;use ieee.std_logic_1164.all;package your_own_type istype t_state is (idle,state0,state01,state011, state0110,state01101, state011011, dummy0, dummy1, dummy2, dummy3, dummy4, dummy5, dummy6, dummy7, dummy8, dummy9, dummy10);end your_own_type;library ieee;use ieee.std_logic_1164.all;use work.your_own_type.all;Entity stmh isport (clk, serial_in, reset : in std_logic; match : out std_logic);end stmh;architecture body_stmh of stmh is

signal present_state : t_state;beginprocess(clk,serial_in, present_state)beginif (reset = '1') thenpresent_state

when state011 => if (serial_in = '0') then present_state

when dummy6 => present_state present_state present_state present_state present_state present_state

Quartus IISynplify

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