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ANDES Confidential

OutlineOutline

SoCANDES

SoC

Embedded Introduction Embedded System Hardware platform Instruction Set Architecture Memory and Cache Embedded System General Peripherals AMBAAndeSightTM & AndESLiveTM

DPF example Real Time OSIC Technology Virtual Game PortingDemo

Power pointAndes training material

Lab(70%)Final(25%)(5%)

IC

(MPEG, H.264)

Company Introduction

Overview of Andes TechnologyOverview of Andes Technology

Andes Highlights

Andes Mission

Provide the best processor-based SoC solution

Market Opportunities

The demand of multi-standard and multi-functions for different applicationsdue to the device convergence of consumer electronics

The BRICs demand a big volume for low cost products Fast growing market in Asia, world-wide IC designs move to Asia

Founded in 2005 March First tier investors and partners (Government VC, MediaTek, and Faraday) USD$20M capital for financial stability

MilestonesMilestones

03/2005 : Company established

03/2006 : Andes ISA debut12/2006 : AndeSight/AndESLive beta release

07/2007 : AndeSight/AndESLive v1.2 release07/2007 : First AndesCore N1213-S release10/2007 : UMC 130nm N1213 hardcore at ~600MHz

04/2008 : AndeSight 1.3 release07/2008 : AndesCore N1003-S release07/2008 : AndeSight 1.3.1 release09/2008 : AndesCore N903-S release09/2008 : TSMC 90nm N1213 hardcore at ~660MHz

Products Introduction

Andes Main Lines of BusinessAndes Main Lines of Business

AndesCoreCPU Core Family

AndeStarAndes 16/32-bit Mixable ISA

AndeShapeSoC + EVB + ICE

AndeSoftOptimized Target SW such as Linux/RTOS, Middleware, and Application Software.

AndESLiveESL Integrated Virtual

Environment

AndeSightIntegrated Development

Environment

AndesEmbedded

AndesCore

AndesCoreTM Market SegmentsAndesCoreTM Market Segments

Portable audio/media playerDVB/DMB basebandDVDDSCToys, Games

MID/NetbookMFPNetworkingGateway/RouterHome entertainmentSmartphone/Mobile phone

N12 series

N10 Series

N9 Series

MCUStorageAutomotive controlToys

High-end

Mid-range

Low-end

N903: Low-power Cost-efficient Embedded ControllerN903: Low-power Cost-efficient Embedded Controller

Features:Harvard architecture, 5-stage pipeline.16 general-purpose registers.Static branch predictionFast MACHardware dividerFully clock gated pipeline2-level nested interruptExternal instruction/data local memory interfaceInstruction/data cacheAPB/AHB/AHB-Lite/AMI bus interfacePower management instructions45K ~ 110K gate count250MHz @ 130nm

Applications:MCUStorageAutomotive controlToys

External Bus Interface

APB/AHB/AHB-Lite/AMI

InstrCache

InstrLM/IF

DataCache

DataLM/IF

N9 uCore

JTAG/EDM

N903 CompetitionN903 CompetitionCores Features N903N903 ARM7TDMI Cortex-M3

Architecture Harvard Von Neumann Harvard

Pipeline Stages 5 3 3

Instruction Set 16-/32-bit mixable Thumb/ARM 16-/32-bit mixable

General-purpose register # 16 16 16

Branch prediction Static None StaticInterrupt latency (Cycle) 10 24-42 12

Data endian support Big and Little Big and Little Big and Little

Bus APB/AHB/AMI 1 AHB 3 AHB Lite

Sleep Mode Yes No Yes

Vectored interrupt support Yes (internal/external) None Yes (external)

DMIPS/Mhz 1.38 0.95 1.25

Core Area (mm2) (TSMC 0.13G) *0.42 0.26 0.43/0.21

Core Power (mW/MHz) (TSMC 0.13G) *0.06 0.06 0.165/0.084

Max Frequency (Mhz) (TSMC 0.13G) *204 133 135/50

DMIPS (TSMC 0.13G) 281.52 126.35 168.75/62.5

Cost Performance (DMIPS/mm2) 670.3 486 393/298*TSMC free library with max speed synthesis constraint

N1033A: Lowe-power Cost-efficient Application ProcessorN1033A: Lowe-power Cost-efficient Application Processor


AHB/AHB(D)/AHB-Lite/APB

InstructionCache

InstructionLM/INF

DataCache

DataLM/INF

MMU/MPU

N10 Core +Audio

JTAG/EDM EPT I/F

DTLBITLB

DMA

AHB(I)


AHB/AHB(D)/AHB-Lite/APB

InstructionCache

InstructionLM/INF

DataCache

DataLM/INF

MMU/MPU

N10 Core +Audio

JTAG/EDM EPT I/F

DTLBITLB

DMA

AHB(I)

Features:Harvard architecture, 5-stage pipeline.32 general-purpose registersDynamic branch predictionFast MACHardware dividerAudio acceleration instructionsFully clock gated pipeline3-level nested interruptInstruction/Data local memoryInstruction/Data cacheDMA support for 1-D and 2-D transferAHB/AHB-Lite/APB busMMU/MPUPower management instructions

Applications:Portable audio/media playerDVB/DMB basebandDVDDSCToys, Games

N1033A CompetitionN1033A Competition

*TSMC free library with max speed synthesis constraint

Cores Features N1033AN1033A ARM926EJ Pipeline Stages 5 5

Instruction Set 16-/32-bit mixable 16 or 32

General-purpose register# 32 16

Dynamic branch prediction 32/64 -Entry BTB No

DMA support 1D and 2D No

Cache tag index Physical tag Virtual tag

Vectored interrupt support Yes (64 addresses) No

Nested interruption level 3 No

Bus AHB/2AHB/AHB-Lite/APB 2 AHB

Audio DSP instructions > 40 dedicated Few general DSP

Max frequency (Mhz) (TSMC 0.13G) *280 276/238

Performance (DMIPS/MHz) 1.6 1.1

Core Power (mW/MHz) (TSMC 0.13G) *0.12 0.36

Core area (mm2) (TSMC 0.13G) *1.4 1.61/1.45

DMIPS (TSMC 0.13G) 448 303.6

Cost Performance (DMIPS/MHz) 320 189

N1213 High Performance Application ProcessorN1213 High Performance Application Processor


AHB

InstructionLM

InstructionCache

DataLM

DataCache

MMU

N12 Execution Core

JTAG/EDM EPT I/F

DTLBITLB

HSMP

DMA

Features:Harvard architecture, 8-stage pipeline.32 general-purpose registersDynamic branch prediction.Multiply-add and multiply-subtract instructions.Divide instructions.Instruction/Data local memory.Instruction/Data cache.MMUAHB or HSMP(AXI like) busPower management instructions

Applications:Portable media playerMFPNetworkingGateway/RouterHome entertainmentSmartphone/Mobile phone

N1213 CompetitionN1213 Competition

Cores Features N1213 ARM1176 MIPS 24K

Instruction Set 16-/32-bit mixable 16 or 32 16 or 32

General-purpose register# 32 16 32

Page Table Support for MMU HW and SW HW only SW only

Interrupt Stack Level 3 2 1

unaligned memory access ld/st multiple mode bit ld/st left/right

uncached read burst use ld multiple none none

DMA support 1D/2D 1D No

Core die size (mm2) (TSMC 90G) *1.38 1.95/1.00 *1.44

Frequency (MHz) (TSMC 90G) *580 620/320 *520

Core power (mW/MHz) (TSMC 90G) *0.27 0.37/0.18 *0.40

Performance (DMIPS/MHz) 1.37 1.22 1.55

DMIPS (TSMC 90G) *795 756/390 *748

Cost Performance (DMIPS/mm2) 576.1 387.7 519.4

*TSMC free library with max speed synthesis constraint

AndeShape

AICE

IDE AndESLiveSimulator

AndESLiveBuilder

Toolchains

AndeSight AndESLive

AndESLive & AndeSight

Andes Total SW SolutionAndes Total SW Solution

user

Integrated Development Environment (IDE)Integrated Development Environment (IDE)

Toolchains: Compiler

AssemblerLinker

Debugger

Toolchains: Compiler

AssemblerLinker

Debugger

Evaluation Board

Evaluation Board

ICEICE

SoCBuilder

SoCBuilder

SimulationEngine

SimulationEngine

AndesightAndesight

AndesliveAndeslive AndeshapeAndeshape

AndesliveAndeslive AndesightAndesight AndeshapeAndeshapeAndes SW SolutionAndes SW Solution == ++ ++

AndESLive HighlightsAndESLive Highlights

SoC builderPre-defined models of AndesCore, peripheral IPs, busDrag-n-Drop to add components and/or bus from PaletteTwo clicks to connect pins or portsTable driven and setting of components properties, memory map, and IRQ

SimulatorCycle-based and instruction-based simulatorFast to run software applicationVisibility of debugging and profiling dataSimulation of I/O devices

AndESLive ModelsAndESLive Models

AndESLive Virtual IOAndESLive Virtual IO

UARTLCDRTCPWMGPIO

AndESLive BuilderAndESLive Builder

Drag-n-Drop components and bus

Drag-n-Drop components and bus

AndeSight InstallationAndeSight Installation

Installation packageAndeSightAndESLiveToolchainsCygwin (Windows only)Demo cases

Optimum System requirementsWindows XP operating system1 GB of RAM for minimum requirement1.41 GB of free disk space for AndeSight v1.3.12.00 GB of free disk space for AndeSight v1.3.2+400 MB if Cygwin is to be installed

AndeSight UIAndeSight UI

Toolbar

Project

Explore Editor Outline

Properties and Console

AndeShape

ANDES Confidential

AndeShapeAndeShape

ADP-XC5FF676 FPGA Based Development Platform

RJ45 (J25)

VIRTEX5 FPGA (U1)

Debug LED(LED7,8)

GPIO Push Buttons(SW4~8)

COM ports (J67,J68))

Audio Phone Jack (J6, J8,J9)

DC-IN Jack (J10)

SDRAM (CON2)

Reset Button(SW3)

FPGA Download Port (J4,J11)

CPU Oscillator (X1)

SD/MMC (CON1)

NOR Flash (U3,U4)

Power Switch(SW1)

AHB Connector (J36)

MII Connector (J24)

LCM Connector (J1,J2) EBI/X-BUS

(J31,J32)

AICE Connector (J29) Power On Button (SW2)

ADP-XC5FF676 FPGA Based Development Platform

SD memory card slotIDE connectorXilinx XCF32P FPGA

configuration flashJTAG configuration portFive user push button

switchesLCD I/FI2S Audio Codec7 segment LED display x2

Hardware features:Xilinx XC5VLX110-1FF676 FPGAEncrypted Bitstreams support144 pins SO-DIMM for SDRAM32MB on-board NOR flash10/100 EthernetMII connector for external 10/100 PHYRS232 serial port x2X-Bus expansion slotAHB bus connector

AndeShape ADP-AG101 PlatformAndeShape ADP-AG101 Platform

Power Subsystem

AHB Header

CF & SD/MMCSlot (On the back)

LCD Connector

UARTs

Audio Codec Subsystem

AG101 SOC

RJ 45 Connector

Memory Subsystem

Debug Port & AICE

GPIOs

Key PadConnector

ANDES Confidential

Block Diagram of ADP-AG101Block Diagram of ADP-AG101

N1213N1213Bus

ControllerBus

ControllerMAC

10/100MAC

10/100 USB2.0USB2.0

LCDController

LCDController

SDRAM ControllerSDRAM

ControllerDMA

ControllerDMA

ControllerSRAM

ControllerSRAM

Controller

PWMPWM I2CI2C GPIOGPIO INTCINTC WDTWDT TimerTimer RTCRTC

STUARTST

UARTBT

UARTBT

UART SSPSSP CFCF I2SI2S SD/

MMCSD/

MMCPowerManagerPower

Manager

AHB to APBBridge

AHB to APBBridge

AHB Bus

APB Bus

ANDES Confidential

Features of ADP-AG101Features of ADP-AG101

AMBA 2.0 based AHB environment for new IP verificationHigh integration flexibility for bus extension32MBx2 SDRAM with one SODIMM slot512KB Boot ROM with 32MBx2 flash memoryHeader for LCD plus touch screen module3 GPIO keypads and 6x6 Key pad headerOn-board 10/100 PHY and RJ45 connectorCF & SD slot, providing CF & SD/MMC card accessOn-board AC97 & I2S codec, selected by switch2 DB9 UART connectorsAndes ICE interface for function debugging

ANDES Confidential

AndeSoft

ANDES Confidential

OSLinux v2.4, v2.6Nucleus PLUSuC/OS-IIECOS

Local Memory and DMA for non-OS BSP v2.0.0

Linux v2.6AndesbootNon-OS Demo ProgramADP-AG101 and ADP-XC5 platform support

LibrariesgLibCnewLibC

Device DriversEthernetLCD controllerDMAUARTI2S, I2C

ANDES Confidential

Andes Linux Software SolutionsAndes Linux Software Solutions

INTC, DMA, TIMER, UART, LCD, TOUCH PANEL, SD, PCI, USB, MACRTC, CF, GPIO, WDT, SPI, SSP, I2S, AC97, Wireless and so on

Browser: Qt Webkit, Webkit/SDL, DilloGUI: XFree86, Xorg, QT/Embedded, SDL, Nano-X, FLTKToolkit: GTK+, glib, pango, cairo, blackbox, tk, ImageMagickNetworking: wget, curl, lynx, samba, rdesktop, amsn, dropbear, openssh, boa Multimedia: fbv, madplay, mplayer, vlc, gstreamer, gnash, ALSA audio APIUtility: busybox, mtd, pkgconfig, opkg, tar, make, coreutilsScript: bash, tcl, python

Middleware

Development Tools

Device Drivers

Applications

Operating Systems

Linux 2.4 and Linux 2.6

VOIP, iaSolution JVM, Alvaview and III for Multimedia

Toolchain: gcc, gdb, newlib, glibc, binutils, sidDebugging: AICE,Trace32, gdbserver, kgdb, straceProfiling: oprofile, gprof, simulator profiling

Libraries

Graphics: libjpeg, libpng, libtiff, libungigAudio: mp3, aac, mp4, ogg, AMR Video: mpeg-1, mpeg-4, h.264, divx, xvidUtility: libz, libncurses, libSDL, libssl, libxml, libxslt, libcurl. libsqlite

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