0 3 5 ) . & 3 - power systems design · 2018-08-07 · our automotive/infotainment issue just might...

July/August 2018

Special Report: Automotive Electronics + Infotainment (pg 25)

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VIEWpoint

The Many Flavors of Automotive ElectronicsBy Jason Lomberg, North America EditorPower Systems Design

MARKETwatch

Automotive Infotainment DevelopmentsBy Kevin Parmenter, Field Applications Engineering, Advanced Energy

DESIGNtips

Optimizing Thermal-Mgmt for Performance and Reliability

By Rudy Ramos, Mouser Electronics

COVER STORY

Optimizing Class-D Audio

Amplifier Output Filters

By Christopher Hare, Technical Marketing Engineer, Coilcraft, Inc.

TECHNICAL FEATURES

Test & Measurement

Simplifying Complex Measurements with a Source

By Tom Ohlsen, Tektronix

Battery Technology

Battery Technology: Power to the PeopleBy Mark Patrick, Mouser Electronics

Power design

Technology-Driven Optimization for Power and Thermal TradeoffsBy Frank Schirrmeister, Cadence Design Systems

SPECIAL REPORT:AUTOMOTIVE ELECTRONICS + INFOTAINMENT

Automotive Infotainment System

Designs Get Easier

By Steve Knoth, Analog Devices, Inc.

Transient Protection Solutions in

Automobiles

By Ron Demcko, Fellow, AVX Corporation

Wide Bandgap SiC Devices for

Auto Power Electronics

By Dennis Meyer, Applications Engineer, and Jason Chiang, Strategic Marketing Manager, Microsemi

Microcontrollers Evolve to Support

BLDC Automotive Needs

By Spencer Manley, and Mathias Müller,

Rutronik

2

FINALthought

Are Self-Driving Cars too Rational? By Jason Lomberg, North America EditorPower Systems Design

Dilbert

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Highlighted Products News, Industry News and

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COVER STORY

Optimizing Class-D Audio Amplifier

Output Filters (pg 9)

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POWER SYSTEMS DESIGN 2018JULY/AUGUST

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POWER SYSTEMS DESIGN

Our automotive/infotainment issue just might be the most diverse offering of the year – most of us drive cars, so OEMs have a wide variety of avenues to approach one of the industry’s most universal topics. Thus, the July/August issue covers such varied themes as audio amplifiers, MLCCs, and SiC MOSFETs, all of them falling under the same, wide umbrella.

Coilcraft helms the Cover Story, and their piece delves into one of the most important parts of the automotive experience – the sound system. Class-D switched-mode amplifiers offer low heat generation, small size, light weight, and very high power efficiency, which makes them perfect for DC-powered audio applications in automotive sound systems.

“The theoretical efficiency limit of Class-D amplifiers is 100%,” notes Coilcraft’s Christopher Hare. “While this cannot be achieved in practice due to the uncompromising second law of thermodynamics, the efficiency of Class-D amplifiers is significantly higher than the linear amplifier classes, achieving over 90% at full load.”

Ron Demcko, with AVX Corporation, authors the next piece, and in it, he examines “two automotive transient voltage control options, transient voltage suppression clamps (i.e., multilayer varistors) and integration capacitors, and compares and contrasts multilayer varistors, ESD-Safe™ MLCCs, and slow-pulse capable multilayer ceramic capacitors.”

The company’s ESD-Safe multilayer ceramic capacitors (MLCCs) are intended for use in IEC 61000-4-2 applications subjected to human-body model (HBM) strikes (150pF, 330Ω), and while many common transients are slow in speed, these MLCCs are designed for fast transients hardening.

Finally, Dennis Meyer and Jason Chiang, both of them with Microsemi, cover one of the preeminent topics in power electronics -- silicon carbide (SiC). Wide bandgap silicon carbide solutions “are on the cusp of huge growth within the transportation sector” and they’re “increasingly being adopted for mainstream automotive applications like DC-DC converter, external/onboard charger and powertrain traction control/motor drive.”

The duo concludes that the “benefits of SiC solutions over silicon IGBT and super junction MOSFET-based solutions are evident at the system level for efficiency and reliability at high power.”Enjoy the July/August issue, and be sure to check out our extensive coverage of automotive electronics at powersystemsdesign.com.

Best Regards,

Jason Lomberg North America Editor, [email protected]

The Many Flavors of

Automotive ElectronicsPower Systems Corporation 146 Charles Street Annapolis, MD 21401 USA Tel: +410.295.0177Fax: +510.217.3608 www.powersystemsdesign.com Editorial Director Jim Graham [email protected]

Editor - EuropeAlly [email protected]

Editor - North AmericaJason [email protected]

Editor - ChinaLiu [email protected]

Contributing Editors Kevin Parmenter, [email protected]

Publishing DirectorJulia [email protected]

Creative Director Chris [email protected]

Circulation Management Sarah [email protected]

Sales Team Marcus Plantenberg, [email protected]

Ruben Gomez, North America [email protected]

Registration of copyright: January 2004ISSN number: 1613-6365

Power Systems Corporation and Power Systems Design Magazine assume and hereby disclaim any liability to any person for any loss or damage by errors or ommissions in the material contained herein regardless of whether such errors result from negligence, accident or any other cause whatsoever.

Free Magazine Subscriptions, go to: www.powersystemsdesign.com

Volume 10, Issue 6

ultra-low total losses minimize the impact on total harmonic distortion plus noise (THD+N), greatly improving audio quality.

And housing dual inductors in a single shielded package saves critical board space.

Learn more about our economical solu-tions for a wide variety of audio amplifi er applications.

Visit coilcraft.com/Class-D today!

Coilcraft dual inductors for Class-D output fi lters provide low distortion and the best possible sound quality

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Based on their high power effi ciency, small size, and light weight, Class-D amplifi ers are a popular choice for extending battery life in DC-powered audio applications, such as those found in automotive sound systems.

Coilcraft offers a unique selection of dual inductors that signifi cantly improve the per-formance of Class-D output LC fi lters. Good linearity of the inductance with current and

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MARKETwatch


By: Kevin Parmenter, Field Applications Engineering, Advanced Energy

A few of my favorite programs include “Weaponology,” “Future Weapons,”

“Modern Marvels” and the science show “Connections.” They all explore the various paths of technological change and interrelations and the significant effects that this change has on society, including that in order for one thing to be developed, enabled and built upon, prior developments had to be invented and built upon.

This is certainly the case with the automotive and infotainment industry. The rapid developments occurring in the automotive electronics arena can trace their origins back to electric motors and electrical developments, time delay wipers, and radios in cars; however, propelling forward the developments in other segments (consumer, communications, wireless and cellular, gaming, embedded control and computing) connectivity, power electronics, LED lighting, Military technology, Radar Wi-Fi, Satellites, GUIs and software, class D audio and AV systems, motor drives, battery technologies and more are coming together to drive the future of

Automotive Infotainment Developments

the automotive and infotainment customer experience. In fact IHS projects 1500 dollars of electronic content per vehicle or more within a few years.

The Society of Automotive Engineers defines five levels of vehicle automation. From Level 0 essentially means no automation to level 5 full automation, no driver needed but may take over if required. Full automation allows us to enjoy the infotainment system that much more!

For us to not only climb the automation hill to get to Level 5 we must continue to advance in all areas, including Night Vision – Lidar – radar and sensing systems, vehicle-to-vehicle communications systems, electrification of the drive train and power electronics, graphics – computing and AI. Video and ultrasound imaging systems, driver-vehicle communication systems and interfaces – voice and data, and of course the rapid development and continued development of memory technologies. Vehicles are generating lots of data and will do more so in the future. The data must be stored and processed not only in the vehicle but also in

server farms. Information will be fed into the vehicles via wireless including 5G from cellular base stations, as well as via wireless Bluetooth, Wi-Fi and DSRC communications. Vehicles will more and more include charging – wireless and otherwise – for consumer electronics, including built in inverters to take our AC line powered systems on the road if needed.

Since we’ll be spending less time driving and more time riding, we’ll have the ability to enjoy our commute times a bit more than we do now, and can even be more productive. Incidents of accidents should also decrease as safety systems and software get better, increasing occupant safety and reducing insurance rates. Biometrics and tracking systems will reduce – possibly even eliminate – vehicle theft . While the speed of this evolution is unknown, we do know we are building on technology developed from days to decades ago to create a future of automotive and infotainment systems that will benefit us all.

PSDwww.powersystemsdesign.com

Optimizing Thermal-Mgmt for Performance and ReliabilityBy: Rudy Ramos, Mouser Electronics

Power conversion is common to almost all electronic systems. Efficiency is critical,

whether the objective is to maximize runtime for a small battery-powered device, reduce utility costs to power data-center servers, or others such as ensuring cost parity for renewables.

Efficiency is never 100%, even in the best systems. That small amount of un-transferred energy is converted to heat, which then presents reliability challenges. Without effective thermal management, heat-dissipating components like power transistors or resistors can run too hot – leading to early failure - or in extreme cases may exceed their maximum rated temperature resulting in rapid destruction.

Reliability follows the Arrhenius Law, which incentivizes cooling: reducing a component’s operating temperature by 10°C can double its lifetime. Moreover, taking steps to ensure a lower junction temperature can increase power capability and allow the power supply to operate safely across a wider

ambient-temperature range.The small proportion of power that enters the power transistors but is not transferred to the load is dissipated from the junction of each device. The junction temperature is related to this power dissipation by the equation:

Tjmax = (PDmax x Rθja) + Ta

Where Tjmax = maximum junction temperaturePDmax = maximum power dissipatedRθja = thermal impedance from junction to ambientTa = ambient temperature

When designing a power supply, the objective is to design for a junction temperature that will not only preserve the device but also ensure the desired reliability. The maximum power dissipation can be estimated using the datasheet efficiency curves. Similarly, the thermal impedance, θja, from junction to ambient, can be found from datasheet curves that also consider cooling effects such as PCB metallization and airflow.

If an acceptable junction temperature cannot be achieved,

when delivering the required power to the load, the design effort must focus on reducing θja. A variety of techniques can be used to achieve this. These include:• Package selection, taking

advantage of packages with enhanced internal features like thermally efficient clips to replace conventional wirebonds, or enlarged metallized areas on the lower or upper side of the die - or both sides for dual-side cooling; these areas are connected directly to a heat slug or exposed metal pad that can be soldered to PCB metallization or attached to a heatsink.

• Board design, including increasing the copper thickness, or adding thermal vias directly beneath the hot components connecting to a heat spreader such as a heavily metallized layer. An insulated metal substrate may also be considered if extremely high heat dissipation is needed.

• More overt thermal-management techniques, such as heatsinks or heat pipes, possibly in conjunction with a cooling fan.

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simulation allows users to see the thermal performance graphically, and also shows secondary effects such as co-heating of components that can be difficult to visualize otherwise. The result of the simulation is a color temperature plot that helps quickly identify any areas of concern.To run a simulation, the user enters settings like the load current, top and bottom ambient temperature, and device case temperature. A thermal simulation can be run in a few minutes, capturing results that can be analyzed graphically using the color temperature plot. If necessary, the design can be changed within WEBENCH to optimize the thermal performance, by changing the board size or copper characteristics on any of the layers, or adding and adjusting thermal vias.

Multiple simulations can be run and compared to identify a design that produces an acceptable temperature. If a suitable Tjmax cannot be assured, additional thermal management such as a heatsink or heat pipe to remove thermal energy from the system more quickly. The temperature plot can help focus attention on the areas of main concern.

Adding a HeatsinkA heatsink is easy to understand and extremely reliable, with no

moving parts, no failure mode, and no operating cost. Usually aluminum, or copper, they can range from simple stamped metal wings intended to be applied to a single transistor, to milled or extruded parts with finning designed to intercept convection airflow for maximum heat transfer. Convection occurs

naturally, as warmed air rises, which perpetuates the flow. Care must be taken to ensure unimpeded airflow from inlet to outlet, also making sure the inlet is placed below the level of the heatsink and the outlet above. This is necessary to prevent heated air stagnating above the hot component, which can

Figure 1: Adding a heatsink to boost top-side cooling of thermally enhanced power package.

Figure 2: Heat pipes are available in various shapes and sizes, or can be customized, to transfer heat to a convenient place to be dissipated by a heatsink fan.

The question arises as to which combination of these techniques should be used for optimum effectiveness, acceptable size and weight, and minimal impact on Bill Of Materials (BOM) cost. The answer is not always obvious, but the potential consequences of over- or under-engineering the solution are clear. Building multiple prototypes to explore different thermal designs may not be viable. On the other hand, if the chosen solution is found to be unsuitable later in the project, redesigning the board to add extra thermal vias or to accept a different package style may be impractical.

Fortunately, help is at hand. Thermal simulation software can help engineers visualize thermal behavior from a system perspective and identify any problem areas before committing to a first prototype.

Some online tools are even available free of charge. TI’s WebTHERM™ is an example, which is ready to perform thermal analysis on a power supply design created using the WEBENCH® online environment. The power

supply is initially designed as a WEBENCH project, using the chosen controller or DC/DC converter IC and known requirements like power-supply input and output voltage ranges.

Once the basic design is

completed, WEBENCH compiles the bill of materials and calculates parameters such as power dissipation and θja. These can be used to calculate Tjmax manually, using known ambient-temperature data. However, running a webTHERM


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exacerbate junction-temperature rise.Despite their many advantages, heatsinks can become large, heavy and costly if sized to dissipate large quantities of heat. The constraints on positioning for best airflow may compromise board layout, and fins can become clogged with dust or dirt and so impede cooling. Attaching the heatsink properly to the component, with clips or screws and a layer of thermal interface material (TIM), also adds to assembly time.

A vast variety of heatsinks are available from manufacturers such as Aavid Thermalloy or Wakefield-Vette, including parts that are optimized to fit specific components, such as processors or FPGAs. On the other hand, heatsink selection can be based on calculations that consider its effect on reducing θja, the overall thermal impedance from the chip junction to the air surrounding the heatsink, resulting in lower junction temperature relative to power dissipation.

Figure 1 shows a power transistor in a thermally enhanced packaged designed for efficient dual-sided cooling using a top-mounted heatsink and a heat spreader in the PCB. The system is shown modeled as a network of thermal impedances, Rth, between the active junction and the ambient environment above and below the board.

The thermal impedance of the heatsink, Rth heatsink, expresses how efficiently heat can be transferred from the base of the heatsink to the ambient environment.

Extend Design Freedom with a Heat PipeIn some designs, constraints on overall size or board layout, or impeded airflow, may prevent attaching a heatsink of the required size directly to a converter IC or power transistor. A heat pipe (Figure 2) can offer a practical alternative, which enables heat to be moved from the source to another location where a suitable heatsink or spreader can be positioned, and greater airflow provided for cooling. The part illustrated, the Wakefield-Vette model 120231, can handle thermal loads up to 25W but is only 6mm diameter × 100mm long.

The heat pipe does not act as a heatsink itself but is a sealed tube designed to transfer heat from its hot end to the cool end by leveraging phase-change principles. Heat is absorbed at the hot end and vaporizes the working fluid inside the tube. The vapor travels towards the cool end and condenses back into liquid releasing its heat in the process. The liquid then travels back to the hot end of the pipe to repeat the sequence. Among the advantages of a heat pipe is that no power is required to sustain this phase-

change mechanism, and the designer has the freedom to position the cool end of the heat pipe in the most suitable location.

Forced-Air CoolingIf passive thermal management using heatsinks or heat pipes is unable to achieve the desired junction temperature, forced-air cooling using a high-quality fan from a manufacturer such as Delta Electronics may be considered. A fan gives the flexibility to optimize cooling by selecting fan size and adjusting speed to increase or decrease the airflow, rated in cubic feet per meter (CFM).

ConclusionProper thermal management is essential to maximize both the performance and reliability of board-mounted power supplies or DC/DC converters. Designers have plenty of tools at their disposal, but it is essential to avoid over-engineering to prevent excessive bulk, BOM cost, or complex assembly challenges. Accurate thermal simulation tools are available free of charge, which provide a visual guide to thermal-management challenges before committing to building hardware. Other techniques such as a custom-selected heatsink, heat pipe, or cooling fan can help overcome broader system constraints on circuit layout or airflow.

Mouser Electronicswww.mouser.com

Optimizing Class-D Audio Amplifier Output Filters

By: Christopher Hare, Technical Marketing Engineer, Coilcraft, Inc.

Careful component selection is the key to high-quality high-efficiency Class-D audio output

When audio ap-plications require the highest power efficiency, lowest

heat generation, smallest size, and lightest weight, Class-D switched-mode amplifiers surpass the linear class amplifiers. This makes Class-D amplifiers the best choice for extending battery life in DC-powered audio applications, such as found in automotive sound sys-tems. This article discusses how careful design of the output LC filter stage of a Class-D amplifier leads to high efficiency and high sound quality, and how choosing the right inductor affects these critical parameters.

Efficiency and Sound Quality Considerations Linear amplifiers have very low theoretical limits on power effi-ciency. While distortion for Class-A amplifiers is low, the ideal upper limit for Class-A efficiency is only 50%. The high resistance of the output stage transistors results in dissipation that generates signifi-cant heat, typically requiring large heatsinks to keep the design at an acceptable temperature. This wastes energy and adds weight to

the overall design. Class B ampli-fiers dissipate less power, but have inferior sound quality due to non-linear crossover distortion of the push-pull controller transitioning between on and off conditions.

Class-AB is a compromise between Class-A and -B characteristics. It has less dissipation than Class-A, eliminating crossover distortion and giving good sound quality. However, Class-AB still has sig-nificant dissipation and an upper theoretical limit on efficiency lower than the Class-B limit of 78%. This can be a major disadvantage for DC-powered audio systems, espe-cially at high power levels.

The theoretical efficiency limit of Class-D amplifiers is 100%. While this cannot be achieved in practice due to the uncompromising sec-ond law of thermodynamics, the efficiency of Class-D amplifiers is

significantly higher than the linear amplifier classes, achieving over 90% at full load. With proper de-sign, sound quality can be compa-rable to Class-AB.

Basic Operation of Class-D Now that we have chosen Class-D for our audio amplifier design, let’s outline the operation of Class-D amplifiers. The basic Class-D block diagram is shown in Figure 2. In the first stage, the low-voltage audio input is compared to a trian-gular waveform to generate a train of fixed-amplitude square pulses. Next, the pulse-width-modulated (PWM) pulses are fed to the switching controller and output stage, which functions similarly to a backward synchronous buck converter. The most common configuration for the output stage is bridge-tied load (BTL) which has 2x more voltage swing across the load compared to single-ended

Figure 1: Comparison of Amplifier Class Attributes

COVER STORY


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COVER STORY


The nearest standard capacitance value is 0.68 uFL = 11.25 uH. The nearest standard inductor value is 10 uH. Once the L and C values are select-ed, graphing the gain vs frequency over the expected range of speaker impedance, typically in the 2-8 Ohm range, allows the designer to determine whether the perfor-mance is acceptable for that range.

Consult the LC Filter Design refer-ence below for a more detailed discussion of the Type-2 and hybrid filter implementations and capacitor selection. For Type-2, the only difference for the single-ended analysis is that Cg = C compared to CBTL = C/2 for Type 1. For the hybrid type, adding caps Cg to ground (Cg ~ 1/10th of CBTL) improves the filtering by coupling high frequencies to ground.

Inductor SelectionFor the 4 Ohm to 8 Ohm speaker range, typical LBTL values range from about 5 to 20 uH, and Coil-craft offers a selection of off-the-shelf inductors in this range for Class-D applications for various power requirements. Selecting an

inductor that does not vary signifi-cantly with current is important in maintaining linearity and minimiz-ing distortion and noise. Higher current requirements typically necessitate a larger inductor size to minimize distortion. Having two uncoupled inductors in a single package minimizes the LC filter footprint, saving critical board space in space-constrained appli-cations such as automotive Class-D audio systems.

The objective measurement that defines sound quality is total har-monic distortion and noise (THD + N). Low THD + N is crucial in the typical hearing-sensitive 1 kHz to 6 kHz frequency range. The optimal inductor choice involves trade-offs in peak current handling, core and winding losses at operat-ing conditions, and part size. Inductor manufacturers, such as Coilcraft have designed single and dual off-the shelf induc-tors specifically tailored for Class-D audio applications. These inductors balance the require-ments for both high-quality sound and high efficiency.

Coilcraftwww.coilcraft.com

and 4x the output power. The result is a higher-frequency, higher-voltage square wave being fed to the load, typically a 4 Ohm or 8 Ohm speaker.

Before the square wave is fed to the speaker, it must pass through a low-pass LC filter in order to re-move the high-frequency switching content and pass only the audio frequency range (typically 20 Hz to 20 kHz) to the speaker. The LC filter also limits the residual ripple current at idle conditions, which improves efficiency.

The switching frequency of the Class-D amplifier determines the filter order and cutoff frequency requirements. Higher switching frequencies allow for smaller com-ponents and lower order filters to achieve the required attenuation in the stop band, but this may cause higher EMI and switching losses. In most Class-D audio applica-tions, the switching frequency is in the range of 200 kHz to 2 MHz.

Low-pass LC Filter DesignFor very cost-sensitive or smaller form factor requirements, filter-less solutions may be feasible, but these can lead to EMI problems and high-frequency power dissipa-

tion due to the switching wave-forms. A filterless design is not practical in a “noisy” automotive environment. As with all things engineering, there are trade-offs in performance vs. size and cost of the LC filter components. Using proven Class-D reference designs and evaluation modules as a starting point can help reduce the time needed to design and test an optimal solution, however, there certainly are interesting challenges in designing Class-D LC filters. Un-derstanding the requirements can provide insights into any trade-offs that may need to be made.

The output LC filter is a critical element in determining the size, sound quality, and efficiency of a Class-D sound system. The output filter is designed to attenu-ate the high frequency switching component while passing the audio frequency band of 20 Hz to 20 kHz. One low-pass LC filter is needed for each audio channel. Keeping the component count to a minimum helps reduce the total required real estate.

The typical Class-D LC filter imple-mentation is a second-order But-terworth LC filter, which creates a flat pass-band and phase response

with a small number of compo-nents. A second order filter gives -40 dB per decade. Selection of the LC values requires an understand-ing of the speaker load impedance variation for the application. The ideal L and C values result in a critically-damped response with a flat passband and flat phase re-sponse. An overdamped response attenuates the audio content, and an underdamped response leads to peaks that may trigger built-in circuit protection or harsh sound.

Class-D BTL filters are defined by three types: Type-1, Type-2, or hybrid. The type defines a differen-tial (Type-1), common mode (Type-2), or hybrid filter implementation that depends on the pulse width modulation (PWM) scheme (AD or BD). Type-1 filters with traditional AD modulation are the simplest and will be used in the following example. LBTL = Series inductanceCBTL = Differential bridge tied load capacitorRBTL = Differential (speaker) loadRL = Single-ended equivalent load = RBTL / 2C = Single-ended capacitor tied to ground = 2 x CBTLThe L and C values for a critically damped Butterworth filter are:

where ω0 is 2 x π x f0

For a cutoff frequency (f0) of 40 kHz and a 4 Ohm speaker load:C = 1.4 uF and CBTL = C/2 = 0.70 uF

Figure 2: Class-D Amplifier Diagram Source: https://en.wikipedia.org/wiki/Class-D_amplifier Figure 3: Class-D Type-1 Differential

Bridge Tied Load (BTL) CircuitFigure 4: Class-D Type-1 Single-Ended Equivalent Circuit

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Simplifying Complex Measurements with a Source

By: Tom Ohlsen, Tektronix

Here’s how two-channel SMUs can speed up DC-DC converter and FET testing

In today’s fast paced world of electronics design, complexity represents evil and must be avoided at all cost while sim-

plicity represents all that is right and good. Ok, maybe it’s not quite that extreme, but when it comes to test and measurement, simplicity is the engineer’s best friend be-cause it saves time and effort and yields more consistent and accu-rate measurement results.

One instrument that maximizes simplicity for many common mea-surements is the source measure-ment unit (SMU), which combines a power supply, a digital multime-ter, current source and electronic load in a single box. This results in a test instrument that is more versatile than the individual instru-ments are alone, simplifies test setups and reduces measurement steps as well as the potential for error.

Rather than spend a lot of time trying to explain how an SMU simplifies measurements, it might be easier to show by example. To that end, here we first look at how to simplify DC-DC converter char-acterization with an SMU followed

by techniques for simplifying FET device testing with an SMU. As these examples illustrate, work-ing with an SMU takes fewer step and delivers critical measurement insight.

Simplifying DC-DC converter characterizationLike any device, DC-DC converters need to be characterized by manu-facturers and by engineers evaluat-ing them for a design. Given the increased pressure to develop products that consume less power, design engineers are looking for ways to increase power conversion efficiencies. Numerous measure-ments are required to characterize the electrical parameters of DC-DC converters. Tests include:

• Line regulation• Load regulation• Input and output voltage ac-

curacy• Quiescent current• Efficiency• Turn-on time• Ripple• Transient response

Typically, electrical characteriza-tion of DC-DC converters involves sourcing and measuring input voltage (VIN), measuring input current (IIN), measuring the out-put voltage (VOUT), and sinking a load current (IOUT). From these measurements, the efficiency and other parameters can be deter-mined. The efficiency is important for most designs, especially bat-tery-powered products, because it directly affects the running time of the device.

Traditionally, the DC characteriza-tion of these devices required the use of a couple of digital multi-

Figure 1: The use of one SMU channel on the input terminal and another on the output terminal replaces several instruments.

meters, a power supply, and an electronic load. However, the DC characterization can be simplified by replacing all of these electronic instruments with a single two-channel SMU. SMUs are well-suited for testing a wide variety of I-V parameters of DC-DC convert-ers because they can source and measure both current and voltage, as well as function as an electronic load. Note that to complete the full range of DC-DC converter tests, an oscilloscope is required with the SMU providing input voltage and the load current. Using one instrument rather than multiple units simplifies the test implementation, software, and synchronization, as well as tak-ing up less rack or bench space. As shown in Figure 1, using one SMU channel (CH1) on the input terminal and another SMU chan-nel (CH2) on the output terminal of the DC-DC converter replaces several instruments.

DC-DC converter characterization involves testing many electrical parameters. We'll focus on load regulation and line regulation because they're among the most commonly performed tests.

Load RegulationLoad regulation refers to a DC-DC converter's ability to maintain the specified output voltage as the load current (ILOAD) varies under a constant VIN. Typically, the load-regulation test is performed over the entire range of load currents.

Figure 2 shows a typical load regulation test setup using two SMU channels. SMU CH1 supplies the input voltage and monitors the input current. SMU CH2 is configured as an electronic load by setting it to sink current (source a negative current). In this mode, the SMU instrument will operate in the fourth quadrant and sink

current. The SMU channels are configured using the remote sense, or four-wire, connection. Using a four-wire connection eliminates the lead resis-tance that would other-wise affect measurement

accuracy. With the four-wire method, the source outputs using one pair of test leads (be-tween Output HI and Output LO), and the voltage drop is measured across a second set of leads (across Sense HI and Sense LO). Connect the sense leads as close to the device as possible, which will minimize lead resistance from adding to the measurement.

Figure 3 shows the results of a typical load regulation test in which the DUT was configured to output a constant 3.6V. SMU CH1 was set to bias 5 V (nominal value) to the voltage input termi-nal. SMU CH2 was configured to

Figure 2: This is a typical load regulation test setup using two SMU channels.

Figure 3: Here is the result for a typical load regulation test.

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TEST & MEASUREMENT


sweep a load current from 0 to 1 A and measure the resulting output voltage. Measurements were taken under software control. The load regulation percentage can be easily calculated from the I-V data. Line RegulationLine regulation refers to a DC-DC converter’s ability to maintain the specified output voltage in response to input voltage changes. The output voltage should remain constant, within a few millivolts, while the input voltage is varied over the specified voltage input range. For the line regulation test, both SMU channels are connected to the DC-DC converter in the same way they were for the load regula-tion test.

However, for this test, the input voltage is swept over the specified input voltage range and the output voltage is measured. The load cur-rent is typically set to 0 A. Figure 4 shows the result from a typical line

regulation test. One channel of the SMU instrument (SMU CH1) was configured to sweep voltage on the input terminal of the device while the other (SMU CH2) was config-ured to measure the output volt-age. The line regulation percentage can then be calculated from the I-V data. Simplifying FET testing with SMUsCharacterizing an FETs current-voltage (I-V) parameters is crucial to ensuring it meet specifications and works properly in its intended applications. These I-V tests may include gate leakage, break-down voltage, threshold volt-age, transfer characteristics, drain current, on-resistance, etc. FET testing often involves programming and synchroniz-

ing several instruments, including a sensitive ammeter and multiple voltage sources, which can be tedious and time consuming. Although a turnkey semiconduc-tor characterization system solves the integration problem, systems of this type typically cost tens of thousands of dollars. A third ap-proach involves using SMUs. The number of SMUs required in the test usually depends on the num-ber of FET terminals that must be biased and/or measured.

An FET is a majority charge-carrier device in which the current-carrying capability is varied by an applied electric field. It has three main terminals: the gate, the drain, and the source. A voltage applied to the gate terminal (VG) controls the cur-rent that flows from the source (IS) to the drain (ID) terminals.

There are many types of FETs, including MOSFET (metal-oxide-semiconductor), MESFET (metal-semiconductor), JFET (junc-tion), OFET (organic), GNRFET (graphene nano-ribbon), and CNTFET(carbon nanotube). These FETs differ in the design of

Figure 4: This shows the result for a typical line regulation test.

their channels.

An FET’s I-V characteristics can be used to extract many device parameters, to study the effects of fabrication techniques and process variations, and to determine the quality of the contacts. Figure 5 illustrates a DC I-V test configura-tion for a MOSFET using a two-channel SMU (CH1 and CH2). Here, the Force HI terminal of SMU CH1 is connected to the gate of the MOSFET and the Force HI terminal of SMU CH2 is connected to the drain. The source terminal of the MOSFET is connected to the Force LO terminals of both SMU channels or to a third SMU chan-nel if it is necessary to source and measure from all three terminals of the MOSFET. Once the device is set up and connected to the SMU, the con-trol software, often an embedded software tool, must be configured to automate the measurements. After connecting the instrument to any computer with an Ethernet cable, entering the IP address of the SMU into the URL line of any web browser will open the instru-ment’s web page. From that page, the user can launch the embedded software and configure the desired test or tests, which can often be saved and recalled for future use.One I-V test commonly performed on a MOSFET is the drain family of curves (VDS-ID). With this test, SMU CH1 steps the gate voltage (VG) while SMU CH2sweeps the drain voltage (VD) and measures the resulting drain current (ID).

Figure 5: This is a DC I-V test configuration for a MOSFET using a two-channel SMU.

Once the two SMU channels are configured to perform the test, the data can be generated and plotted on the screen in real time. Figure 6 shows a MOSFET drain family of curves created by using a two-channel SMU optimized for low current measurements. Once exported to a .csv file, this I-V data can be imported into a

spreadsheet for further analysis or displayed in table view. Another common I-VFET test this same configuration supports is Drain Current (ID) as a function of Gate Voltage (VG). For this test, the gate voltage is swept and the resulting drain current is measured at a constant drain voltage. Figure


16

TEST & MEASUREMENT


7 shows the results of an ID-VG curve at a constant drain voltage. However, in this case, the generat-ed data was exported to a file and plotted on a semi-log graph. This test can be easily reconfigured to step the drain voltage as the gate voltage is swept. The ID-VG data shows the many decades of drain current that the SMU measured, from 1E-12 to 1E-2 amps. SummaryTest complexity is the enemy of engineering efficiency and productivity. As shown here, source measure units that combine the functionality of multiple instruments into a single box can simplify testing procedures, saving time and producing more accurate and repeatable results. In the case of DC-DC converter

testing, a single two-channel SMU replaces a couple of digital multimeters, a power supply, and an electronic load. In the case of the FET characterization, SMUs are a simpler, cost-effective alternative to test setups such as

Figure 7: In this example, drain current is shown as a function of the gate voltage of a MOSFET.

sensitive ammeter and multiple voltage sources or a dedicated semiconductor characterization system.

Tektronixwww.tek.com

Figure 6: This MOSFET drain family of curves was created using a two-channel SMU optimized for low current measurements.

Battery Technology: Power to the People

By: Mark Patrick, Mouser Electronics

Energy storage is growing in importance for today’s applications

As the roll out of billions of sensors and wireless nodes in the Internet of Things

(IoT) progresses, more attention is being paid to the battery technology that powers them. At the same time developers of electric cars are also looking for better battery solutions.

Regularly changing the batteries of a billion devices in the IoT represents a major challenge - in terms of both cost and logistics. Consequently developers are keen to implement rechargeable battery cells that can use energy harvested direct from the environment, such as via solar cells or thermal gradients.

Lithium-based batteries have been taking over from nickel cadmium (NiCd) and nickel metal hydride (NiMH) cells in recent years by providing a higher energy density levels. However, these come with their own challenges, especially when placed in an industrial or electric vehicle context.

Rechargeable lithium batteries are prone to the development of

dendrites which can cause short circuits and, in the worst case scenario, lead to fires. The small filaments grow during charging and can eventually connect across the anode and cathode. This has made it more difficult to transport cells from offshore manufacturing plants, due to the risk of the batteries igniting in the hold of cargo planes.

Lithium cells also have a limited number of charging cycles. This is fine for consumer applications, such as mobile phones that are replaced every two to three years, but poses a problem for

industrial applications that are expected to last for 10-20 years - and yet the demand for smaller size and longer life continues to increase. So researchers and battery companies are looking at different ways of providing higher energy density in a cell that is safer to use. Applying Solid State Technology One way is to take a solid state approach. Current lithium polymer cells have an energy density of around 160Wh/l and use a thick polymer liquid that allows the lithium ions to move but which can leak and allow

Figure 1: TDK battery

POWER TO THE PEOPLE


1918

POWER TO THE PEOPLE



need to be packed efficiently to increase the battery capacity. The arrangement of aluminium ions inside graphene is critical for better battery performance.”

In Spain, a Euro 3 million research project has started developing a new type of rechargeable solid state battery also using aluminium. The sulphur-aluminium battery with advanced polymeric gel electrolytes (SALBAGE) project could produce a solid state battery with an energy density over five times that of today’s lithium-ion cells. It is led by Spanish battery developer Albufera Energy Storage, in Madrid, along with several European companies and universities. The new battery is expected to have a high energy density of 1000Wh/kg and low price (at around 60% of today’s lithium-based cells).

Magnesium is an increasingly popular choice for battery cell technology too. Researchers at the University of Houston have found a way to make magnesium batteries that are intrinsically safer and twice the capacity of current lithium ion batteries. This project has already spanned several years and involved scientists from three universities and three leading US scientific laboratories. The key is expanding a titanium disulphide cathode to allow magnesium chloride molecules in whole, rather than having to use energy to break

the molecular bonds. “We are combining a nanostructured cathode and a new understanding of the magnesium electrolyte,” said Yan Yao, Associate Professor of Electrical Engineering at the University of Houston, which is heavily involved. This allows batteries with a cathode capacity of 400mAh/g (up from 100mAh/g for earlier magnesium batteries) and twice that of commercial lithium-ion batteries (which generally have a capacity of 200mAh/g). Though admittedly, the voltage of the new battery remains low at about 1V, compared to 3V to 4V for lithium-based batteries for IoT applications.

Sodium is another material with potential for next generation batteries. Switzerland scientists have developed a prototype of a 3V solid state sodium battery with the potential for higher energy densities than lithium cells. "We still had to find a suitable solid ionic conductor that, as well as being non-toxic, was chemically and thermally stable, and that would allow the sodium to move easily between the anode and the cathode," said Hans Hagemann, Professor of Physical at the University of Geneva. The researchers discovered that a boron-based substance, a closo-borane, enables sodium ions to circulate freely. As the closo-borane is an inorganic conductor, it removes the risk of the battery catching fire while recharging. "The difficulty was establishing

close contact between the battery's three layers: the anode, consisting of solid metallic sodium; the cathode, a mixed sodium chromium oxide; and the electrolyte, the closo-borane," said Léo Duchêne, a researcher at Empa's Materials for Energy Conversion Laboratory. Sheffield-based start-up Faradion is also working to commercialise its liquid sodium battery technology for electric scooters and cars, while Oxis Energy in Oxford has developed lithium-sulphur cells for the same types of applications.

ConclusionA lot of engineering effort is going into replacing current liquid lithium-ion polymer batteries, in order to better attend to both IoT and electric vehicle applications. Solid state lithium designs that can be surface mounted and versions that charge quickly in electric vehicles are already coming to market. Research on other materials, such as sodium and sulphur, are in early stages of market acceptance, while entirely new cells with much higher performance levels are on the horizon. All of these aim to provide higher density, longer charging cycles and faster charging, without the risks of fire, in order to provide system designers with the energy they need.

Mouser Electronicswww.mouser.com

the growth of dendrites. This also prevents the cells being soldered to a board in a surface mount reflow process, thereby increasing production costs.

As the name suggests, solid state batteries have solid layers and so inhibit the growth of dendrites. However, getting the ions to move easily between the anode and cathode has significant difficulties associated with it. These need to be addressed - as the easier they move, the faster the cell will charge.

TDK for example has launched the first solid state lithium cell that can be surface mounted. The cell uses ceramic layers that allow the ions to move, and can be recharged up to 1000 times. It has a capacity of 100µAh at a nominal voltage of 1.4V allowing

currents of a few mA to be drawn and comes in a compact EIA 1812 package. It is aimed predominantly at applications such as real-time clocks, Bluetooth beacons, wearables and IoT nodes using energy harvesting.

Toshiba has likewise developed a solid state battery. This employs a titanium niobium oxide anode material that can be charged in a matter of minutes, and is aiming this at electric vehicles. The SCiB cell has double the storage capacity by volume of the current generation of lithium batteries with graphite-based anodes (where a 20Ah cell has an energy density of 176Wh/l) and will start shipping next year.

Samsung has also been working on new forms of lithium cell,

using a 3D ball of graphene and silicon dioxide to coat both the anode and the cathode. This doubles the energy density and stops the growth of dendrites. The technology has been patented and is set to appear in batteries for IoT and mobile phones soon.

Other PossibilitiesResearchers are, however, also looking at many other materials for battery cells, from aluminium and sodium to magnesium and graphene. The staff at the Clemson Nanomaterials Institute, in South Carolina, for instance, have developed an aluminium battery that could be cheaper and more reliable than lithium-ion technology. Apparao Rao, Professor of Physics at Clemson University and Director of the Clemson Nanomaterials Institute, has used aluminium foil and a graphene anode to construct a battery that can operate over 10,000 cycles and has an energy density of 200Wh/kg.

The battery cell uses thin sheets of graphite called few-layer graphene as the electrode to store electrical charge from aluminium ions present in the electrolyte.

“We knew that aluminium ions could be stored inside few-layer graphene,” said Ramakrishna Podila, Assistant Professor of Physics who also worked on the project. “But the ions

Figure 2: Toshiba SCiB batteryy

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POWER DESIGN



Technology-Driven Optimization for Power and Thermal Tradeoffs

By: Frank Schirrmeister, Cadence Design Systems

How small architecture changes early in the design phase can have a huge impact on the power consumption of the end product

Traditionally the key concerns and

optimization targets in chip development have been summarized as “PPA”—performance, power and area. Depending on the application domain, the relative weighting of those three design objectives can vary greatly. In mobile devices, power has been key for quite some time. In fitness trackers, medical devices, and other products for the IoT edge, power may be so scarce and important that harvesting of power during operation is critical. In contrast, for wall-outlet-powered devices like servers and most consumer electronics, power may be less of an issue, but thermal effects become critical. Also, can a given package deal with the energy consumption appropriately or will parts of the devices have to shut down to prevent overheating? This links back to mobile applications as

well, where in some cases, for instance AnTuTu, benchmarks simply started dropping to lower levels at a later time during operation as thermal limits were reached and some of the processing power needed to be switched off.

As illustrated in Figure 1, looking at the various components of a chip from analog and mixed-signal circuitry, control hardware, dataflow hardware, memory, and software, the last three typically have the biggest impact on power consumption—especially at higher levels of abstraction. Designers make several decisions that significantly influence the power consumption of the

design. Micro architects who take an algorithm defined in C or SystemC and decide how to implement it face various high-impact areas for low-power optimization, such as bit-width selection, tradeoffs between performance and voltage and energy consumption, optimization of the design activity, trading area versus energy consumption, memory optimization, clock gating, voltage scaling and hardware/software tradeoffs. For instance, if specific functions can be moved from software to hardware at the architectural level, significant power reduction can be achieved. System-level models are required but relatively easy to

Figure 1: Highest optimization potential exists at the system-level

get to, they allow dealing with a reasonable amount of data at high simulation speed but limited accuracy.

As the design proceeds towards implementation at the register-transfer level (RTL), the number of options to reduce the energy consumption is still quite high, allowing reasonable overall leverage. Specific areas of the design can be dynamically switched to low-power modes, trading performance versus energy during execution. Popular methods are reduced clocking or full clock gating of areas in the design. Optimized resource sharing, isolation of operands and optimized coding of controller and bus states can contribute to reduce the capacities to be switched. In principle, architecture changes are still possible at this level. For example, a user may change the number of multipliers to reduce switching via utilization of correlation between subsequent

data in a data stream. However, users often focus completely on functional verification during this phase. Also, simulation times are becoming significant and the actual effort to design the RTL often prohibits focus on energy optimization at this level of abstraction.

After logic synthesis for the gate-level netlist, dynamic energy consumption can be determined fairly accurately based on the design activity. At this level, design teams can utilize optimizations minimizing the capacities that have to be driven by the most active nodes in the design. Also, energy consumption can be optimized using a balance of path delays to avoid spikes and spurious transitions and re-timing. The accuracy of power estimation is quite high at this level of abstraction, but the amount of data to be dealt with increases greatly. Even if the gate-level simulation is performed without

back-annotated timing, users have to take into account significant simulation times.

Once design teams have reached the actual layout phase, which leads to the delivery of a GDSII tape for actual implementation, sufficient data is available to allow accurate simulation and estimation of energy consumption. Depending on the estimates at this level of abstraction, design teams can still do transistor sizing and layout rearrangements to achieve optimization based on placement and interconnect. The accuracy at this level of abstraction is very high, but the amount of data to be processed and the simulation speed are so limited that typically only a small number of test vectors can be used for analysis. The leverage on energy consumption is comparatively low as no major design changes, such as adjustments to the number of arithmetic resources, can be

Figure 2: The need for “deep cycles”

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POWER DESIGN


made anymore.

Bottom line, power optimization faces a dilemma: While decisions at higher levels of abstraction at the system level have the highest impact, they are made based on the least-accurate data available for the design at that

point in time. In contrast, when the most accuracy is available at the layout level, the impact of changes based on that data is relatively small, and simulation times take a very long time. To address that dilemma, users need to be offered techniques that allow combination of deep

simulation cycles including software execution, for example, with accurate information derived from semiconductor technology library definition.

Bridging Abstraction LevelsAs illustrated in Figure 2, if not enough cycles are executed for

Figure 3: Cadence Dynamic Power Estimation Flow

a design, including the software running on its processors, users are at risk of getting stuck in a local minimum. Deep cycles are needed to find the actual worst-case power consumption.

Using emulation in combination with power estimation from RTL or gate-level, it is possible to bridge abstraction levels today. With emulation solutions, like the Cadence Palladium Z1 Enterprise Emulation Platform, users can collect large amounts of activity data in a relatively short amount of time and connect them to implementation flows. Even though emulation allows execution in the MHz range when compared with simulation that runs in the Hz range, identifying the correct hotspots is best achieved by starting with more abstract, course-grain activity information, like raw toggle counts for the design, where each toggle counts as one to achieve early-stage estimation.

After refining the area of interest, weighted toggle counts can be used. They operate with weights on different nets, for instance, when treating a memory write-enable toggle as more significant for power consumption than a NAND gate input toggle. This achieves higher accuracy. The highest accuracy can ultimately be achieved using the SAIF toggle-count format at fine-grain accuracy. This format can then be consumed by power Figure 4: Checks to be performed during a power off/on scenario

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calculators like the Cadence Joules RTL Power Solution, which takes low-level technology data from .lib definitions into account.

Figure 3 shows the resulting design flow and an example of a power profile debug environment that includes toggle count and visualization of

a power shutoff. Design teams can shift the power optimization steps to a much earlier time in the design cycle using either: (1) A combination of activity data derived from the RT-level with estimates of power consumption from RTl using technology information in .lib files, or (2) Using activity information derived from the gate-level with


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POWER DESIGN


annotated power information to which .lib files can be annotated directly. This saves expensive redesign cycles as opposed to discovering power issues that need to be corrected at a later stage of the project. It also allows designers to optimize power with software running on processors that are part of the design and can heavily impact the dynamic power consumption.

Utilizing Standard Formats Like IEEE 1801IEEE 1801/UPF is an IEEE standard that specifies power intent using either a separate file via TCL-style commands or power intent written directly in the hardware description via language attributes and HDL packages. The standard defines the different power domains in a design and various tools, such as simulation and emulation, can consume IEEE 1801 compliant code to help users represent the power intent. When considering a design with four power domains—three of which are switchable and one that is switchable but also has high- and low-voltage states—users will have to test nine basic states and 24 modes of operation.

This testing can be done in simulation and emulation. Although some of these modes of operation may not be consequential, when paired with hundreds or even thousands of

functional tests, one can begin to understand the impact of overlaying low power on the verification problem. It becomes very desirable to enlist the raw computational power of emulation, augmenting what can be done in simulation.

A typical functional test would be augmented to include the power control signals. For power shutoff verification, for instance, the cycles for asserting isolation begin the sequence, followed by state retention, and then finally a power shutdown of the domain must be asserted to verify operation. Figure 4 calls out a number of checks that ought to be performed.

When evaluating emulation support for IEEE 1801, users should check for specific capabilities that have specific implications to them. For instance, memory randomization during shutdown and power-up, control over the read value during the power-off state, non-volatile memory state retention, and the freezing of data on retention are important when it comes to making the low-power verification repeatable. Users should be aware that in emulation—such as when using the Palladium Z1 platform—a 10%-20% capacity overhead associated with IEEE 1801-driven low-power verification exists due to the automatic insertion of logic to handle power domain management. The emulation

workflow for IEEE 1801 power verification in the Palladium Z1 platform requires a change to existing user code to include that IEEE 1801 power intent file during the compilation stage, and the rest of the flow is fully automated.

User Experiences For dynamic power analysis, one recent example was shared at CDNLive in Silicon Valley in a presentation by Theodore Wilson, technical lead for Architecture Co-Verification at Microsemi, called, “Rapid Turns with Palladium and Joules”. The key metric Microsemi was trying to optimize was “power analysis is throughput—the time from activity trace to actionable power reports.” By combining the Palladium Z1 platform with Joules power estimates, Microsemi was able to do gate-level runs as soon as RTL was functional… all of it early, accurate and precise. Other customers, such as Texas Instruments, previously reported results of the emulation to implementation flow to be within 96 percent of their expected power consumption. By doing longer runs in emulation when compared to simulation, they were able to detect unexpected power conditions as the design was run on emulation with actual software for real use-case scenarios.

www.cadence.comMore information on Microsemi case study http://bit.ly/2J0Cspy

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Automotive Infotainment System Designs Get Easier

By: Steve Knoth, Analog Devices, Inc.

Multi-Output Power Management ICs now have the power and levels of integration to handle modern automotive systems

As product form factors are decreasing, demand for their functionality and

features continue to increase. Furthermore, the industry trend for sophisticated digital ICs such as microprocessors (uP) and microcontrollers (uC) or field programmable gate arrays (FPGAs) that power these products continues to lower their operating voltage while simultaneously increasing their amperage. Microprocessors are among the most popular of these to design in, and there is a growing list of power efficient types. They are designed to provide low power consumption and high performance processing for a wide range of wireless, embedded and networking applications.

The original intent of these processors was to enable OEMs to develop smaller and more cost-effective portable handheld devices with long battery life, while simultaneously offering enhanced computing performance to run feature-rich multimedia applications.

Nevertheless, demand for this same combination of high power efficiency and processing performance has spread to non-portable applications. A couple of examples include automotive infotainment systems and other embedded applications, both of which demand similar levels of power efficiency and processing horsepower. In all cases, a highly specialized, high performance power management IC (PMIC) is necessary to properly control and monitor the microprocessor’s power so that all of the performance benefits of these processors can be attained. Further, as the electronic content of automobiles continues to dramatically increase, so too has the use of microprocessors as the work horse of various control systems within the vehicle.

Automotive PMIC ChallengesElectronic systems designed for automotive applications are challenging for many reasons, including the wide operating temperature range, strict EMC and transient requirements, as well as the high quality levels demanded by automotive

OEMs. Starting with the wide operating temperature range, power management ICs are challenged on two fronts. First, power conversion - even when highly efficient - must dissipate some level of power as heat. When several DC-DCs and LDO regulators are packed into a single device, the combined power dissipation can be significant, easily approaching two Watts or more. Typical PMIC packages such as the 6mm x 6mm 40 pin, exposed pad QFN have a thermal resistance of 33°C/W resulting in a junction temperature rise in excess of 60°C. When this is combined with the additional challenge of a wide ambient operating temperature range, the maximum junction temperature of the PMIC can often exceed 125°C. Even in body electronics, not under the hood, the ambient temperature inside a sealed plastic electronic control module can reach 95°C. Due to these temperature challenges many PMICs rated for 85°C, or even 125°C, are not sufficient for sustained high temperature operation.

Another key to operating an integrated power management device in a high ambient temperature environment is for the device to self-monitor its own die temperature and report when its junction temperature is getting too high so that the system controller can make an intelligent decision on whether to reduce power to the load(s). Operating system software can do this by turning off less critical functions or by turning down the performance in processors and other high power functions such as displays and network communications.

The environment within a current vehicle’s dashboard is crowded with electronics. Adding to this crowding are radios from Bluetooth to cell phone based network connectivity. Therefore, it is imperative that any additional entries to this thermally constrained environment not contribute excessive heat or EMI. There are strict Electromagnetic Compatibility (EMC) requirements which cover radiated and conducted emissions, radiated and conducted immunity or susceptibility, and Electrostatic Discharge (ESD). Being able to conform to these requirements affects the performance aspects of a PMIC design. Some are straightforward, such as the DC-DC switching regulators must operate at a fixed frequency well outside of the AM radio band. However, another common radiated emission source found in

DC-DC converters comes from the switching edge rates of its internal power MOSFETs. These edge rates should be controlled to reduce radiated emissions.

Many of today’s embedded systems and advanced processors require controlled and choreographed sequencing as power supplies are powered up and applied to various circuits. Allowing for system flexibility and a simple approach to sequencing not only makes the system design easier, but it also enhances system reliability and allows for a single PMIC to handle a broader range of the system than just a specific processor’s requirements.

A Simple SolutionHistorically, many PMICs have not possessed the necessary power to handle these modern systems and microprocessors. Any solution to satisfy the automotive power management IC design constraints as already outlined must combine a high level of integration, includ-ing high-current switching regula-tors and LDOs, wide temperature range of operation, power se-quencing and dynamic I2C control of key parameters with hard-to-do functional blocks. Furthermore, a device with high switching fre-quency reduces the size of external components and ceramic capaci-tors reduce output ripple. This low ripple combines with accurate, fast response regulators to satisfy

Figure 1: LTC3676-1 Simplified Typical Application Diagram

28



demanding voltage tolerances of 45nm type processors. Such power ICs must also be capable of meeting the rigorous automotive

environment including radiated emission suppression, although the input voltage is typically a pre-regulated 5V or 3.3V rail off the

system or battery voltage.

A High Power, Power Management SolutionThe LTC3676/-1 are complete power management solutions for Freescale i.MX6 processors, ARM-based processors and other advanced portable microprocessor systems. The LTC3676/-1 contain four synchronous step-down DC/DC converters at up to 2.5A each for core, memory, I/O and system on-chip (SoC) rails plus three 300mA linear regulators for low noise analog supplies. The LTC3676-1 configures a 1.5A buck regulator for source/sink and tracking operation to support DDR memory termination and also adds a VTTR reference output for DDR. These two pin features replace the LDO4 enable pin and feedback pins of the LTC3676. LDO4 is still programmable by I2C. Supporting the multiple regulators is a highly configurable power sequencing capability, dynamic output voltage scaling, a pushbutton interface controller, plus regulator control via an I2C interface with extensive status and fault reporting via an interrupt output. The LTC3676 supports i.MX6, PXA and OMAP processors with eight independent rails at appropriate power levels with dynamic control and sequencing. Other features include interface signals such as the VSTB pin that toggles between programmed run and standby output voltages on up to four rails simultaneously. The device is available in a low profile 40-pin 6mm x 6mm x 0.75mm

exposed pad QFN package.

The LTC3676 Power Management Solution for Application Processors can solve the automotive infotainment system design challenges outlined above. The LTC3676HUJ PMIC is available in a high temperature (H-Grade) option with a junction temperature rating from -40°C to +150°C, easily satisfying the high temperature automotive operating requirement. The IC includes a thermal warning flag and interrupt specifically for junction temperature monitoring and also includes a hard thermal shutdown for reliable protection of the hardware, should power dis-sipation be mismanaged, or in the event of a severe fault condition.

The LTC3676 PWM switching fre-

Figure 2: The LTC3676 Startup Sequence

Figure 3. The LTC3676 Power-Down Sequence

quency is specifically trimmed to 2.25MHz with a guaranteed range of 1.7MHz to 2.7MHz. Its internal regulators can also be set to a forced continuous PWM operating mode to prevent operation in pulse skip or burst-mode even at light loads. This not only keeps the frequency fixed but also further reduces voltage ripple on the DC-DC output capacitors.

Suppressing Radiated & Conducted EmissionsSince there are 4 switching regulators onboard the LTC3676, each has an associated reactive device (inductor) to be concerned about. One possible solution is to shield the LTC3676 area to prevent EMI from being emitted. Besides being expensive and heavy, this does not solve the problem of

contamination by any wires that might be connected to the power supply area. It is better to use source suppression and antenna elimination.

Source suppression necessitates good layout/component selection (and internal IC design) to prevent the generation of radio frequency energy. It is often necessary to use shielded inductors and to place those inductors further away from the LTC3676 than the output capacitors. This is because the AC currents circulate from the LTC3676 through the inductor, through the output capacitor, to ground and back to the LTC3676. It is clear that wide traces, preferably area fill, should be used to connect the ground of the output capacitors to the ground

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of the LTC3676 and to the ground of the PVIN input decoupling capacitors also.The LTC3676 also provides some tools for source suppression. Its DC-DC converters specifically include a dv/dt control feature which slows down the switching edge rates to reduce radiated emissions. Since the buck regulators are synchronous, both the rise and the fall time are both controlled. A slow edge rate of about 3ns rise/fall, was selected to both pass emission requirements and still limit switching losses, which helps to optimize power converter efficiency. Each of the 4 buck switching regulators in the LTC3676 default to this 3ns edge rate control mode, but can also be individually set via I2C, to a faster 1ns rate, to improve efficiency, if limited edge rate and emissions control is not required.

In addition to switching time control, the LTC3676 offers some other EMI suppression tools. The frequency of the buck regulators can be changed from 2.25MHz to 1.12MHz. Also, to minimize the input ripple, which can end up radiating through the power input wiring, the buck regulators can be staggered between two different clock phases.

The LTC3676 is also capable of providing considerable power, in excess of 10W. This can result in substantial circulating currents and so it is imperative to provide an uninterrupted path for this current to circulate. In particular,

slots in the ground plane, which force the large circulating currents to flow around them, create slot antennas. But other obstacles, such as changing layers, contribute some energy in the EMI signature and should be minimized. Ideally the top and bottom layers should be all, or mostly, ground plane, with the signal layers flowing internally. Since this is usually not practical, some thought needs to go into how the ground plane will be connected prior to commencing layout. For example, it is not a good idea to put the LTC3676 into a corner or tab on the PCB. This will make it very difficult to properly route the ground plane. However, it is a good idea to route the high circulating current areas of the LTC3676 first, to ensure the most optimum layout possible.

If EMI control is planned and executed with the concepts of source suppression and antenna elimination in mind, it is possible to create a full power system that is a good EMI neighbor without increasing product cost or weight.

More Key Features The LTC3676 fully satisfies the automotive ESD requirements of 2kV HBM and 1000V CDM which is another key requirement for approaching zero defects in the automotive assembly process. Further, the IC has very low standby current consumption, typically 12uA, which is desired in “always on” automotive navigation, security and safety systems which must maintain continuous power

to real time clock circuits for temporal awareness, even when the engine is not running.

Finally, the LTC3676 supports simple and effective power sequencing which can be handled through serial communications or via pin strapping where power supply output voltages are tied to enable pins in the desired turn-on sequence. Internally each enable is delayed micro seconds to further time stagger the startup sequence. This feature is supported with precision low voltage enable thresholds so the sequencing is possible even with output voltages as low as 0.43V. Each supply voltage output is also soft-started to limit inrush current and produce clean voltage transitions. See Figure 2.

The LTC3676 also includes easily programmable power-down sequence control. The IC includes two registers for initializing a power down sequence configuration which will be followed at the next turn-off event or overpower fault condition. Each regulator (DC-DC and LDO) can be pre-set to any one of four time slots for shutdown. Each regulator output includes an internal pull-down resistor that is engaged when disabled to guarantee the controlled discharges as shown in Figure 3 and a low starting point for the next turn-on sequence.

Analog Deviceswww.analog.com

Transient Protection Solutions in Automobiles

By: Ron Demcko, Fellow, AVX Corporation

ESD-Safe MLCCs, Slow Transient Wave-Rated MLCCs, and Multilayer Varistors

Thanks to modern technology, passenger

vehicles are now safer, more enjoyable, and more efficient than ever. Today’s automobiles utilize incredible amounts of computing power to improve the overall driving experience in several different ways. For example, arrays of sensors and dedicated processing units now monitor and make use of vast amount of data from systems spanning cabin entertainment electronics to critical underhood modules. Multiple central processing units now employ high-speed networks to transmit data to even larger and more powerful processors that profile, prioritize, and control numerous sub systems. In addition, automobiles now utilize RF links to communicate with both one another and surrounding infrastructure.

The complexity of automotive ICs and the often critical

nature of their high-reliability performance helps support the argument that these increasingly prolific devices are now more susceptible than ever to transient voltages. Automotive design engineers generally use shielding and routing methods to redirect transients, transient voltage suppressors to clamp the effects of incoming transients, or integration capacitors to capture transient voltages and slowly release their energy back into the circuit at levels below the susceptibility limit. However, due to the varying nature of these device’s cost, size, and performance limitations, there is no “one size fits all” solution

for each and every automotive application.

This article examines two automotive transient voltage control options, transient voltage suppression clamps (i.e., multilayer varistors) and integration capacitors, and compares and contrasts multilayer varistors, ESD-Safe™ MLCCs, and slow-pulse capable multilayer ceramic capacitors.

Performance ConsiderationsThe ideal method of transient voltage suppression is to clamp the transient voltage with a transient voltage suppressor (TVS). Of all the

Figure 1: MLV (left) vs. TVS diode (right) temperature derating



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combination of qualities is fairly common. In most engine control units (ECUs), there is typically an 80/20 need for ESD integration capacitors versus MLVs on the pins. For example, a 300-pin ECU would have a 240:60 ratio of integration capacitors to MLVs.

ESD Models ESD is a sub-nanosecond rise-time event that is generated by the charge transfer of materials in the tribo-electric material series. ESD can be either positive or negative in polarity, contact- or air-discharge, and repetitive or random in nature.

An ESD event is typically modeled by a capacitor charged to a particular voltage level in series with a current-limiting resistor, both of which are discharged at particular repetition rates to simulate a certain number of real-world transients on the device under test (DUT). There are several models that can be used to simulate the various transient sources that could inject ESD

into a victim, but the three most common are the charged device model (CDM), the machine model (MM), and the human-body model (HBM).

ESD-Safe™ MLCCs are generally intended for use in IEC 61000-4-2 applications subjected to HBM strikes (150pF, 330Ω), but not exclusively in contact discharge mode (Figure 3). Although there are many common transients that are slow in speed, ESD-Safe MLCCs are primarily intended for use in fast transients hardening.

Transient Voltage Control via Multilayer Varistor (MLV) Clamping Multilayer varistors are zinc oxide (ZnO2) ceramic semiconductors that exhibit nonlinear voltage-current (VI) characteristics in the presence of an electric bias. The number of grains between the multilayer conducting electrodes determines the breakdown voltage, which is defined as the

1mA current conduction point on the VI curve. Clamping voltage is defined as the maximum voltage measured with an 8x20µs waveform applied at a specific current magnitude defined by the energy rating of the part. Another parameter of MLVs is operating voltage, which is the steady-state voltage that can be indefinitely applied to the MLV without causing an increase in the specified leakage current of the part.

Figure 4 shows the VI curve for

Figure 3: The human-body model (HBM) is one of the three most common models that can be used to simulate transient sources that could inject ESD into a victim

Figure 4: MLV voltage-current (VI) curves

TVS devices available on the market, multilayer varistors (MLVs) are one of the best choices due to the fact that they are small, lightweight, and capable of both clamping voltages in their on-state and acting as an electromagnetic interference (EMI) filter in their off-state. Additionally, MLVs do not have the same severe power derating limitations as TVS diodes do (Figure 1). This feature is increasingly important in automotive LED drivers and engine electronics, as these applications are frequently subjected to operating temperatures approaching or even exceeding 125°C.

In some cases, ICs have a level of on-chip protection or are located deeply within the inner portion of a PCB or module. In these instances, an integration capacitor can often be used to attenuate the front-end, rise-time effects of the transient. This type of protection, electrostatic discharge (ESD) integration,

is best suited for non-critical automotive applications. In instances where communication bus structures need transient control, MLVs are a more effective transient voltage solution, as the magnitude of capacitance needed within an integration capacitor would cause signal data skew.

Modern vehicles have several dozen CAN interfaces that require transient voltage control. Figure 2 illustrates a typical CAN circuit both before and after the implementation of CAN MLVs. In this example, an MLV is connected from both the CANH and CANL lines to the ground and is used to provide EMI filtering in the varistor’s off-state and to provide bidirectional protection for the IC when ESD or other transients are present, making it an effective replacement for both the EMC capacitor and the bidirectional diodes used in the circuit with a single MLV. MLVs are also well suited for use in automotive

CAN circuits due to the fact that several series can operate at 150°C without the need for derating. So, as CAN interfaces and other communication buses continue to expand their roles to underhood applications, the case for the use of MLVs will only become stronger.

In circuits that utilize ICs with on-chip protection or ICs integrated within a PCB or module, or in applications where automotive circuits employ lower cost, slower, and less complicated ICs, the ICs will exhibit at least a moderate degree of inherent ESD survivability. So, ESD integration capacitors can provide effective transient voltage protection in these types of circuits. However, it is important to understand that these solutions are only effective in the case of short-waveform incidents upon fairly rugged ICs in non-critical applications that can withstand large amounts of capacitive loading. Luckily, though, that

Figure 2: A typical CAN circuit with two MLCCs and two diodes (left) and a typical CAN circuit with either two MLVs or one two-element MLV array (right)

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the model is charged, Cicap is the capacitance value of the integration capacitor, and Vic is the voltage that the IC (or device to be protected) experiences.

The original charge of the ESD model is split between the ESD model's capacitance and the ESD integration capacitor. For example, if the capacitor in the ESD model is rated for 150pF

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