1

A Cost-Efficient High-Speed 12-bit Pipeline ADC in 0.18-m Di

gital CMOSTerje Nortvedt Andersen, Bjørnar Hernes, Member, IEEE, Atle Briskemyr, Frode Telstø,

Johnny Bjørnsen, Member, IEEE, Thomas E. Bonnerud, and Øystein Moldsvor

　　指導教授 :林志明　教授　學生：劉彥均

2

OUtline Introduction Pipeline Architecture Stage Architecture SC Current Bias Generator Mesurement Results Conclusion References

3

Introduction lower dynamic power consump

tion, and smaller area, system on chip(SoC)

12-bit pipeline ADC, 1.8V, 0.18- m pure digital CMOS technology.

4

Pipeline Architecture

Pipeline architecture.

5

Stage Architecture

Pipeline stage

6

Stage Architecture

1SBulk-switching of the pMOS device in the transmission gates and 2S

7

Stage Architecture When 1.5-bit stages are used, the s

tage output voltage is given by:

8

Stage Architecture

Principal scheme of ADSC and decoder and switching block (DS

B).

9

Stage Architecture

Stage opamp. The values of bias currents and compensations capacitors are given for the first stage in the pipeline chain.

10

SC Current Bias Generator

Modeling a resistance using (a) the SC circuit, and (b) the SC bias current generator.

11

SC Current Bias Generator The value of the equivalent resistor i

s given by:

The value of the bias currents are given by

12

Mesurement Results

Power dissipation versus conversion rate. The input frequency and

signal swing is 10 MHz and 2V , respectively.

13

Mesurement Results

14

Mesurement Results

Die photograp

h.

15

ConclusionLow area and low and scalable

power dissipation results

16

References[1] B. Hernes, A. Briskemyr, T. N. Andersen, F. Telstø, T. E. Bonnerud, and Ø. Mold

svor, “A 1.2 V 220 MS/s 10 b pipeline ADC implemented in 0.13 m digital CMOS,” in IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, 2004, pp. 256–257.

[2] T. B. Cho and P. R. Gray, “A 10 b, 20 Msample/s, 35 mW pipeline A/D converter,” IEEE J. Solid-State Circuits, vol. 30, no. 3, pp. 166–172, Mar.1995.

[3] W. C. Song, H.-W. Choi, S. U. Kwak, and B. S. Song, “A 10-b 20-Msample/s low-power CMOS ADC,” IEEE J. Solid-State Circuits,vol. 30, no. 5, pp. 514–521, May 1995

[4]M. Gustavsson, J. J.Wikner, and N. N. Tan, CMOS Data Converters for Communications. Boston, MA: Kluwer , 2000.

[5] K. R. Laker and W. Sansen, Design of Analog Integrated Circuits and Systems. New York: McGraw-Hill, 1994.

[6] D. Kelly, W. Yang, I. Mehr, M. Sayuk, and L. Singer, “A 3 V 340 mW 14 b 75MSPS CMOS ADC with 85 dB SFDR at Nyquist,” in IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, 2001, p. 134.