1 comp541 datapaths i montek singh mar 8, 2007. 2topics over next 2/3 classes: datapaths basic...
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3 Parts of CPUs Datapath The registers and logic to perform operations on them The registers and logic to perform operations on them Control unit Generates signals to control datapath Generates signals to control datapathTRANSCRIPT
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COMP541COMP541
Datapaths IDatapaths I
Montek SinghMontek Singh
Mar 8, 2007Mar 8, 2007
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TopicsTopics Over next 2/3 classes: datapathsOver next 2/3 classes: datapaths Basic register operationsBasic register operations
Book sections 7-2 to 7-6 and 7-8Book sections 7-2 to 7-6 and 7-8 Computer datapathsComputer datapaths
First part of Chapter 10First part of Chapter 10
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Parts of CPUsParts of CPUs DatapathDatapath
The registers and logic to perform operations on themThe registers and logic to perform operations on them Control unitControl unit
Generates signals to control datapathGenerates signals to control datapath
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Memory and I/OMemory and I/O Are connected to the data/control in and out Are connected to the data/control in and out
lineslines Example: register to memory opsExample: register to memory ops
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MicrooperationsMicrooperations Basic operations of the datapathBasic operations of the datapath
Example: moving data from one register to anotherExample: moving data from one register to another Not necessarily microprogrammed controlNot necessarily microprogrammed control
Just a description of operationsJust a description of operations Microoperation expected to complete in one Microoperation expected to complete in one
clockclock Register transfer notation, nextRegister transfer notation, next
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Register Transfer Language (RTL)Register Transfer Language (RTL) Registers named in uppercaseRegisters named in uppercase
PC, IR (instruction), R3PC, IR (instruction), R3 Little endianLittle endian
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RTRT Transfer from R1 to R2Transfer from R1 to R2
R2 R2 R1R1 R2 is destinationR2 is destination R1 is sourceR1 is source
ConditionalConditional If(K1 = 1) then (R2 If(K1 = 1) then (R2 R1)R1) K1: R2 K1: R2 R1 as a shorter formR1 as a shorter form
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TransferTransfer Transfer at the clock edgeTransfer at the clock edge When K1 is highWhen K1 is high n bits widen bits wide
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SymbolsSymbols Note memory transfersNote memory transfers
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Syntax not Verilog (but similar)Syntax not Verilog (but similar)
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Types of MicrooperationsTypes of Microoperations Transfer – have just looked atTransfer – have just looked at ArithmeticArithmetic LogicLogic ShiftShift
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ArithmeticArithmetic Basic ops (not multiply, divide)Basic ops (not multiply, divide)
R0 R0 R1 + R2R1 + R2 Subtraction by 2’s complementSubtraction by 2’s complement
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Notation is Shorthand for Notation is Shorthand for HardwareHardware ConsiderConsider and and
Note overflowNote overflowand carry registersand carry registers
211:1 RRRKX 1211:1 RRRXK
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Logic MicrooperationsLogic Microoperations
OR notation a little confusingOR notation a little confusing
shows two types of syntax for ORsshows two types of syntax for ORs211:)21( RRRKK
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Shift MicrooperationsShift Microoperations Here just the basic one-bit shiftsHere just the basic one-bit shifts
Bit falls off the end, zero shifted inBit falls off the end, zero shifted in
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Multiplexer-Based TransfersMultiplexer-Based Transfers ConsiderConsider
Which can also be expressed asWhich can also be expressed as
Block diagram nextBlock diagram next
20)12()10()11( RRthenKifelseRRthenKif
20:21,10:1 RRKKRRK
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Multiplexer Block DiagramMultiplexer Block Diagram
Detailed block diagram nextDetailed block diagram next
20:21,10:1 RRKKRRK
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DetailedDetailed
Simpler version is Simpler version is easier to follow easier to follow and to deriveand to derive
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Bus-Based TransfersBus-Based Transfers How about when there are lots of registers?How about when there are lots of registers?
Beyond a certain point muxes become unwieldyBeyond a certain point muxes become unwieldy Can use buses and send data over common Can use buses and send data over common
set of wiresset of wires
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Simple CasesSimple Cases
One muxOne mux One output One output
bus bus
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TransfersTransfers Can’t be as generalCan’t be as general Only single sourceOnly single source About ½ the hardwareAbout ½ the hardware
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Three-State BusThree-State Bus Remember three-state drivers Remember three-state drivers
allow having multiple outputs allow having multiple outputs share wireshare wire
Have to control so only one is Have to control so only one is assertedasserted
Example nextExample next
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Same Example with 3-StateSame Example with 3-State One R outputOne R output
Enable controlsEnable controls Load controls which Load controls which
latcheslatches Fewer wiresFewer wires Especially important Especially important
outside chipoutside chip
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Memory TransfersMemory Transfers Usually one or more buses associated with Usually one or more buses associated with
memorymemory AddressAddress DataData
Note that memory can be slower, so may have Note that memory can be slower, so may have to use complex timingto use complex timing Address on one clock cycleAddress on one clock cycle Data latched at later clock cycleData latched at later clock cycle
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DatapathDatapath Blue signals Blue signals
generated by generated by controlcontrol
A&B buses to ALUA&B buses to ALU B can be constant B can be constant
from memoryfrom memory Can also send addr Can also send addr
and dataand data
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R1R1R2+R3R2+R3 SignalsSignals
Load enableLoad enable A, B selectA, B select MB SelectMB Select MF SelectMF Select G SelectG Select Destination (D)Destination (D)
What about What about timing?timing?
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TimingTiming All can occur in one clock, butAll can occur in one clock, but Signals must be available in time to propagate Signals must be available in time to propagate
through muxes, ALU and through muxes, ALU and Be at R inputs by next posedgeBe at R inputs by next posedge
Go back and look at pathGo back and look at path
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NextNext Look at specific MIPS designLook at specific MIPS design
Next timeNext time Continue design review of ALUContinue design review of ALU Look at shifterLook at shifter