1-jpe09133

7/28/2019 1-JPE09133

1/8

Analysis and Design of a High Voltage Flyback Converter with Resonant Elements 107

JPE 10-2-1

Analysis and Design of a High Voltage Flyback Converter with Resonant ElementsSung-Soo Hong , Sang-Keun Ji , Young-Jin Jung , and Chung-Wook Roh

Dept. of Electrical Engineering, Kookmin University, Seoul, Korea

Abstract

This paper presents the operational characteristics of a high voltage yback converter with resonant elements. In high voltagelow power applications, the effect of a transformers stray capacitance might be the most important factor that inuences theoverall performance of the circuit. A detailed mode analysis and the design procedure are presented in designing the high voltageyback converter. To verify and conrm the validities of the presented analysis and design procedure, a computer simulation andexperiments have been performed.

Key Words: Flyback converter, High voltage power supply, Resonant elements, Stray capacitance

I. INTRODUCTION

Flyback converters have been widely used because of theirrelative simplicity and their excellent performance for mult-output applications. They can save cost and volume comparedwith the other converters, especially in low power applications.

In a yback converter, a transformer is adopted to achievegalvanic isolation and energy storage. Research is mainlyfocused on the leakage inductance of the transformer [1][3],

since voltage spikes caused by the series resonance betweenthe transformer leakage inductance and the parasitic capac-itance of the switch are the dominant factors in determiningthe power conversion efciency and the switching noise in lowoutput voltage and high output current applications.

On the other hand, in high output voltage and low outputcurrent applications such as the high output voltage powersupply (HVPS) in printers, the horizontal deection circuit incathode-ray tubes (CRT) displays, etc., the aforementioned res-onance is not the main factor which degrades the performanceof a yback converter. Instead, the parallel resonance betweenthe transformers magnetizing inductance and the parasiticcapacitance of the transformer are the dominant factors, sincethe large number of turns of the secondary windings generatea large parasitic capacitance.

The duty cycle loss due to this resonance is a severeproblem in such high output voltage applications. Beside theproblem of low power conversion efciency, the expectedoutput voltage in the kilo voltage range cannot be obtained inthe rst prototype based on the conventional design method.A redesign of the transformer based on the trial and errorprocess is inevitable in this case. This results in a lengthy

Manuscript received Nov. 4, 2009; revised Jan. 6, 2010 Corresponding Author: [email protected]

Tel: +82-2-910-4947, Fax: +82-2-910-4449, Kookmin UniversityDept. of Electrical Engineering, Kookmin University, Korea

process for developing a high output voltage yback converter[4][6]. Therefore, it is very important for the optimum designof a high voltage yback converter to take into considerationthe resonance between the magnetizing inductance and theparasitic capacitance of the high voltage transformer whichhas large secondary winding turns [7], [8]. In this paper,the operational characteristics and an analysis considering theresonance effect is provided in details. A design example of ahigh voltage yback converter with resonant elements is alsopresented. Finally, an experimental prototype circuit with anoutput of 1200V is provided to demonstrate the performancecharacteristics and design procedure of a high voltage yback converter with resonant elements.

I I . T HE O PERATIONAL C HARACTERISTICS

A. Circuit Conguration

Fig. 1 shows the yback converter with a high voltageyback transformer, having high turns ratio between theprimary and secondary windings considered in this paper.This yback converter with resonant elements is composedof resonant tank networks including the parasitic capacitorof the switch ( C p ), the transformer magnetizing inductance(Lm ), the parasitic capacitor of the diode ( C s ) and the windingcapacitance ( C ws ). Since the capacitance on the secondary sideis reected to the primary side with the value of n2 times,where n is the turn ratio of the transformer and the windingcapacitance ( C ws ) is sufciently large compared with thatof a conventional transformer. Thus, the resonance betweenthe parasitic capacitance C ws and the magnetizing inductancewhich arise during the turn-on and turn-off transitions of thesemiconductor elements is the dominant factor which affectthe duty cycle loss [9].

This circuit can be transformed to an equivalent circuit on

the primary side, as shown in Fig. 2. A process to determine

7/28/2019 1-JPE09133

2/8

108 Journal of Power Electronics, Vol. 10, No. 2, March 2010

Fig. 1. Flyback Converter with Resonant Elements.

(a) Short circuit cell (b) ZVS quasi-resonantnetwork

(c) Equivalent circuit

Fig. 2. Equivalent Circuit of high voltage Flyback Converter withResonant Elements.

the topology of a resonant switch network is to replace allthe low-frequency lter inductors with open circuits, and toreplace all the dc sources and low-frequency lter capacitorswith short circuits [10]. The elements of the resonant switchcell remain in Fig. 2(a). The parasitic capacitance of the diode(C s ) and the winding capacitance ( C ws ) on the secondary sideare reected to the primary side with the value of n2 times. Inthe case of the zero-voltage-switching (ZVS) quasi-resonantswitch, the network of Fig. 2(b) is always obtained, where theparasitic capacitances referred to the primary side are givenas follows:

C r = C p // C wsn2 // C s

n2 .(1)

So this simplied yback equivalent circuit which consistsof magnetizing inductance ( Lm ) and stray capacitance ( C r ) isshown in Fig. 2(c).

B. Operational Principles

For the convenience of the mode analysis in the steady state,several assumptions are made as follows:

The semiconductor devices are ideal, i.e., there is noforward voltage drop in the on-state, no leakage currentin the off-state, and no time delay at both turn-on and

turn-off.

(a) Mode 1 [ t 0 t 1 ] (b) Mode 2 [ t 1 t 2 ]

(c) Mode 3 [ t 2 t 3 ] (d) Mode 4 [ t 3 t 4 ]

Fig. 3. Four operating modes of high voltage yback converter withresonant elements.

The converter is operated in the boundary conductionmode (BCM) [11], [12].

The output capacitors C o is sufciently large. Thereforethe output voltage can be assumed to be a constant DCvoltage during the switching period T s .

The following variables are dened as follows: Characteristic impedance Z o = Lm /C r . Resonant frequency f o = 1 / 2 Lm C r . Characteristic impedance ratio Q p = n2RL /Z o . Normalized switching frequency ratio f ns = f s /f o ,

where fs is the switching frequency of the converter.The steady-state voltage and current waveforms for each

operating mode of the circuit shown in Fig. 2(c) are illustratedin Fig. 3. There are four stages during one switching period.The corresponding key waveforms are given in Fig. 4. Everycycle of the converters operation can be divided into thefollowing intervals, depicted in Fig. 4: ( t0 , t1 ), the resonanceof Lm and C r ; (t1 , t2 ), the linear discharging of Lm ; (t2 , t3 ),the resonance of Lm and C r ; (t3 , t4 ), the conduction of Q.

Mode 1 [t0 t1 ]: Resonant IntervalPrior to t0 , the switch Q is conducting and V g is applied

to the primary winding. When Q is turned off at t=t0 , theformer operational mode, where the magnetizing current iLmis linearly ramped up, ends. Because of the resonance betweenLm and C r , the magnetizing energy in Lm is not immediatelytransferred to the secondary side. The energy transfer to the

secondary side is delayed until the parasitic capacitor C r ischarged to V Cr (t)=nV o V dc . V dc increases from 0 to V g +nV o . In mode 1, the current and voltage can be represented asfollows:

vCr (t) = V g cos 0t i(0)Z 0 sin 0t (2)iLm (t) =

V gZ 0

sin 0t + i(0)cos 0t (3)

where o = 1 / Lm C r , Z o = o Lm .This mode ends when V Cr (t) = nV o at t=t1 . At t=t1 , thediode D on the secondary side is turned on. From equation

(2), the stray capacitance voltage V Cr (t1) can be obtained as:

nV o = V g cos 1 i(0)Z o sin 1 (4)

7/28/2019 1-JPE09133

3/8


Fig. 4. Key waveforms of high voltage yback converter with resonantelements.

where n = 0(tn tn 1). Hence, 1 = 0(t1 t0).The switch conversion ratio M reected to the primary sideis given by nV o /V g and can be represented as follows:

M + cos 1 i(0)Z o

V gsin 1 = 0 . (5)

Mode 2 [t1 t2]: Discharging IntervalWhen V Cr (t) reaches nV o at time t=t1 , the diode in thesecondary side is turned on and the magnetizing current in Lm

ows to the secondary side. The magnetizing inductor currentiLm , owing through the path Lm d C o , is expressed as:

iLm (t) = nV OLm

(t t1) + i(t1). (6)It is noted that V Cr remains at nV o . The voltage across theprimary switch is given during this mode by V dc = V g + nV o

which is the same as that of an ideal yback converter. Theenergy stored in the primary inductance of the transformer istransferred to the load. At t=t2 , the stored energy is completelytransferred, and i(t2) becomes zero.

This state can be approximately described by the following

equation:

nV OLm

(t t1) + i(t1) = 0 2 =Z 0 i(t1)

nV O. (7)

Substituting (7) into (3) leads to

2M = sin 1 +i(0)Z o

V gcos 1 . (8)

Mode 3 [t2 t3]: Resonant IntervalAfter the energy stored in Lm is completely transferred

to the output capacitor and the load on the secondary side,resonant occurs between C r and Lm . When the current in

Lm is zero, the diode on the secondary side is turned off.

However, the drain-source voltage of the switch V dc doesnot immediately go to zero but a quasi resonant occurs. Theresonant action of Lm and C r causes V dc to decrease to zeroat t3 . Therefore the body diode of switch Q is turned on andit ensures the zero voltage switching (ZVS) operation. Theinductor current iLm , owing through the path Lm d C o ,is negative. The resonant voltage V Cr and the resonant currentiLr on the primary side can be expressed as:

vCr (t) = nV O cos o t (9)iLm (t) =

nV oZ o

sin o t. (10)

This stage ends when V Cr (t) reaches V g at t=t3 and thefollowing equations can be obtained from equation (9):

cos 3 = 1

M . (11)

From the equation (11), it can be seen that the switch

conversion ratio M should be at least larger than 1. The switchQ can operate with ZVS for M > 1.

Mode 4 [t3 t4 ]: Charging IntervalIn this mode the switch Q is turned on and V dc =0. Before

the polarity of the current iLm changes, the main switch shouldbe turned on to ensure ZVS operation. The input energyis stored in the magnetizing inductance Lm , via the pathV gLm Q. The voltage V Cr (t) remains V g . The primary sidecurrent iLm increases linearly, and is expressed as:

iLm (t) =V gL

m

(t

t3) + i(t3). (12)

This mode ends when the switch Q is turned off. Sincei(t4) = i(0) , equation (12) can be written as:

i(0) =V gZ o

[4 M sin 3]. (13)

The output current I o can be found by averaging the outputdiode current id (t) over one switching period as:

I O =1

T S t 4

0id (t)dt =

2

ni(t1)2

(14)

where = o T S . Substitution of (14) into (7) leads to:

2 2 =2Q p

(15)

where Q p = n2V o

Z o I o . Combining (5) and (8) gives:

2 sin 1 = cos 1 +1

M . (16)

Substitution of (5) into (13) leads to:

cos 1 + M sin 1 = M sin 3 + 4 . (17)

7/28/2019 1-JPE09133

4/8


Based on (11), and (15) (17) the expressions can beobtained as:

3 = cos 1

1

M (18a)

2 = 2Q p (18b)1 = cos

1 1M + 2 2 + 1 1M 22 2 + 1 (18c) = 1 + 2 + 3 + 4 (18d)

4 =cos 1 + M

sin 1+ M sin 3 . (18e)

Expressions (18a)-(18e) will be used later to design the ZVShigh voltage yback converter with resonant elements.

C. Voltage Conversion Ratio

The magnetizing current iLm during the entire mode of operation is expressed as:

i(t1) = V gZ Osin 1 + i(0)cos 1 (19a)

i(t2) = 0 = nV OZ O

2 + i(t1) (19b)

i(t3) = nV OZ O

sin 3 (19c)

i(t4) = i(0) =V gZ O

4 + i(t3). (19d)

From (19b), the magnetizing current at t=t1 can be ex-pressed as:

i(t1) =nV OZ O

2 . (20)

Substitution of (20) into (19a) leads to:

i(0) =nV OZ O 2

V gZ O sin 1

cos 1. (21)

From (21), (19d) can be expressed as:

i(t3) =nV OZ O 2

V gZ O sin 1

cos 1 V gZ O

4 . (22)

The voltage conversion ratio can be calculated from thesubstitution of (22) into (19c) as follows:V O

V g=

1

n

4 cos 1 + sin 1

2 + cos 1 sin 3

=1n

(t4 t3)cos(t1 t0) Lm C r + Lm C r sin

(t1 t0) Lm C r(t2 t1) + Lm C r cos

(t1 t0) Lm C r sin(t3 t2) Lm C r

. (23)

It is noted that if the time intervals at mode 1 and mode 3 areshort, the voltage conversion ratio of equation (23) becomesas:

V oV g

=1n

(t4 t3)(t2 t1)

=1n

D1 D

(24)

where D is the duty cycle, D = t4 t3 and 1 D = t2 t1 .It is also noted that equation (24) is the same as the voltageconversion ratio of a conventional yback converter.

Fig. 5. Waveforms for the switch power loss as a function of Q p and f ns .

III. D ESIGN C ONSIDERATIONS

A. Switch Power Losses

The characteristic impedance ratio Q p and the normalizedswitching frequency ratio f ns are the most important pa-rameters for a high voltage yback converter with resonantelements because they determine the power loss. Since theload current is small in low power level high output voltageapplications, the power loss of the switch is the dominantfactor. For example, in a HVPS in a laser jet printer, whosepower level is about 1Watt with an output voltage of 1,500volt, the size and volume of the converter is determined mainlyby the switch due to its large sized heatsink element.

The energy dissipated by the switch during the resonantperiods, such as Mode 1 and Mode 3, is given by the current

though the parasitic capacitance of the switch C p multiplied bythe drain-source voltage V ds . During these resonant periods,the drain-source voltage of the switch V dc can be expressedas:

Mode1 : vds (t) = V g (1 cos ) + i(0)Z o sin Mode3 : vds (t) = V g + nV o cos . (25)The power loss of the switch during the resonant period

is dened as an integral of the drain-source voltage of theswitch multiplied by magnetizing inductance current and di-vided by the period T . In addition, because the magnetizinginductance current divides into the parasitic capacitance C pand the resonant capacitance C r , the impedance ratio shouldbe multiplied. The power loss of the switch, P sw loss , can beobtained as follows:

P s w l os s =

V g 2

Z 0( cos 1 +1)+ V g i (0) sin 1

+ 12 i (0)2 Z 0

V g 2

Z 0sin 2 1

V g i (0)2 sin

2 1

+ nV OZ 0 V g cos 3 V g

nV O2 sin

2 3

1

C pC r

. (26)

The characteristics of the switch power loss during theresonant period are depicted in Fig. 5. These characteristicsdescribes how, at a given f ns , the power loss magnitude varieswith the characteristic impedance ratio Q p . We can minimizethe power loss of the switch by optimal choices of Q p and f ns .The power loss decreases as Q p decreases and f ns increases.However, the switch conversion ratio M is less than 1 as Q p

7/28/2019 1-JPE09133

5/8


decreases and f ns increases. Therefore to obtain the minimumpower loss of the switch Q p , it is recommended to select alow value of f ns and a high value of M , which determinesthe turns ratio of the transformer.

B. Boundary Condition of the Resonant Capacitor

When designing a high voltage yback converter withresonant elements, there exist a minimum value of the resonantcapacitor C r . The parasitic capacitances of the switch anddiode are obtained from the available datasheet. There alsoexists a minimum winding capacitance on the large numberof turns of the secondary windings. The parasitic capacitanceof the diode ( C s ) and the winding capacitance ( C ws ) on thesecondary side are reected to the primary side with the valueof n2 times. When selecting Q p and f ns it should be notedthat there exists a minimum resonant capacitance C r .

IV. D ESIGN PROCEDURE

From the operational analysis described above, the designprocess of a high voltage yback converter with resonantelements is considered in this section and a design example isgiven based on a 150mW prototype converter.

Step 1 Dene the system specications: The input voltageV in , output voltage V o , output power P o , switching frequencyf s , parasitic capacitance of the switch C p , parasitic capaci-tance of the diode C s and the winding capacitance C ws .

Step 2 Select the characteristic impedance ratio Q p andthe normalized switching frequency ratio f ns : The key de-sign parameter is the power loss of the switch. Mechanisms

that cause power loss are discussed in Chapter 3, includingswitching loss.

Step 3 Determine M and 1 4 : With Q p and f nsselected, the switch conversion ratio M is reected to theprimary side and the phase variables of each mode 1 4can be found from (18a e). If M < 1, other values of Q pand f ns should be selected.

Step 4 Determine the turns ratio n and the resonant elementssuch as Lm and C r : The turns ratio n of the high voltagetransformer can be found from M specied in Step 3.

n = M V g

V o. (27)

The characteristic impedance Z o and the resonant frequencyf o can be determined, using Q p , f ns and equation (27).

Z o =n2RL

Q p, f o =

f sf ns

. (28)

From equation (28), the resonant elements are obtained as:

Lm =Z o

2f o, C r =

12Z o f o

. (29)

Check to see if the resonant capacitor C r is larger thanC r min equals C s + C ws . If not, return to Step 2, i.e. selectother values of Q p and f ns .

Fig. 6. Circuit topology design for high output voltage application :V g = 24 V , V o = 1220V , V c 1 = 610 V , Q = KS D 526 Y , D 1,

D 2 = 718 , L m = 100 .8H , C r = 50 .58nF , C o , C 1 = 470 pF ,R L = 10 M .

Step 5 Determine the maximum voltage and current stresson the switch: From equation (3), the peak current of themagnetizing inductance can be expressed as:

iLm,pk = V gZ o 2 + i(0) 2 . (30)The voltage stress of the switch and the output diode are

expressed as:

V ds, max = V g + nV O , V d, max = V O +1n

V g . (31)

A. Design Example

Low input voltage, high output voltage and low power levelapplications, are the areas where high voltage yback con-verters can be particularly advantageous. As an example, weconsider the design of a 150mW yback DC-to-DC converteraccording to the following specications:

range of input voltage: V g, min =24V , V g, max =27 V output voltage: V o =1.22kV (using voltage doubler:V c1=610V ) load range: 12.2A I o 122A switching frequency: f s =70kHz minimum capacitance: C p =90 pF , C s =10 pF , C ws =20 pF

The high output voltage yback power circuit in this exam-ple is shown in Fig. 6. Using Step 2, Q p and f ns are selected asQ p =84 and f ns =0.933 respectively. It is noted that this designexample features a low input voltage, an extremely high outputvoltage and a small load range in a real printer application.Thus, Q p and f ns are selected to be large values. Fromequation (19), the switch conversion ratio M and 1 4are obtained as M =1.0163, 1=2.362, 2=0.338, 3=3.321 and4=0.253 respectively. Since M > 1, we can proceed to thenext step. From equation (27), the turns ratio n of the highvoltage transformer is obtained as n=0.04. From equation (28),the characteristic impedance Z o and the resonant frequencyf o are Z o =44.66 and f o =70.45kHz . Finally, from equation(29), the resonant elements are obtained as Lm =100.8H and C r =50.58nF . We observe that C r satises the desiredconstraint on the minimum C r , where C r min =18.86nF . From(30), the peak current is iLm,pk =586mA . From (31), thepeak drain-to-source and diode voltage are V ds, max =48.4V andV d, max =1210V , respectively. The key components include: theswitch Q: KSD 526-Y and the output diode D : 718.

7/28/2019 1-JPE09133

6/8


V. S IMULATION A ND E XPERIMENT

To verify the analysis and design procedure presented inthis paper a PSIM simulation and an experiment were carriedout on an actual high voltage yback converter with resonantelements using the specications and parameters listed inTable 1. A schematic representation of the yback convertermodeled in the simulation program is shown in Fig. 6.

The high voltage yback converter with resonant elementsconsists of an ideal transformer, a magnetizing inductance anda resonant capacitor. In order to make the design process moreefcient, the PSIM simulation data contains key waveformssuch as the voltage stress on the switch, the magnetizing in-ductor current and the resonant capacitor voltage. This yback design example is included to demonstrate an application of the procedure, and the results are supported by a simulation.The simulation and theoretical results are compared in Table 2,which shows the design parameters and the simulated valuesof the key voltage and the current waveforms during thewhole switching period. Fig. 7 shows the results of the PSIM

simulation, which contains the key voltage and the currentwaveforms of the high voltage yback converter. It can beseen that the PSIM simulation results coincide well with thepredicted results shown in Fig. 4 and Table 2.

TABLE IPARAMETERS O F E XPERIMENTAL C IRCUIT

Part Value TypeSwitch Q V ce : 80V KSD 526-Y

Diode ( D 1 , D 2 ) V r : 6kV 718Transformer ( L m ) 100.8 H Ferrite Core

Capacitor ( C 1 , C o ) 470 pF C 1 : ceramics / C o : ALLoad Resistor ( R

L) 10M Non-Inductive Resistor

TABLE IIDATA O F D ESIGN VALUE A ND IMULATION R ESULT

Design SimulationParameter

value ResultDeviation

V c 1220[V ] 1205[V ] 1.23[%]i (0) 233 .2[mA ] 218.3[mA ] 6.39[%]i (t 1 ) 211 .0[mA ] 210.1[mA ] 0.85[%]

t 1 t 0 5.338[s ] 5.35[s ] 0.26[%]t 2 t 1 0.877[s ] 0.89[s ] 1.48[%]t 3 t 2 7.502[s ] 7.49[s ] 0.16[%]t 4 t 3 0.571[s ] 0.56[s ] 1.93[%]

TABLE IIIDATA O F M EASURED R ESULT A ND S IMULATION R ESULT

Measured DesignParameter

result resultDeviation

V o 1226[V ] 1205[V ] 1.71[%]V ce, max 50.3[V ] 48.5[V ] 3.58[%]V cr, max 24.7[V ] 24.0[V ] 2.83[%]V cr, min 26.0[V ] 24.0[V ] 5.80[%]

V scc, max 637[V ] 600[V ] 5.81[%]

V scc, min 655[V ] 613[V ] 6.41[%]

Fig. 7. PSIM simulation results for the design circuit operating at 1205V dc output.

(a) Simulation results

(b) Experimental results

Fig. 8. Key waveforms of high voltage yback converter.

Fig. 8 shows the experimental waveforms of Fig. 6, V o ,V Cr , V sec and V ds , respectively. Each waveform shows goodagreement with the simulation and the experimental results inTABLE III. As can be seen, the output voltage ( V o ) is about -1226V. The designed value and the simulated value are -1220Vand -1205V, respectively. In addition, the measured outputvoltage was within 1.23% of the calculated value, verifyingthe accuracy of the equations given here. The other measuredparameters are also similar to the calculated and simulatedvalues.

The measured power loss of the switch is shown in Fig.

9 and TABLE IV, which shows the waveforms of V ce , I c

7/28/2019 1-JPE09133

7/8


Fig. 9. Switch power loss of experimental measurements.

TABLE IVDATA O F M EASURED R ESULT

Parameter Measured resultV ce, max 51.0[V ]V ce, min 0.4[V ]I c, max 145[mA ]

P sw Loss 0.159[W ]

and P sw Loss , respectively. As can be seen, the power lossis negligible. The temperature of the switch is about 30.4 Cat an ambient temperature of 24.1 C. It is veried that byconsidering the parasitic capacitance of transformer, the outputvoltage of the actual low power high voltage output yback converter can be precisely predicted.

VI. C ONCLUSIONS

The effect of the resonant elements in a dc/dc converter witha transformer can be very important and must be consideredwhen designing a high voltage yback converter. The rstrequirement of a yback converter used in low power levelhigh output voltage applications is that the output voltageshould be obtained at the expected value. Unlike an idealyback converter, the output voltage of a real converter isrestricted by the parasitic properties of the high voltageyback transformer. The inuence of the transformers straycapacitance is dominant.

In this paper, to analyze the effects of these resonant ele-ments, an equivalent circuit was derived. The design considera-

tions and a design example of a high voltage yback converterwith 150mW have been presented. The design, simulation andexperimental results were also given and the results agree wellwith the analytical results. This design procedure is expectedto be well suitable for high output voltage applications.

ACKNOWLEDGMENT

This work was supported by the research program 2010of Kookmin University, Korea and also by the Ministry of Knowledge Economy (MKE), Korea, under the InformationTechnology Research Center (ITRC) support program super-vised by the Institute of Information Technology Advancement

(IITA) under Grant IITA2009-C10900904-0002.

R EFERENCES

[1] Shelton Gunewardena, Wendel E. Archer, Robert O. Sanchez, Highvoltage miniature transformer design, Electrical Insulation Conferenceand Electrical Manufacturing & Coil Winding Conference, 2001 Pro-ceedings, pp.141-147, 2001.

[2] M. J. Prieto, A. Fernandez, J. M. Diaz, J. M. Lopera, J. Sebastian,Inuence of transformer parasitics in low-power applications, Applied Power Electronics Conference and Exposition, 1999 APEC99 Four-teenth Annual, Vol.2, pp.1175-1180, Mar. 1999.

[3] MIT, Staff of Dept of EE, Magnetic circuit and transformer, MIT Press,1965

[4] McArdle, J., Wilson, T.G. Jr., and Wong, R.C., Effects of powertrain parasitic capacitance on the dynamic performance of DCto-DCconverters operating in the discontinuous MMF mode, IEEE Trans. onPower Electron., Vol. 2, No. 1, pp.219, Jan. 1987.

[5] Lu, H.Y., Zhu, J.G., Ramsden, V.S., and Hui, S.Y.R., Measurementand modeling of stray capacitance in high frequency transformer, IEEE Power Electronics Specialist Conf. Rec., pp.763768, Jun. 1999.

[6] Lu, H.Y., Zhu, J.G., and Hui, S.Y.R., Experimental determination of stray capacitances in high frequency transformers, IEEE Trans. onPower Electron., Vol. 18, No. 5, pp.1105111, Jun. 2003.

[7] S.-K. Chung, Transient characteristics of high-voltage yback trans-former operating, Applied IEE Proceedings Electric Power Applica-tions, Vol. 151,No. 5, pp.628-634, Sep. 2004.

[8] Huang Kewei, Li Jie, Hu Xiaolin, Fan Ningjun, Analysis and simulationof the inuence of transformer parasitics to low power high voltageoutput yback converter, IEEE Industrial Electronics InternationalSymposium, pp. 305-310, Jun. 2008.

[9] Ramsden, V.S., Lu, H.Y., and Zhu, J.G., Dynamic circuit modeling of a high frequency transformer, IEEE Power Electronics Specialist Conf. Rec., Vol. 2, pp.147914857, May 1998.

[10] Robert W, Dragan M, Fundamentals of Power Electronics, BoulderColorado, 2002.

[11] Tabisz, W.A.; Gradzki, P.M.; Lee, F.C.Y., Zero-voltage-switched quasi-resonant buck and yback converters- experimental results, IEEE Trans.on Power Electron., Vol. 4, No. 2, pp.194-204, Apr. 1989.

[12] Vorperian, V., Quasi-square-wave converters: topologies and analysis, IEEE Trans. on Power Electron., Vol. 3, No. 2, pp. 183-191, Apr. 1988.

Sung-Soo Hong received his B.E. degree in ElectricalEngineering from Seoul National University, Seoul,Korea, in 1980, and his M.S. and Ph.D. in Electricaland Electronics Engineering from the Korea AdvancedInstitute of Science and Technology, Seoul, Korea, in1986 and 1992, respectively. From 1984 to 1998, hewas an Electronics Engineer with Hyundai ElectronicsCompany. In 1993, he was with the Virginia PolytechnicInstitute and State University, Blacksburg, as a Research

Scientist. Since 1999, he has been an Assistant Professor in the ElectronicsEngineering Department, Kookmin University, Seoul, Korea. His researchinterests are in the areas of modeling and control techniques for powerconverters, EMI analysis and reduction techniques for power electronicscircuits.

Sang-Keun Ji was born in Seoul, Korea in 1981. Hereceived his B.S. and M.S. in Electronics Engineeringfrom Kookmin University, Seoul, Korea, in 2007 and2009, respectively, where he is currently working towardhis Ph.D. in the School of Electronics Engineering. Hisresearch interests are in the areas of high-efciencypower converters and renewable energy applications.Mr. Ji is a member of KIPE (Korean Institute of PowerElectronics).

Young-Jin Jung was born in Seoul, Korea in 1978.He received his B.S. in Electronics Engineering fromSuwon University, Suwon, Korea, in 2004. He receivedhis M.S. in Electronics Engineering from KoookminUniversity, Seoul, Korea, in 2008. Since 2006, he hasbeen with Department of Power Electronics, KookminUniversity, where he is currently a doctoral student.His research interests are in the areas of modelingand control of converters and inverters. Mr. Jung is a

member of KIPE (Korean Institute of Power Electronics).

7/28/2019 1-JPE09133

8/8


Chung-Wook Roh was born in Korea in 1971. Hereceived his B.S., M.S., and Ph.D. in Electrical En-gineering and Computer Science from the Korea Ad-vanced Institute of Science and Technology (KAIST),Taejon, Korea, in 1993, 1995, and 2000, respectively.In 2000, he joined the Digital Media Network Division,Samsung Electronics Company, Suwon, Korea, wherehe was a Project Leader of the Plasma Display DriverDevelopment Team. Since 2004, he has been with the

department of Electrical Engineering, Kookmin University, Seoul, Koreawhere he is currently an Associate Professor. His research interests includedriver circuits of displays such as light emitting diodes, plasma display panels,

low-power circuits for at panel displays, as well as the modeling, design, andcontrol of power conversion circuits, soft-switching power converters, resonantinverters, and electric drive systems. He is the author or coauthor of more than100 technical papers published in journals and conference proceedings andhas more than 50 patents. Dr. Roh has received several awards including aBest Presentation Award from the annual conference of the IEEE IndustrialElectronics Society in 2002, a Best Paper Award from the Korean Institute of Power Electronics in 2003 and a Best Paper Award from the Korean Instituteof Power Electronics in 2009, respectively. He is currently a journal editorfor the Korean Institute of Power Electronics.

1-jpe09133

Documents