1 mips תיאור מפושט של מעבד החיבורים המתוארים תומכים בכל...

1

MIPS מעבד של מפושט תיאור

ALUPCInstruction

Instructionmemory

#register

Registers

Data

#register

#register

address

Datamemory

Data

פקודות שלבי בכל תומכים המתוארים - R-typeהחיבורים I-typeו : בפקודות נתמוך add, sub, or, xor, and, slt, lw, sw, beq, jאנו

: למשל כמו נוספות פקודות מוסיפים כיצד לדעת שנצטרך ,bne, addiכמובןjal, jr

2

PCInstruction

memory

4

Registers

Mux

Mux

Mux

ALU

EX

M

WB

M

WB

WB

ID/EX

0

EX/MEM

MEM/WB

Datamemory

Mux

Hazarddetection

unit

Forwardingunit

IF.Flush

IF/ID

Signextend

Control

Mux

=

Shiftleft 2

Mux

שבועות שלושה עוד

3

שלבי ביצוע הוראת מכונה(1 )FETCH-קרא הוראה מהזיכרון ע"פ הכתובת שמכיל ה = PC.(2 )DECODE פענח את הפקודה וקרא את האוגרים הנחוצים =

)אחד או שניים(.(3 )EXECUTE-בעזרת ה = ALU חשב את התוצאה, או כתובת

רצויה.(4 )MEMORY השתמש בתוצאה לבצע במידת הצורך: או =

(.Load( או קריאה מהזיכרון )Storeטעינה לזיכרון )(5 )WRITE BACK.בצע במידת הצורך טעינה לאוגר =

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קוראים השעון מחזור כל במשךכותבים השעון בסוף

cycle time

rising edge

falling edge

, תשנה - שעון עליית כל השעון פי על מיוצרים הבקרה קווי) נדרש ) אם הבקרה קווי את בעקבותיה

5

Single cycle data paths

Processor uses synchronous logicdesign (a “clock”).

f T

1 MHz 1 μs

10 MHz 100 ns

100 MHz 10 ns

1 GHz 1 ns

All state elements act like positive edge-triggered flip flops.

D Q

clk

6

Edge-Triggered D Flip Flops

D Q

CLK

Value of D is sampled on positive clock edge.Q outputs sampled value for rest of cycle.

D

Q

7

Single cycle data paths: Definition

All instructions execute in a single cycle of the clock (positive edge to

positive edge)Advantage: a great way to learn CPUs.

Drawbacks: unrealistic hardware assumptions,

slow clock period

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Recall: MIPS R-format instructions

Instruction

Fetch

Instruction

Decode

Operand

Fetch

Execute

Result

Store

Next

Instruction

Fetch next inst from memory:012A4020

opcode rs rt rd functshamtDecode fields to get : ADD $8 $9 $10

“Retrieve” register values: $9 $10

Add $9 to $10

Place this sum in $8

Prepare to fetch instruction that follows the ADD in the program.

Syntax: ADD $8 $9 $10 Semantics: $8 = $9 + $10

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Separate Read-Only Instruction Memory

32

Addr

Data

32

זכרוןפקודות Reads are combinational: Put a

stable address on input, a short time later data appears on output.

טעינת התוכנית לזכרון

לא מעניננו כרגע

זכרון (מטמון) נפרד לפקודות ולנתונים

)Instruction Memory & Data

Memory(

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1שלב : Straight-line Instruction Fetch

32

Addr

Data

32

InstrMem

Fetching straight-line MIPS instructions requires a machine that generates this timing diagram:

Why +4 and not +1?

Why do we increment every clock cycle?

CLK

Addr

Data IMem[PC + 8]IMem[PC + 4]IMem[PC]

PC + 8PC + 4PC

PC == Program Counter, points to next instruction.

11

New Component: Register (for PC)

In later examples, we will add an “enable” input: clock edge updates state only if enable is high

32Din

Clk

PC

Dout32

Built out of an array of 32 flip-flops

D Q

clk

D Q

D Q

Din0

Din1

Din2

Dout0

Dout1

Dout2

12

New Component: A 32-bit adder (ALU)

Combinational:היציאה שווה לסכום ערכי

B ו-Aכניסה מלפני זמן קצר (~ ננו

שניה).

32+

32

32

A

B

A + B

32ALU

32

32

A

B

A op B

op

ln(#ops)ALU:

כנ"ל רק למס פונקציות .opרבות לפי הבורר

Zero?

Sometimes, extra outputs for use by control logic ...

13

Design: Straight-line Instruction Fetch

CLK

Addr

Data IMem[PC + 8]IMem[PC + 4]IMem[PC]

PC + 8PC + 4PC

Clk

32Addr Data

InstrMem

32D

PC

Q32

32

+

32

320x4

+4 in hexadecimal

State machine design in the service of an ISA

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Instruction

Fetch

Instruction

Decode

Operand

Fetch

Execute

Result

Store

Next

Instruction




Add $9 to $10




Goal #1: An R-format single-cycle CPU

Done!

To continue, we need registers ...

15

Register files:

R1

R2

...

R31

Why is R0 special?

Q

Q

Q

R0 - The constant 0 Q

clk

.

.

.

.

.

32MUX

32

32

sel(rs1)

5

.

.

.

rd1

32MUX

32

32

sel(rs2)

5

.

.

.

rd2

“two read ports”

wd

D

D

D

En

En

En

DEMUX

.

.

.

sel(ws)5

WE

32

16

Register File Schematic Symbol

32rd1

RegFile

32rd2

WE32wd

5rs1

5rs2

5ws

Why do we need WE (Write Enable)?If we had a register file w/o WE, how could we work around it?

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Instruction

Fetch

Instruction

Decode

Operand

Fetch

Execute

Result

Store

Next

Instruction




Add $9 to $10




Goal #1: An R-format single-cycle CPU

What do we do with these?

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Computing engine of the R-format CPU

32rd1

RegFile

32rd2

WE32wd

5rs1

5rs2

5ws

32ALU

32

32

op

opcode rs rt rd functshamt

Decode fields to get : ADD $8 $9 $10

Logic

What do we do with WE?

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Putting it all together ...

32rd1

RegFile

32rd2

WE32wd

5rs1

5rs2

5ws

32ALU

32

32

op

LogicIs it safe to use same clock for PC and RegFile?

32Addr Data

InstrMem

32D

PC

Q32

32

+

32

320x4

To rs1,rs2, ws, op decodelogic ...

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Reminder: How data flows after posedge

32rd1

RegFile

32rd2

WE32wd

5rs1

5rs2

5ws

32ALU

32

32

op

Logic

Addr Data

InstrMem

D

PC

Q+

0x4

21

Next posedge: Update state and repeat

32rd1

RegFile

32rd2

WE32wd

5rs1

5rs2

5ws

D

PC

Q

22

A CPU capable of R-type instructions only

5[25:21]=Rs

5[20:16]=Rt

5[15:11]=Rd

InstructionMemoryPC

Adder4

ck

6[31:26]

6[5:0]=funct

?איך זה נראה בספר

25


5[25:21]=Rs

5[20:16]=Rt

5[15:11]=Rd

Reg File

InstructionMemoryPC ALU

Adder4

ck

ck

6[31:26]

6[5:0]=funct


26


5[25:21]=Rs

5[20:16]=Rt

5[15:11]=Rd

Reg File


Adder4

ck

ck

6[31:26]

6[5:0]=funct


32

I-format ALU instructions: 2יעד מס

Syntax: ORI $8 $9 64 Semantics: $8 = $9 | 64

16-bit immediate extended to 32 bits.

In this example, $8 (the result register) is rt !!! (was rd previously).

Zero-extend: 0x8000 ⇨ 0x00008000

Sign-extend: 0x8000 ⇨ 0xFFFF8000

Some MIPS instructions zero-extend immediate field, other instructions

sign-extend.

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Computing engine of the I-format CPU

32rd1

RegFile

32rd2

WE32wd

5rs1

5rs2

5ws

32ALU

32

32

op

Decode fields to get : ORI $8 $9 64

Logic

In a Verilog implementation, what should we do with rs2?

Ext

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Merging data paths ...

I-format

R-formatAdd muxes

How many ?

Where ?

35

The merged data path ...

32rd1

RegFile

32rd2

WE32wd

5rs1

5rs2

5ws

32ALU

32

32

op

opcode rs rt rd functshamt

ALUsrc

Ext

ExtOp

ALUctr

RegDest

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Loads, Stores, and Data Memory ...

32Dout

Data Memory

WE32Din

32Addr

Syntax: LW $1, 32($2) Syntax: SW $3, 12($4)

Action: $1 = M[$2 + 32] Action: M[$4 + 12] = $3

Zero-extend or sign-extend immediate field?

Writes are clocked: If WE is high, memory Addr captures Din on positive edge of clock.

Reads are combinational: Put a stable address on Addr,a short time later Dout is ready

Note: Not a realistic main memory (DRAM) model ...

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- ה ?CPUאיפה

CPU

InstructionMemory

DataMemory

PC

39

A CPU capable of lw instructions only

5[25:21]=Rs

5[20:16]=Rt

Reg File


Adder4

ck

ck

6[31:26]

RegWrite=1

16[15:0]

5

add

Sext16->32

DataMemory

AddressD. Out

40

A CPU capable of lw instructions only

5[25:21]=Rs

5[20:16]=Rt

Reg File


Adder4

ck

ck

6[31:26]

RegWrite=1

16[15:0]

5

add

Sext16->32

DataMemory

AddressD. Out

41

A CPU capable of lw & sw instructions only

5[25:21]=Rs

5[20:16]=Rt

Reg File


Adder4

ck

ck

6[31:26]

RegWrite=0

16[15:0]

5

add

Sext16->32

DataMemory

D.In

Address

MeWrite=1

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A CPU capable of R-type & lw instructions (principle)

5[25:21]=Rs

5[20:16]=Rt

Reg File


Adder4

ck

ck

6[31:26]

RegWrite

16[15:0]

5

add

Sext16->32

DataMemory

5[25:21]=Rs

6[5:0]=funct ALUcontrol

5[15:11]=Rd

Address

43

A CPU capable of R-type & lw instructions

5[25:21]=Rs

5[20:16]=Rt

Reg File


Adder4

ck

ck

6[31:26]

RegWrite

16[15:0]

5

add

Sext16->32

DataMemory

5[25:21]=Rs


Rd

AddressD. Out

44

A CPU capable of R-type & lw/sw instructions

5[25:21]=Rs

5[20:16]=Rt

Reg File


Adder4

ck

ck

6[31:26]

RegWrite

16[15:0]

5

add

Sext16->32

DataMemory

5[25:21]=Rs


Rd

Address

D.In

D. Out

MemWrite

45

Conditional Branches in MIPS ...

Syntax: BEQ $1, $2, 12

Action: If ($1 != $2), PC = PC + 4

Zero-extend or sign-extend immediate field?

Action: If ($1 == $2), PC = PC + 4 + 48

Immediate field codes # words, not # bytes.

Why is this encoding a good idea?

46

:Branch להוספת דרושים אלמנטים

ALU

Zero

Readregister 1

Registers

Readregister 2

Write register

WriteData

Readdata 1

Readdata 2

Instruction

AdderSum

Shiftleft 2

SighExtend

BranchTarget

מועברליחידתהבקרהכתוצאההלוגית

שלההשוואה

16 32

PC+4 - ה FetchמשלבIn addresses, we always shift left by two bits

47

Design: Instruction Fetch with Branch

Clk

32Addr Data

InstrMem

32D

PC

Q

32

32+

32

32

0x4

Syntax: BEQ $1, $2, 12Action: If ($1 != $2), PC = PC + 4Action: If ($1 == $2), PC = PC + 4 + 48

PCSrc

32

+32

Extend

48

שילוב כל הפקודות

Readregister 1

Registers

Readregister 2

Write register

WriteData

Readdata 1

Readdata 2

Zero

ALU

ALUresult

Data

Signextend 32

Readaddress

memory

Writeaddress

Writedata

Readdata

Write

Read

16

Add4

PC

Mux

Readaddress

Instruction

Instructionmemory

ADD

ALUresult

Shiftleft 2

Mux

Mux

49

What is single cycle control?

32rd1

RegFile

32rd2

WE32wd

5rs1

5rs2

5ws

ExtRegDest

ALUsrcExtOp

ALUctr

MemToRegMemWr

Equal

RegWr

32Addr Data

InstrMem

Equal

RegDestRegWr

ExtOpALUsrc MemWr

MemToReg

PCSrc

Combinational Logic(Only Gates, No Flip Flops)

Just specify logic functions!

50

בקרה קווי

PC

Instructionmemory

Readaddress

Instruction

16 32

AddMux

Registers

Writeregister

Writedata

Readdata 1

Readdata 2

Readregister 1Readregister 2

4

Mux

ALU operation3

RegWrite

MemRead

MemWrite

PCSrc

ALUSrc

MemtoReg

ALUresult

ZeroALU

Datamemory

Address

Writedata

Readdata M

ux

Signextend

AddALU

resultShiftleft 2

51

Control

PC

Instructionmemory

Readaddress

Instruction[31– 0]

Instruction [20– 16]


Add


MemtoReg

ALUOp

MemWrite

RegWrite

MemRead

BranchRegDst

ALUSrc


4

16 32Instruction [15– 0]

0

0Mux

0

1

Control

Add ALUresult

Mux

0

1

RegistersWriteregister

Writedata

Readdata 1

Readdata 2

Readregister 1

Readregister 2

Signextend

Shiftleft 2

Mux

1

ALUresult

Zero

Datamemory

Writedata

Readdata

Mux

1


ALUcontrol

ALUAddress

52

Instruction RegDst ALUSrcMemto-

RegReg

WriteMem Read

Mem Write Branch ALUOp1 ALUp0

R-format 1 0 0 1 0 0 0 1 0lw 0 1 1 1 1 0 0 0 0sw X 1 X 0 0 1 0 0 0beq X 0 X 0 0 0 1 0 1

R-format Iw sw beq

Op0

Op1

Op2

Op3

Op4

Op5

Inputs

Outputs

RegDst

ALUSrc

MemtoReg

RegWrite

MemRead

MemWrite

Branch

ALUOp1

ALUOpO

Control

53

ALU control

ALUOp Funct field OperationALUOp1 ALUOp0 F5 F4 F3 F2 F1 F0

0 0 X X X X X X 0100 1 X X X X X X 1101 0 X X 0 0 0 0 0101 0 X X 0 0 1 0 1101 0 X X 0 1 0 0 0001 0 X X 0 1 0 1 0011 0 X X 1 0 1 0 111

ALU control output000 AND001 OR010 add110 subtract111 set-on-less-than

(sign of rs-rt -> rd)

00 = lw, sw01 = beq, 10 = arithmetic

ALUop

Operation2

Operation1

Operation0

Operation

ALUOp1

F3

F2

F1

F0

F (5– 0)

ALUOp0

ALUOp

ALU control block

54

- ה jumpפקודת

4 bits 26 bits 2 bits

00

קפיצה : כתובתבבתים :במילים קפיצה כתובת

0110

101 … 101111011

101 … 101111011

101 … 101111011

00 101 … 1011110110110 הסופית : הקפיצה

ביטים 4תוספת : אחרונים

: הפקודה J 101…101111011 פירוש

בכתובת נמצאת הבאה 1001…111111011הפקודה

55

Jump

Shiftleft 2

PC

Instructionmemory

Readaddress

Instruction[31– 0]

Datamemory

Readdata

Writedata

RegistersWriteregister

Writedata

Readdata 1

Readdata 2

Readregister 1

Readregister 2




Add

ALUresult

Zero


MemtoReg

ALUOp

MemWrite

RegWrite

MemRead

Branch

JumpRegDst

ALUSrc

I nstruction [31– 26]

4

Mux

Instruction [25– 0] Jump address [31– 0]

PC+4 [31– 28]

Signextend

16 32Instruction [15– 0]

1

Mux

1

0

Mux

0

1

Mux

0

1

ALUcontrol

Contr ol

Add ALUresult

Mux

0

1 0

ALU

Shiftleft 226 28

Address

1 mips תיאור מפושט של מעבד החיבורים המתוארים תומכים בכל...

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