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Students: Lin IliaKhinich Fanny

Instructor: Fiksman Evgeny

ספרתיות למערכות המעבדהמהירות

High Speed Digital Systems Laboratory

הטכניון - מכון טכנולוגי לישראל

הפקולטה להנדסת חשמל

Technion - Israel institute of technologydepartment of Electrical Engineering

Mid Stage Presentation

Virtex II Pro FPGADynamic Reconfiguration

Spring semester 2005

Abstract

• Partial reconfiguration involves defining distinct portions of an FPGA design to be reconfigured while the rest of the device remains in active operation.

• Active partial reconfiguration is done when the device is active.

Virtex II Pro Architecture

Configuration Data

Bits that directly define the state of programmable logic.

Configuration File

The internally stored file that controls the FPGA so that it performs the desired logic function.

Configuration of Virtex II Pro

Configuration Frame The smallest number of

bits that can be read or written through the configuration interfaces is one frame.

Configuration Interface A logical interface

through which configuration commands and data can be read and written.

Configuration of Virtex II Pro

Configuration

Protocol

The protocol used by configuring device. There are two protocols used in the project: SelectMAP and BoundaryScan.

Modular Design

Allows to independently work on different pieces, or modules of a design and later merge these modules into one FPGA design.

Module-based Partial Reconfiguration

Module-based Partial Reconfiguration is used when

communication is needed between modules.

System Architecture

PLB

OPB

ControllerInterface

PPC405 BRAM

ICAP

UART

ReconfigurableLogic

RAM

Microblaze

CPUInterface

ICAPInterface

ICAP Interface

The fundamental module used to perform in-circuit reconfiguration of Virtex-II Pro devices.

ICAP Interface

A direct access to the configuration registers as

well as a configuration data transfer using the

SelectMAP" protocol.

Physical Limitations

For current FPGA devices, data is loaded on a column-basis, with the smallest load unit being a configuration bitstream "frame".

Physical Limitations

1. Height

2. Width

3. Horizontal placement

4. All logic encompassed by the width of the module are considered part of it’s "frame."

Physical Limitations

5. Clocking logic.

6. IOBs immediately above and below reconfigurable module.

7. IOBs on the edge of a leftmost or rightmost slice reconfigurable module.

Implementation details

The considered physical limitations are applied on the bitstream compilation stage:

ngdbuild –uc system.ucf

Partial bitstream:

bitgen –r …

Achievements

• Complete hardware device.

• Partial configuration file.

Next Steps

1. Test partial reconfiguration from the Xilinx software.

2. Main core software.

3. Reconfiguration core software.

4. Changes in hardware architecture.

5. Running the complete system.

6. Documentation for the performed steps.