1.1 ZVZCS-FB-PWM principle

ZVS-FB-PWM轉換器的架構

ZVZCS-FB-PWM 轉換器的操作波形 Mode 1: QA及QD 導通，輸入功率經由變壓器而傳至負載端。在此模式期間，阻隔電容器Cb兩端電壓從負的最大值呈線性增加。

Vin

A

B

C

D

i

Tr C1

Mode 2: QA截止，變壓器㆒次側電流I對QA的輸出電容CA充電，對QB的輸出電容CB放電，接著㆓極體DB導通(QB的反向並接㆓極體)。其㆗QB能夠以完全的ZVS方式導通。

Vin

A

B

C

D

i

Tr C1

Mode 3:在QB開始導通時，反流器之輸出電壓 Mode 4:當變壓器在㆒次側電流I降到零值時， VAB 被拑制為零值，此時與輸入電壓源Vi相比， 其會有往負值方向增加的變動傾向。阻隔電容器 其值非常小之阻隔電容器Cb兩端的電壓，則施 Cb㆖的電壓完全施加在Lik及變壓器的㆒次側㆖， 加在漏電感Lik㆖。阻隔電容器Cb可視為定電壓 使㆒次側的電流I繼續保持為零值。在此期間Cb的 源，變壓器㆒次側電流I呈線性㆘降而達到零值。 電壓保持定值，QD仍然為導通的狀態，但是沒

有電流流過。

Vin

A

B

C

D

i

Tr C1

Mode 5: QD完全以ZVS及的操作方式截斷，此時變壓器㆒次側為開路狀態。

Vin

A

B

C

D

i

Tr C1

Mode 6: 在QC導通後，因為高電壓施加到漏電感Lik㆖，使變壓器㆒次側電流I呈線性增加。至此則完成㆒個操作週期。

Vin

A

B

C

D

i

Tr C1

1.2 Meansurement of primary side Object: Primary side waveform of OZ960, MosFET and Transformer test report Conditions:

Operation frequency: 60KHz Ambient temperature: 24°C Panel: LG 14.1” TFT XGA, model: LP141XA-D1AP Scope: Tektronix TDS 360, S/N: A1003 Current probe: Tektronix P6022, S/N: B1006 Power supply: GW GPC-3030D, S/N: A1011 Thermal tester: OPTEX PT-3S, S/N: A1010

Test Item: 1. OZ960 output waveform 2. MosFET output waveform 3. Transformer Primary side voltage and current waveform Test result: 1. In Fig A, The switches of MosFET A, B, C and D are configured such that MosFET A

and B, C and D are turned on complementarily. The duration of A and D, B and C turn on simultaneously determines an amount of energy put into the transformer. When B and D shift left simultaneously, the duty cycle become short.

2. In Fig B. The third waveform is a mathematical waveform from V_AB-V_CD which V_AB is Drain of MosFET A, B and V_CD is Drain of MosFET C, D. It equal Vc add transformer primary voltage as fourth and fifth waveform.

3. Fig C is show the timming of OZ960 output waveform and primary side of transformer.

Fig A

Fig B

Fig C

2. OZ960 function description

CTIMR: Capacitor for CCFL ignition duration

Determine the necessary striking time. An approximate of the timing calculation is: T[second]=C[uF] This capacitor remains reset at no charge if lamp is connected and at normal operation.

OVP: Output voltage sense Vth=2.0V It ensures that output gets sufficient striking voltage while operating the power transformer safely.

Protection Open-lamp protection in the ignition period is provided through both OVP and CTIMR to ensure a rate voltage is achieved and a required timing is satisfied. Removal of the CCFL during normal operation will trigger the current amplifier output and shuts off the inverter. This is a latch function.

C8

1.0U

OZ960

U2OZ960/SSOP20

1

2

3

4

5

6

18

17

16

15

14

138

7

19

9

10

12

11

20CTIMR

OVP

ENA

SST

VDDA

GNDA

CT

RT

PWRGND

LCT

DIM

LPWMRT1

REF

PDRV_A

FB

CMP

PDRV_C

NDRV_D

NDRV_B

CN1

1

2

T1

CR2

31

2

C6

R14C7

Vo

Vo'

+

-

C14

1. C8 is control striking time. Stricking time[second ] = C8[uF]. When output is open, the voltage of OVP is over than 2V then the CTIMER start to account striking time. 2. The OVP threshed is set at 2V. Output voltage is set by C6 and C14. The Vo is calculated as:

' 6

6 1 4'

'6 1 4

6

6 1 4

6

2 2

2 .8

o O

o

o o

o

CV VC C

V D io d e d r o p v o l t a g eC CV V

CC CV

C

= ×+

= + ≅+

= ×

+= ×

. 8

a.

1. t: 0~t1 2. t: t1~t2 3. t: t2~t3

VmVinVout == DC

D

VVmVVVout+−=

−=DC VVmVVinVout −=−= 2

b.

c.

DM

ML

RCTML

VVVVoutVV

TRCifeVV

−==⇒=⇒

>>→⋅= − /

d.

( )

( ) ( ) 12122

221

12'2

211'

2'22'2max

CCCVVoutVV

VVoutCC

CVV

CCCVV

VDVoutVVVVVaVout

DppH

D

DD

++==⇒

+=+

=∴

+=

+=⇒

−=−=

−

Θ

ENA: Enable input; TTL signal is applicable

ON/OFF

OZ96

0

U2OZ960/SSOP20

1

2

3

4

5

6

18

17

16

15

14

138

7

19

9

10

12

11

20CTIMR

OVP

ENA

SST

VDDA

GNDA

CT

RT

PWRGND

LCT

DIM

LPWMRT1

REF

PDRV_A

FB

CMP

PDRV_C

NDRV_D

NDRV_BR15

C9

R15 and C9 recifier the noise from ON/OFF. When VENA>1.5V, the IC will be turn on.

SST: Soft-start capacitor

The soft-start time is not related to the striking time for the CCFL. It simply provides a rate of rise for the pulse width where diagonal switches are turned on. Normally, a 0.47uF capacitor is connected.

OZ960

U2OZ960/SSOP20

1

2

3

4

5

6

18

17

16

15

14

138

7

19

9

10

12

11

20CTIMR

OVP

ENA

SST

VDDA

GNDA

CT

RT

PWRGND

LCT

DIM

LPWMRT1

REF

PDRV_A

FB

CMP

PDRV_C

NDRV_D

NDRV_B

C10

VDDA: Voltage source for the IC

5V

OZ960

U2OZ960/SSOP20

1

2

3

4

5

6

18

17

16

15

14

138

7

19

9

10

12

11

20CTIMR

OVP

ENA

SST

VDDA

GNDA

CT

RT

PWRGND

LCT

DIM

LPWMRT1

REF

PDRV_A

FB

CMP

PDRV_C

NDRV_D

NDRV_BR16

C11

R16 and C11 is recifier circuit, it supply stable voltage for OZ960 VDDA.

GNDA: Analog signal ground reference REF: Reference voltage output; 2.5V typical FB: CCFL current feedback signal CMP: Compensation output of the current error amplifier

The CCFL current is regulated through this error amplifier. The non-inverting reference is at 1.25V nominal.

OZ960

U2OZ960/SSOP20

1

2

3

4

5

6

18

17

16

15

14

138

7

19

9

10

12

11

20CTIMR

OVP

ENA

SST

VDDA

GNDA

CT

RT

PWRGND

LCT

DIM

LPWMRT1

REF

PDRV_A

FB

CMP

PDRV_C

NDRV_D

NDRV_B

C3

shortCN1

SM02B-BHSS-1

1

2

CR1BAV99L

3 1

2

T1

C622P,3KV

R17

C12

C13

R13

30:2200CIUH8D42

C5

2.2U,X5R,6.3V

C14

0.033U

The feedback loop is determine output current. The output current is calculated as:

( )21.25 13 lamp rmsV R Iπ

= × ×

( )1.25

0.45 13lamp rmsI

R=

×

If there is a diode on the Feedback loop. The output current is calculated as:

Va = =

( ) ( )

2145.0318.025.1

318.02145.025.1

212125.1

RVI

VRI

VRIVmV

Drms

Drms

Drmsdc

⋅+

⇒

−⋅⇒

−⋅⋅===ππ

DIM: Low-frequency PWM signal for burst-mode dimming control LCT: Triangular wave for burst-mode dimming control

Vdim

OZ960

U2OZ960/SSOP20

1

2

3

4

5

6

18

17

16

15

14

138

7

19

9

10

12

11

20CTIMR

OVP

ENA

SST

VDDA

GNDA

CT

RT

PWRGND

LCT

DIM

LPWMRT1

REF

PDRV_A

FB

CMP

PDRV_C

NDRV_D

NDRV_B

C17

R20 OZ960 integrates a burst-mode dimming function to perform a wide dimming control for the CCFL. The burst mode frequency is set by C17,

17

1490[ ][ ]

f HzC nF

=

The ramp peak of burst mode triangle is 3V and ramp valley is 1V. We can adjust Vdim to control LPWM duty cycle.

PGND: Power ground reference RT1: Resistor for programming ignition frequency RT: Timing resistor set operation frequency CT: Timing capacitor set operating frequency

Operating frequency A resistor RT and a capacitor CT determine the operating frequency of OZ960. The frequency is calculated as:

RT

RT

OZ96

0

U2OZ960/SSOP20

1

2

3

4

5

6

18

17

16

15

14

138

7

19

9

10

12

11

20CTIMR

OVP

ENA

SST

VDDA

GNDA

CT

RT

PWRGND

LCT

DIM

LPWMRT1

REF

PDRV_A

FB

CMP

PDRV_C

NDRV_D

NDRV_B

R21

R22

R

C18

R21 and C18 determine the operation frequency. The frequency is calcuated as:

4

18 21

70 10[ ][ ] [H

f kHzC pF R k

•=

• Ω]

OZ960 also provide an optional striking frequency as desired. Striking frequency When R22 is used, it is connected in parallel with R21 during the ignition period. The frequency is calcuated as:

4

S18

70 10[ ][ ] [S

f kHzC pF R k

•=

• Ω] which 21 22//SR R R=

Because operation frequency is known number, C18 and R21 are constant.

Than 4

2122 4

18 21

70 10 [ ][ ][ ] [ ] [ ] 70 10S

R kR kf kHz C pF R k

• • ΩΩ =

• • Ω − • which S Hf f>

NDR_B: NMOSFET drive output NDR_D: NMOSFET drive output PDR_A: PMOSFET drive output PDR_C: PMOSFET drive output

Vin

Vin

P-mosf et' gate

P-mosf et' gate

OZ96

0

U2OZ960/SSOP20

1

2

3

4

5

6

18

17

16

15

14

138

7

19

9

10

12

11

20CTIMR

OVP

ENA

SST

VDDA

GNDA

CT

RT

PWRGND

LCT

DIM

LPWMRT1

REF

PDRV_A

FB

CMP

PDRV_C

NDRV_D

NDRV_B

R18

R19

C15

C16

D3

D4

D3, C15, R19 is a level-shift circuit, because OZ960’ supply voltage is +5V, the output of PDR is 5V, but the PMOS is switched by Vin (>5V), so the PDR must be shifted.

How to selection the value of R and C?

The RC should be large more than T. 1. If RC >> T, the waveform will be fine.

2. If RC is not large enough, the waveform will be distortion. a. C is small.

b. R and C are small.

3. Zener diode is removed.

4. Zener diode is replacement by diode.

Transformer turn ration design

RLC

N1 N2

550

If input voltage range is from 9V~21V, we can assume max duty is 83%. And max. Duty cycle happen at input voltage 8V.

8V

-8V0.41

-0.41

Input voltage through H Bridge, We get input voltage waveform of transformer as above figure. We also assume output voltage of lamp is 550V We can get R.M.S value.

V24.782.0882.081

41.0)8(41.08 222 =×=×=×−+×

If we use transformer which TOKO BLX103B, secondary of transformer is 1500N.

19550/1500*24.7

150024.7

550

1

1

11

2

1

≅=

=→=

NN

NNN

VVo

The equation is not really exact; Actually tolerance is about 15%. So it need to fine tune, because we can not calculate transformer magnetic current and core loss.

±

3. Simulation and Analysis of OZ960 inverter Functional information

3.1 Rectifier circuit 3.2 Enable circuit 3.3 Soft-start circuit 3.4 Level shift circuit for drive the P-MOSFET’s gate 3.5 Striking time and OVP control circuit 3.6 Feedback loop 3.7 Triangle circuit 3.8 Burst-mode circuit

Functional information 3.1 Rectifier circuit

If Vin=12V Then VA=5.6V VDDA= VA – VBE =5.0V Spec. VDDA=4.7V~5.5V

Pspice Simulation:

3.2 Enable circuit R8 and C8 rectifier the noise from ON/OFF, when ENA>1.5V the IC will be turn on. C8 charge from 0 to 1.5V need 0.6ms, it is delay time from ON/OFF to H.

3.3 Soft-start circuit

Normally, a 0.47uF capacitor is connected.

3.4 Level shift circuit for drive the P-MOSFET’s gate

PSpice Simulation:

3.5 Striking time and OVP control circuit

Striking time T[second]=C9[uF]

4

4 6

6 4

4

'

' 2.8

'

12 18 2.8 4202.812

O O

O OVP D

O O

O p

CV VC C

V V V VC CV VCp nV Vp −

= ×+

= + ≅+

= ×

+= × = p

Pspice Simulation: VAMPL V5=2500V/60kHz

( )

( )

DOVP

B

B

DOVP

DOVPB

DOVPB

VVVCC

VVVCC

VVCCCV

VVCC

CV

2

2

2

2

12

21

1

21

21

1

+≅

+≅

++

=

+=+

×

3.6 Feedback loop

Pspice simulation:

( )

( )245.0

318.02

318.022 2

RVVrmsIR

VIRVout

DFB

DrmsR

⋅+

=

−⋅⋅=π

VAMPL V1=1800V/60kHz

3.7 Triangle circuit Operation frequency

7 9

700000 700000[ ] 51.3[ ][ ] [ ] 220 62H

f kHz kHzC pF R k

= = =• Ω ×

Striking frequency

9 11// 55.3700000 700000[ ] 57.5[ ]

[ ] [ ] 220 55.3

S

ST S

R R R k

f kHz kHzC pF R k

= = Ω

= = =• Ω ×

3.8 Burst-mode circuit

Brightness is negative dimming control.

12

1490 1490[ ] 219[ ][ ] 6.8L

f Hz HzC nF

= = =

1. If R2 is known, then

( )

( ) ( )

24

2 45

2 4

DD DimH DimL

adjH DimL adjL DimH

DimL

DD DimL DimL adjL

R V V VR

V V V V

R R VRR V V R V V

−=

−

=− − −

2. If R4 is known, then

( )

( ) ( )

2 4

2 45

2 4

adjH DimL adjL DimH

DD DimH DimL

DimL

DD DimL DimL adjL

V V V VR R

V V VR R VR

R V V R V V

−= •

−

=− − −

Lamp current = 3.5mA~8.0mA duty-cycle = 43%~100% VDIM = 0.9V~2.1V

4 2

4 2 5

5 2.1 5 2.1 2.1

5 0.9 0.9 0.9R R

R R R

− −+ =

−= +

5R

If R2=270K then R4=360K and R5=111.7K choose 100K 4. Measurement and Verification of OZ960 inverter 4.1 Measurement of waveform of OZ960 inverter Functional information

4.1.1 Signal waveform of ENA, CTIRM, OVP, SST, FB and CMP 4.1.2 Waveform of OZ960 pin LPWM and FB 4.1.3 Vadj vs. Striking voltage at open lamp 4.1.4 OVP loop experiment 4.1.5 Vin, Duty-cycle and lamp voltage relational

4.1.1.a OZ960 signal waveform of ENA, CTIMR, OVP, SST, FB and CMP at open lamp state when Vadj=3.4V. Vin=8.9V Vin=12V

Vin=16V Vin=19V

Vin=21V

4.1.1.b Normally OZ960 signal waveform of ENA, CTIMR, OVP, SST, FB and CMP

Vin=12V, Vadj=0V. Vin=19V, Vadj=0V.

4.1.1.c Normally OZ960 signal waveform of ENA, CTIMR, OVP, SST, FB and CMP Vin=12V, Vadj=3.4V. Vin=19V, Vadj=3.4V.

4.1.2 Waveform of OZ960 pin LPWM and FB

LPWM pin of OZ960 FB pin of OZ960

4.1.3 Vadj vs. Striking voltage at open lamp condition I. Vin=8.9V

1.Vadj=0V 2. Vadj=3.4V

II. Vin=12V

1.Vadj=0V 2. Vadj=3.4V

III. Vin=16V

1.Vadj=0V 2. Vadj=3.4V

IV. Vin=21V

1.Vadj=0V 2. Vadj=3.4V

Striking voltage waveform fix Vadj=3.4V

1. Vin=8.9V 2. Vin=12V

3. Vin=16V 4. Vin=21V

4.1.4 OVP loop experiment

a. Change C6 from 33nF to 22nF C5=22pF, C6=22nF

( ) ( ) PPDOVPO VppnVV

CCCV −=×+×

+=+×

+= 30035.022

2222222

5

56

Vin=12V

b. Change C5 from 22pF to 33pF C5=33pF, C6=33nF

( ) ( ) PPDOVPO VppnVV

CCCV −=×+×

+=+×

+= 30035.022

3333332

5

56

Vin=12V

c. Change C5 from 22pF to 27pF C5=27pF, C6=33nF

( ) ( ) PPDOVPO VppnVV

CCCV −=×+×

+=+×

+= 36705.022

2727332

5

56

Vin=12V

d. Change C5 from 22pF to 18pF C5=18pF, C6=33nF

( ) ( ) PPDOVPO VppnVV

CCCV −=×+×

+=+×

+= 55035.022

1818332

5

56

Vin=12V

4.1.5 Vin, Duty-cycle and lamp voltage relational Vin=8.9V, Duty-cycle=54.8%

Vin=12V, Duty cycle=36.9%

Vin=16V, Duty cycle=26.2%

Vin=21V, Duty cycle=21.4%

Vin (V) Frequency (kHz) Duty cycle(%) Vlamp (kVp-p) Vlamp (Vrms)

9 56.6 54.8 1.26 401 12 57.5 36.9 1.32 407 16 57.1 26.2 1.38 413 21 57.1 21.4 1.4 418

4.2 Functional test of OZ960 inverter Conditions:

Inverter: IV10101/T Ambient temperature: 24°C Panel: LG 14.1” TFT XGA, model: LP141XA-D1AP Scope: Tektronix TDS 220, S/N: A1004 Power supply: GW GPC-3030D, S/N: A1011 LCR meter: Zentech 100 LCR METER Multi-meter: HP 34401A, S/N: A1001 Thermal tester: OPTEX PT-3S, S/N: A1010

Test Item: 4.2.1 Vdim vs. Ilamp 4.2.2 Vcc vs. Ilamp 4.2.3 Operation frequency vs. Ilamp 4.2.4 Burst frequency vs. Ilamp 4.2.5 Relationship between Vlamp and FB signal Test result: 4.2.1Vdim vs. Ilamp

Condition: Vcc=12V, fH=57.4KHz, fBurst=150Hz Vdim(V) Iin(A) Ilamp(mA)

4.0 0.37 5.60 2.0 0.22 4.01 0.1 0.08 2.11

4.2.2 Vcc vs. Ilamp Condition: Vdim=4.0V, fH=57.4KHz

Vcc(V) Iin(A) Ilamp(mA) 9 0.50 5.56 12 0.37 5.61 16 0.27 5.62 19 0.23 5.62

Condition: Vdim=2.0V, fH=57.4KHz

Vcc(V) DutyVlamp (%) t1/T(%) Iin(A) DutyLPWM (%) Ilamp(mA) 9 70.46 58.47 0.28 30.26 4.02 12 68.37 59.67 0.21 30.26 4.14 16 68.07 61.77 0.16 30.26 4.25 19 66.57 62.37 0.14 30.26 4.28

*t1: Vlamp except rise and fall time.

Vcc=9V Vadj=2.0V Vcc=12V Vadj=2.0V

Vcc=16V Vadj=2.0V Vcc=19V Vadj=2.0V Condition: Vdim=0.1V, fH=57.4KHz

Vcc(V) DutyVlamp (%) t1/T(%) Iin(A) DutyLPWM (%) Ilamp(mA) 9 32.08 20.69 0.09 69.2 2.03 12 29.09 21.29 0.08 69.1 2.28 16 26.99 21.60 0.06 68.9 2.42 19 26.09 22.19 0.05 68.7 2.47

*t1: Vlamp except rise and fall time.

Vcc=9V Vadj=0.1V Vcc=12V Vadj=0.1V

Vcc=16V Vadj=0.1V Vcc=19V Vadj=0.1V 4.2.3 Operation frequency vs. Ilamp Condition: Vdim=4.0V, Vcc=12V

fH (KKz) RT(KΩ) Iin(A) Ilamp(mA) Tr.Duty(%) 37.3 82 0.35 8.54 - 49.5 62 0.36 5.65 54.45 57.4 53.6 0.36 5.62 45.24 65.15 47 0.38 5.60 41.69

* There is an unstable output current, when frequency at 37.3kHz. 4.2.4 Burst frequency vs. Ilamp Condition: Vcc=12V, Vdim=2.0V fBurst (Hz) CLCT(nF) DutyVlamp (%) t1/T(%) Iin(A) DutyLPWM (%) Ilamp(mA)

150 10 68.37 59.67 0.22 30.26 4.12 224 6.8 66.98 54.34 0.20 30.45 3.86 307 4.7 68.10 51.07 0.19 33.54 3.36

fBrust=150Hz fBrust=224Hz

fBrust=307Hz Condition: Vcc=12V, Vdim=0.1V fBurst (Hz) CLCT(nF

) DutyVlamp (%) t1/T(%) Iin(A) DutyLPWM (%) Ilamp(mA)

150 10 30.12 20.99 0.08 68.98 2.21 224 6.8 29.12 18.37 0.06 69.09 1.71 307 4.7 27.36 11.55 0.03 69.72 0.51

fBrust=150Hz fBrust=224Hz

fBrust=307Hz

4.2.5 Relationship between Vlamp and FB signal a. (fLPWM=150Hz, T=6.67ms), Vadj=1.5V Vin(V) Rise(us) Fall(us) D(t1/T)(%) Vp-p(kV)

9 320 520 48.58 1.90 12 240 340 50.07 1.92 16 160 240 51.27 1.92 19 140 200 50.67 1.94

Vin=9V Vin=12V

Vin=16V Vin=19V

b. Vin=12V, Vadj=1.5V, (fLPWM=150Hz, T=6.67ms) R13(KΩ) Rise(us) Fall(us) D(t1/T)(%) Vp-p(kV)

13 200 80 47.08 1.91 33 240 340 50.07 1.92 47 270 1320 55.62 1.91

R13=13KΩ R13=33KΩ

R13=47KΩ

c. Vin=12V, Vadj=1.5V, (fLPWM=150Hz, T=6.67ms) R15(KΩ) Rise(us) Fall(us) D(t1/T)(%) Vp-p(kV)

33 170 1720 58.62 1.91 51 240 340 50.07 1.92 75 340 240 42.28 1.91

R15=33KΩ R15=51KΩ

R15=75KΩ d. Vin=12V, Vadj=1.5V R13(KΩ) R15(KΩ) Rise(us) Fall(us) D(t1/T)(%) Vp-p(kV)

47 75 380 440 44.68 1.9 21 33 180 200 53.67 1.9

R13=47KΩ R13=21KΩ

R15=75KΩ R15=33KΩ 4.3 Transformer turn rate Input voltage range is 9V to 21V, we assume max. duty cycle is 84%. And max. duty cycle happen at input voltage 8V. The output voltage of lamp is 450Vrms. We can get the R.M.S. value.

( ) V33.784.081

42.0842.08 222

=×=×−+×

If the secondary turns of transformer is 2200.

3511

220033.7

45012

1≅⇒

=⇒=

NNN

NVVo

Actually tolerance is about ±15%. Actually test, 1. N1:N2=30:2200 2. If the input voltage is lower than 8.9V inverter can’t turn on. 3. When inverter is normally work then start decrease input voltage, it will shut-down

while input voltage is 8.4V and the duty cycle is 80%.

Conclusion O2 (OZ960) TI1451 Remark Switching topology

PWM: Zero-Voltage-Swit

ching (ZVS)

Royer: Self Exciting

O2: PWM-ZVS is controlled by O2 chip. ( quite stable). TI1451: Oscillation frequency is controlled by transformer.

Output-Waveform

Very Good Medium O2: ZVS-Phase-Shift Control, Output waveform is almost sine and symmetry is very good. TI1451: Waveform is most likely as triangle.

Operating Frequency

Constant- Frequency(Easy

to control)

Variable –Frequency (Not easy to

control).

O2: Designer can easy to decide the optimized operation frequency for panels. TI1451: Operating frequency is decided by oscillated capacitor, primary inductance of transformer, and the equivalent load from the load of secondary side of transformer. The operating frequency is not easy to design and operating frequency is easy to change when panel dimming is changed.

Working with transformer

Very Good Good O2: Transformer uses two windings. Transformer easy to manufacture. TI1451: Transformer needs four windings. Transformer is more complicated.

Efficiency > 85% ~=75% O2: O2's topology is single stage. TI1451: TI1451 topology is two stages.

Open-lamp and short protection

Yes No O2: Open-lamp and short protection functions are integrated in Chip. TI1415: Need to add extra circuit to do these protections

Thermal issue

No Yes O2: The temperature of transformer and MOSFET's is low because O2 inverter has higher efficiency. TI1451: TI1451 topology causes many components with higher thermal, which are transformer, oscillated capacitor, MOSFET and choke.

Brightness efficiency

Very Good Medium O2: Output current is sine waveform.

Burst-Mode Function

Yes No O2: Burst mode function is built in IC. And transformer is without noise when inverter works under burst-mode. TI1451: Need add extra circuit to implement the function. Transformer has noise when inverter works under burst-mode.

Pspice Circuit OVP

Power stage

Secondary of transformer