1/2.74” 32megapixel-prototype cmos image sensor with 0
TRANSCRIPT
7.9: 1/2.74-inch 32Mpixel Prototype CMOS Image Sensor with 0.64μm Unit Pixels Separated by Full-Depth Deep-Trench Isolation© IEEE 2021 International Solid-State Circuits Conference 1 of 18
1/2.74” 32Megapixel-Prototype CMOS Image Sensor with 0.64μm Unit Pixels Separated
by Full-Depth Deep-Trench IsolationJongeun Park, Sungbong Park, Kwansik Cho, Taehun Lee, Changkyu Lee, DongHyun Kim, Beomsuk Lee, SungIn Kim, Ho-Chul Ji, DongMo Im, Haeyong Park, Jinyoung Kim, JungHo Cha, Taehoon Kim, In-Sung Joe, Soojin Hong, Chongkwang Chang, Jingyun Kim, WooGwan Shim, Taehee Kim, Jamie Lee, Donghyuk Park, EuiYeol Kim, Howoo Park, Jaekyu Lee, Yitae Kim, JungChak Ahn, YoungKi Hong, ChungSam Jun, HyunChul Kim, Chang-Rok Moon, Ho-Kyu Kang
Samsung Electronics, Hwaseong, Korea
7.9: 1/2.74-inch 32Mpixel Prototype CMOS Image Sensor with 0.64μm Unit Pixels Separated by Full-Depth Deep-Trench Isolation© IEEE 2021 International Solid-State Circuits Conference 2 of 18
Self Introduction
Sungbong Park B.S. & M.S. from Seoul National University, Seoul, Korea Ph.D. from University of Tokyo, Tokyo, Japan, in 2008 Was with NTT, APIC, Finisar, 2009-2014 Was with Intel, Santa Clara, CA, USA, 2014-2019 Have been with Samsung since 2019 My interests are CIS APS design, Silicon Photonics,…
7.9: 1/2.74-inch 32Mpixel Prototype CMOS Image Sensor with 0.64μm Unit Pixels Separated by Full-Depth Deep-Trench Isolation© IEEE 2021 International Solid-State Circuits Conference 3 of 18
Outline Motivation: Pixel Shrink 0.64μm-pixel Image Sensors Pixel Design Challenges and Solutions Keeping FWC Node isolation In-pixel SF scaling
Performance Summary
7.9: 1/2.74-inch 32Mpixel Prototype CMOS Image Sensor with 0.64μm Unit Pixels Separated by Full-Depth Deep-Trench Isolation© IEEE 2021 International Solid-State Circuits Conference 4 of 18
Outline Motivation: Pixel Shrink 0.64μm-pixel Image Sensors Pixel Design Challenges and Solutions Keeping FWC Node isolation In-pixel SF scaling
Performance Summary
7.9: 1/2.74-inch 32Mpixel Prototype CMOS Image Sensor with 0.64μm Unit Pixels Separated by Full-Depth Deep-Trench Isolation© IEEE 2021 International Solid-State Circuits Conference 5 of 18
Pixel Shrink High resolution, more and smaller cameras
0
1
2
3
Year05 10 15 20 25
0
1
2
3
Pixe
l Pitc
h [μ
m]
# of
Pix
els
[Mp]
< 0.7μm> 100Mp
7.9: 1/2.74-inch 32Mpixel Prototype CMOS Image Sensor with 0.64μm Unit Pixels Separated by Full-Depth Deep-Trench Isolation© IEEE 2021 International Solid-State Circuits Conference 6 of 18
Challenges
Pixel pitch [µm]0.9 0.8 0.7 0.64
Effe
ctiv
e Vo
l. Si
PD
100%
79%65%
52%
6000e-
4800e-
FWC
ISSCC’20 ISSCC’18 IEDM’19
① Maintaining FWC ② Node isolation ③ In-pixel Tr scaling
7.9: 1/2.74-inch 32Mpixel Prototype CMOS Image Sensor with 0.64μm Unit Pixels Separated by Full-Depth Deep-Trench Isolation© IEEE 2021 International Solid-State Circuits Conference 7 of 18
Outline Motivation: Pixel Shrink 0.64μm-pixel Image Sensors Pixel Design Challenges and Solutions Keeping FWC Node isolation In-pixel SF scaling
Performance Summary
7.9: 1/2.74-inch 32Mpixel Prototype CMOS Image Sensor with 0.64μm Unit Pixels Separated by Full-Depth Deep-Trench Isolation© IEEE 2021 International Solid-State Circuits Conference 8 of 18
0.64μm Pixel Sensor Stacked CIS w/ full-depth DTI & Vertical TG 32Mp-prototype w/ tetra-binning & DCG
DCG: Dual Conversion Gain
μ-Lens
Color Filters
FDTI
Si P
D
STI In-pixel Tr
x2
7.9: 1/2.74-inch 32Mpixel Prototype CMOS Image Sensor with 0.64μm Unit Pixels Separated by Full-Depth Deep-Trench Isolation© IEEE 2021 International Solid-State Circuits Conference 9 of 18
Outline Motivation: Pixel Shrink 0.64μm-pixel Image Sensors Pixel Design Challenges and Solutions Keeping FWC Node isolation In-pixel SF scaling
Performance Summary
7.9: 1/2.74-inch 32Mpixel Prototype CMOS Image Sensor with 0.64μm Unit Pixels Separated by Full-Depth Deep-Trench Isolation© IEEE 2021 International Solid-State Circuits Conference 10 of 18
Depth
Pote
ntia
l
① Φ▲:
② Vol.▲ TG Low
TG High
ⓐ FWC
STIVTG
n-Si▲
FDTIp-
Poly
①
②
FWC > 6000 e- PD volume ▲ & Potential ▲
7.9: 1/2.74-inch 32Mpixel Prototype CMOS Image Sensor with 0.64μm Unit Pixels Separated by Full-Depth Deep-Trench Isolation© IEEE 2021 International Solid-State Circuits Conference 11 of 18
ⓐ FWC
Dopingconc.
4800e-
0.64μm0.7μm
6000e-
6000e-
FWC > 6000 e- PD volume ▲ & Potential ▲
4800e-
6000e-
Depth
Pote
ntia
l
TG Low
TG High
7.9: 1/2.74-inch 32Mpixel Prototype CMOS Image Sensor with 0.64μm Unit Pixels Separated by Full-Depth Deep-Trench Isolation© IEEE 2021 International Solid-State Circuits Conference 12 of 18
ⓑ Node Isolation
0.37V
0.19V
0.4V
0.64μm0.7μm
x3x1x1 Surface p-Si conc.
Pote
ntia
l Bar
rier
VDD
RGTG
FD
LKG Path
VDD-FD LKG (DIBL) ΔFWC for tetra pixels
Too much p-Si Signal loss at low light
p-well
RG Drain
FDTG Drain
VDD
eee
VDD
VFDΦB
ee
p-Si
7.9: 1/2.74-inch 32Mpixel Prototype CMOS Image Sensor with 0.64μm Unit Pixels Separated by Full-Depth Deep-Trench Isolation© IEEE 2021 International Solid-State Circuits Conference 13 of 18
ⓑ Node Isolation
p-well
RG Drain
FDTG Drain
VDDee STI
Using STI, instead
VDD
RGTG
FD
LKG Path
VDD-FD LKG (DIBL) ΔFWC for tetra pixels
Too much p-Si Signal loss at low light
p-well
RG Drain
FDTG Drain
VDD
eee
VDD
VFDΦB
ee
p-Si
7.9: 1/2.74-inch 32Mpixel Prototype CMOS Image Sensor with 0.64μm Unit Pixels Separated by Full-Depth Deep-Trench Isolation© IEEE 2021 International Solid-State Circuits Conference 14 of 18
ⓒ In-pixel SF Scaling
RTS signal ~ W·LTOX
p-welln+n+
L
W
SiO2
TOX
# Pi
xels
, log
ΔOutput [a.u.]0
Area [ppm]
Better RTS
SF scale-down Worse Temporal noise, RTS, Linearity
7.9: 1/2.74-inch 32Mpixel Prototype CMOS Image Sensor with 0.64μm Unit Pixels Separated by Full-Depth Deep-Trench Isolation© IEEE 2021 International Solid-State Circuits Conference 15 of 18
ⓒ In-pixel SF Scaling
Tox▼ Tox & SP W ▼
SF area 38% ▼
3
0.64μm0.7μm
RTS
Pix
el [p
pm]
18
9
4
SF area 17% ▲
RTS improved by reducing Tox and Spacer Width
14%17%
7.9: 1/2.74-inch 32Mpixel Prototype CMOS Image Sensor with 0.64μm Unit Pixels Separated by Full-Depth Deep-Trench Isolation© IEEE 2021 International Solid-State Circuits Conference 16 of 18
PerformanceItems 0.7μm 0.64μm
FWC [e-] 6,000 6,000
Dark current [e-/s] @ 60°C 1.3 1.1
White pixels [ppm] 10 15
Temporal noise[e-rms] 1.4 1.4
RTS pixels[ppm] 3 4
Y-SNR[dB] 31.7 30.7
0.7μm
0.64μm
7.9: 1/2.74-inch 32Mpixel Prototype CMOS Image Sensor with 0.64μm Unit Pixels Separated by Full-Depth Deep-Trench Isolation© IEEE 2021 International Solid-State Circuits Conference 17 of 18
Outline Motivation: Pixel Shrink 0.64μm-pixel Image Sensors Pixel Design Challenges and Solutions Keeping FWC Node isolation In-pixel SF scaling
Performance Summary
7.9: 1/2.74-inch 32Mpixel Prototype CMOS Image Sensor with 0.64μm Unit Pixels Separated by Full-Depth Deep-Trench Isolation© IEEE 2021 International Solid-State Circuits Conference 18 of 18
Summary Production-ready 0.64μm-pixel CIS FWC > 6000e- by PD volume and potential ▲ VDD-FD node isolated by STI In-pixel SF scaling with Tox ▼ and W·L ▲
Demand for more (=smaller) pixels.Pixel shrink must continue.