2 vhdl complete outputs

8/13/2019 2 VHDL Complete Outputs

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1) Half Adder Simulation By Data Flow Modelling


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2) Full Adder Simulation By Data Flow Modelling


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3) (a) Half Subractor Simulation By Data Flow Modelling


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3) (b) Full Subtractor Simulation By Data Flow Modelling


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4) BD to Decimal Decoder Simulation By Data Flow Modelling


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!) Binary to "ray ode on#erter Simulation By Data Flow

Modelling


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$) "ray to Binary ode on#erter Simulation By Data Flow

Modelling


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%) BD to &'ce3 ode on#erter Simulation By Data Flow

Modelling


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) 4'1 Multi*le'er Simulation uing +f,ele-ae tatement


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.) 2'4 Decoder Simulation By Data Flow Modelling


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1/) 2 Bit Multi*lier Simulation By Data Flow Modelling


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11) 2 Bit om*arator Simulation By Data Flow Modelling


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12) Half Adder Simulation by Structural Modelling


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1!) 4'1 Multi*le'er Simulation By Data Flow Modelling


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1$) 2'4 Decoder By Be0a#ioral Modelling


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1. VHDL Code For Half Adder By Data Flow Modelling

library ieee

ue ieeetdlogic11$4all

entity 0alfadder i

*ort(ab5 in bitc5 out bit)

end 0alfadder

arc0itecture 0alfadder of 0alfadder i

begin

67(a 'or b)

c67(a and b)

end 0alfadder


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3. (a) VHDL Code For Half Sutra!tor By Data Flow Modelling

library ieee


entity 0alfubtractor i

*ort(ab5 in bit differenceborrow5 out bit)

end 0alfubtrator

arc0itecture 0alfubtractordfm of ubtractor i

begin

difference67(a 'or b)

borrow67((not a) and b)

end 0alfubtractordfm


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3. () VHDL Code For Full Sutra!tor By Data Flow Modelling

library ieee


entity fullubtractor i

*ort(ab*re#iouborrow5 in bit

differencene'tborrow5 out bit)

end fullubtractor

arc0itecture fullubtractordfm of fullubtractor i

begin

difference67((a 'or b) or (b 'or *re#iouborrow) or (a 'or *re#iouborrow))

ne'tborrow67(((not a) and (b or *re#iouborrow)) or (b and *re#iouborrow))end fullubtractordfm


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". VHDL Code For BCD #o De!i$al De!oder By Data Flow

Modelling

library ieee


entity bcdtodecimal i

*ort(abcd5 in bit e5 out bit#ector(/ to .))

end bcdtodecimal

arc0itecture bcdtodecimaldfm of bcdtodecimal i

begin

e(/)67((((not a) and (not b)) and (not c)) and (not d))

e(1)67((((not a) and (not b)) and (not c)) and d)e(2)67(((not b) and c) and (not d))

e(3)67(((not b) and c) and d)

e(4)67((b and (not c)) and (not d))

e(!)67((b and (not c)) and d)

e($)67((b and c) and (not d))

e(%)67((b and c) and d)

e()67(a and (not d))

e(.)67(a and d)

end bcdtodecimaldfm


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%. VHDL Code For Binary to &ray Code Con'erter By Data Flow

Modelling

library ieee


entity binarytogray i

*ort(b/b1b2b35 in bitg/g1g2g35 out bit)

end binarytogray

arc0itecture btg of binarytogray i

begin

g367b3

g267b3 'or b2g167b2 'or b1

g/67b1 'or b/

end btg


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. VHDL Code For &ray to Binary Code Con'erter By Data Flow

Modelling

library ieee


entity graytobinary i

*ort(g/g1g2g35 in bitb/b1b2b35 out bit)

end graytobinary

arc0itecture gtb of graytobinary i

begin

b367g3

b267g3 'or g2b167(g3 'or (g2 'or g1))

b/67(g3 'or (g2 'or (g1 'or g/)))

end


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. VHDL Code For BCD #o *+!e,,3 Code Con'erter By Data

Flow Modelling

library ieee


entity bcdtoe'ce3 i

*ort(b/b1b2b35 in bit e/e1e2e35 out bit)

end bcdtoe'ce3

arc0itecture bcdtoe'ce3dfm of bcdtoe'ce3 i

begin

e367((b3 or (b2 and b/)) or (b2 and b1))

e267(((not b2) and b/) or ((not b/) and (b1 'or b2)))e167(b1 'nor b/)

e/67(not b/)

end bcdtoe'ce3dfm


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-. (a) VHDL Code For "1 Multi/le+er 0,ing F*LS*

State$ent,

library ieee


entity mu'41 i

*ort(5 in bit#ector(/ to 1) d5 in bit#ector(/ to 3) y5 out bit)

end mu'41

arc0itecture mu'41be0a#iouralifele of mu'41 i

begin

*roce(d)

beginif 78//8 t0en

y67d(/)

elif 78/18 t0en

y67d(1)

elif 781/8 t0en

y67d(2)

ele

y67d(3)

end ifend *roce

end mu'41be0a#iouralifele


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-. () VHDL Code For "1 Multi/le+er 0,ing CAS* State$ent,

library ieee


entity mu'41 i

*ort(5 in bit#ector(/ to 1) d5 in bit#ector(/ to 3) y5 out bit)

end mu'41

arc0itecture mu'41be0a#iouralcae of mu'41 i

begin

*roce(d)

begin

cae iw0en 8//8 79 y67d(/)

w0en 8/18 79 y67d(1)

w0en 81/8 79 y67d(2)

w0en ot0er 79 y67d(3)

end cae

end *roce

end mu'41be0a#iouralcae


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14. VHDL Code For 2 Bit Multi/lier By Data Flow Modelling

library ieee


entity multi*lier2bit i

*ort(a5 in bit#ector(1 downto /)b5 in bit#ector(1 downto /)

d5 out bit#ector(3 downto /))

end multi*lier2bit

arc0itecture multi*lier2bitdfm of multi*lier2bit i

ignal c5 bit

begin

d(/)67(a(/) and b(/))d(1)67((a(1) and b(/)) 'or (a(/) and b(1)))

c67((a(1) and b(/)) and (a(/) and b(1)))

d(2)67((a(1) and b(1)) 'or c)

d(3)67((a(1) and b(1)) and c)

end multi*lier2bitdfm


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11. VHDL Code For 2 Bit Co$/arator By Data Flow Modelling

library ieee


entity com*arator2bit i

*ort(ab5 in bit#ector(1 downto /) y5 out bit#ector(2 downto /))

end com*arator2bit

arc0itecture com*arator2bitdfm of com*arator2bit i

begin

y(/)67 (((a(1) and (not b(1))) or (a(1) and a(/) and (not b(/)))) or ((not b(1)) and a(/)

and (not b(/))))

y(1)67 ((((not a(1)) and b(1)) or ((not a(1)) and (not a(/)) and b(/))) or (b(1) and (nota(/)) and a(/)))

y(2)67 ((a(1) 'nor b(1)) and (a(/) 'nor b(/)))

end com*arator2bitdfm


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12. VHDL Code For Half Adder y Stru!tural Modelling

library ieee


entity 0alfadder i

*ort(ab5 in bit umcarry5 out bit)

end 0alfadder

arc0itecture 0alfaddertruct of 0alfadder i

com*onent 'or1 i

*ort(*:5 in bit r5 out bit)

end com*onent

com*onent and1 i

*ort(u#5 in bit w5 out bit)end com*onent

begin

'15'or1 *ort ma*(abum)

'25and1 *ort ma*(abcarry)

end 0alfaddertruct

entity 'or1 i

*ort(*:5 in bit r5 out bit)

end 'or1

arc0itecture 'or1dfm of 'or1 i

begin

r67* 'or :

end 'or1

entity and1 i

*ort(u#5 in bit w5 out bit)

end and1

arc0itecture and1dfm of and1 i

begin

w67u and #

end and1


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2 vhdl complete outputs

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