2009-06-04:【技術專題】right-half-plane (rhp)...

13
1 課程講義:【電力電子】 DC-DC Converter - Modeling Techniques 交通大學 808-電力電子實驗室 June 4, 2009 台灣新竹交通大學電機與控制工程研究所808實驗室 電源系統與晶片、數位電源、馬達控制驅動晶片、DSP/FPGA控制 http://pemclab.cn.nctu.edu.tw/ Lab-808: Power Electronic Systems & Chips Lab., NCTU, Taiwan 1/26 200964鄒應嶼 教授 國立交通大學 電機與控制工程研究所 Right-Half-Plane (RHP) Zero LAB808 NCTU Lab808: 電力電子系統與晶片實驗室 Power Electronic Systems & Chips, NCTU, TAIWAN 台灣新竹交通大學電機與控制工程研究所 台灣新竹交通大學電機與控制工程研究所808實驗室 電力電子系統晶片、數位電源、DSP控制、馬達與伺服控制 http://pemclab.cn.nctu.edu.tw/ Lab-808: Power Electronic Systems & Chips Lab., NCTU, Taiwan 2/26 Zero in the Boost and Buck/Boost Converters (CCM) Boost () () ( )( ( )) ( ) ' ' v s ds V D r Cs sL DR s Q s o i C o o 2 2 2 1 1 1 1 C r D C r R D L D Q LC D C L o o 1 L C D v o v i Buck/Boost L C D v o v i () () ( )( ( )) ( ) ' ' v s ds V D r Cs sDL DR s Q s o i C o o 2 2 2 1 1 1 1 C D r D r R D L D Q LC D L C o o ) ) ( ( ) ( 1 2 2 Why the RHP zero will occur? Where is the RHP zero? What is the effect of the RHP zero? Can the RHP zero be eliminated?

Upload: others

Post on 09-Oct-2020

3 views

Category:

Documents


0 download

TRANSCRIPT

  • 1

    課程講義:【電力電子】 DC-DC Converter - Modeling Techniques交通大學 808-電力電子實驗室 June 4, 2009

    台灣新竹‧交通大學‧電機與控制工程研究所‧808實驗室電源系統與晶片、數位電源、馬達控制驅動晶片、DSP/FPGA控制

    http://pemclab.cn.nctu.edu.tw/Lab-808: Power Electronic Systems & Chips Lab., NCTU, Taiwan

    1/26

    2009年6月4日

    鄒 應 嶼 教 授

    國立交通大學 電機與控制工程研究所

    Right-Half-Plane (RHP) Zero

    LAB808NCTU

    Lab808: 電力電子系統與晶片實驗室Power Electronic Systems & Chips, NCTU, TAIWAN

    台灣新竹•交通大學•電機與控制工程研究所

    台灣新竹‧交通大學‧電機與控制工程研究所‧808實驗室電力電子系統晶片、數位電源、DSP控制、馬達與伺服控制

    http://pemclab.cn.nctu.edu.tw/Lab-808: Power Electronic Systems & Chips Lab., NCTU, Taiwan

    2/26

    Zero in the Boost and Buck/Boost Converters (CCM)

    • Boost

    ( )( )

    ( )( ( ))

    ( )'

    'v sd s

    VD

    r Cs sL D Rs

    Qs

    o i C

    o o

    2

    2

    2

    1 11 1

    Cr

    DCr

    RDL

    DQ

    LCD

    CLo

    o

    1

    L

    C

    D

    vovi

    • Buck/Boost

    L C

    D

    vovi ( )( )

    ( )( ( ))

    ( )'

    'v sd s

    VD

    r Cs sDL D Rs

    Qs

    o i C

    o o

    2

    2

    2

    1 11 1

    C

    Dr

    Dr

    RDL

    DQ

    LCD

    LCo

    o

    ))(

    ()(

    1

    2 2

    Why the RHP zero will occur? Where is the RHP zero? What is the effect of the RHP zero? Can the RHP zero be eliminated?

  • 2

    課程講義:【電力電子】 DC-DC Converter - Modeling Techniques交通大學 808-電力電子實驗室 June 4, 2009

    台灣新竹‧交通大學‧電機與控制工程研究所‧808實驗室電源系統與晶片、數位電源、馬達控制驅動晶片、DSP/FPGA控制

    http://pemclab.cn.nctu.edu.tw/Lab-808: Power Electronic Systems & Chips Lab., NCTU, Taiwan

    3/26

    Right-Half-Plane (RHP) Zero

    A Mathematical Introduction to Control Theory, Shlomo Engelber, Imperial College Press,pp. 147, The Effect of Zeros in the Right Half-Plane

    Understanding the Right-Half-Plane Zero, May 1, 2009 12:00 PMCHRISTOPHE BASSO, Director, Product Application Engineering, ON Semiconductor, Phoenix

    Tricks of the Trade - understanding the right-half-plane zero in small-signal DC-DC converter models, IEEE Power Electronics Society NEWSLETTER, January 2001.

    Right-Half-Plane Zero (of DC-DC Converters) - A simplified explanation, Lloyd Dixon, 1984, (slup084)

    4/26

    RHP Zero of Boost and Buck-Boost Converters

    Right-Half-Plane Zero - A simplified explanation, Lloyd Dixon, 1984, (slup084)

    Switchmode power supply handbookKeith H. Billings

    Incremental changes in duty ratio.

    L C

    D

    voviIO

    IL

    DFlyback Circuit, Continuous Inductor Current Mode

    IO

    IL

  • 3

    課程講義:【電力電子】 DC-DC Converter - Modeling Techniques交通大學 808-電力電子實驗室 June 4, 2009

    台灣新竹‧交通大學‧電機與控制工程研究所‧808實驗室電源系統與晶片、數位電源、馬達控制驅動晶片、DSP/FPGA控制

    http://pemclab.cn.nctu.edu.tw/Lab-808: Power Electronic Systems & Chips Lab., NCTU, Taiwan

    Right-Half-Plane (RHP) Zero

    Frequency response of RHP zero in voltage-mode control

    Frequency response of RHP zero in current-mode control

    The RHP zero is still present with current mode control!

    OOiOiL VDVVDVDVV )()1(

    dVVDVdVVV OiOOiL ˆ)()1(ˆˆ)(ˆ

    dIdLVjdId

    LDVVji LiLOiO ˆˆˆˆ

    )1)((

    )()1()1( 22

    OiO

    iOO

    O

    iOz VVVL

    VRDLDR

    VLDVR

    LOi

    LL

    Oi

    iL

    Oi

    LLO iVV

    ILjiVVVi

    VVILjDii ˆ

    )(ˆ

    )(ˆ

    )()1(ˆˆ

    fz

    40

    20

    0

    -20

    -40

    dio ˆˆ

    (dB)

    1 10 100 1K 10K 100(Hz)

    0

    -90

    -180

    dio ˆˆ(Deg)

    fz

    40

    20

    0

    -20

    -40

    Lo ii ˆˆ

    (dB)

    1 10 100 1K 10K 100

    0

    -90

    -180

    Lo ii ˆˆ(Deg)

    6/26

    RHP Zero of CCM Buck-Boost (Flyback) Converter

    L

    iO ILs

    Vdi

    ˆ

    DLDR

    LIV OL

    iz

    2

    2)1(

    • Buck/Boost

    L C

    D

    vovi ( )( )

    ( )( ( ))

    ( )'

    'v sd s

    VD

    r Cs sDL D Rs

    Qs

    o i C

    o o

    2

    2

    2

    1 11 1

    C

    Dr

    Dr

    RDL

    DQ

    LCD

    LCo

    o

    ))(

    ()(

    1

    2 2

    1P

    2P

    CrCz

    11

    xRQ

    20

    0

    xR

  • 4

    課程講義:【電力電子】 DC-DC Converter - Modeling Techniques交通大學 808-電力電子實驗室 June 4, 2009

    台灣新竹‧交通大學‧電機與控制工程研究所‧808實驗室電源系統與晶片、數位電源、馬達控制驅動晶片、DSP/FPGA控制

    http://pemclab.cn.nctu.edu.tw/Lab-808: Power Electronic Systems & Chips Lab., NCTU, Taiwan

    7/26

    RHP Zero of CCM Boost Converter

    The effect of any control action during the ON time is delayed until the switch is turned FF.

    Output response is initially in the opposite direction of the desired correction.

    Brian Lynch, Under the Hood of a DC-DC Boost Converter, 2008-09 Power Supply Design Seminar - SEM1800.

    RHP Zero

    L

    C

    D

    vovi R

    8/26

    Compensation of RHP Zero

    REF: LM5000 High Voltage Switch Mode Regulator

    A current mode control boost regulator has an inherent right half plane zero (RHP zero). This zero has the effect of a zero in the gain plot, causing an imposed +20dB/decade on the rolloff, but has the effect of a pole in the phase, subtracting another 90° in the phase plot. This can cause undesirable effects if the control loop is influenced by this zero. To ensure the RHP zero does not cause instability issues, the control loop should be designed to have a bandwidth of ½ the frequency of the RHP zero or less. This zero occurs at a frequency of:

    where ILOAD is the maximum load current.

    Hz) (inRFPzeroLOAD

    OUT

    LIDV

    2)( 2'

  • 5

    課程講義:【電力電子】 DC-DC Converter - Modeling Techniques交通大學 808-電力電子實驗室 June 4, 2009

    台灣新竹‧交通大學‧電機與控制工程研究所‧808實驗室電源系統與晶片、數位電源、馬達控制驅動晶片、DSP/FPGA控制

    http://pemclab.cn.nctu.edu.tw/Lab-808: Power Electronic Systems & Chips Lab., NCTU, Taiwan

    Compensation of OP-Amp uA741

    Kent H. Lundberg, "Internal and External Op-Amp Compensation: A Control-Centric Tutorial," American Control Conference, 2004.

    Complete Fairchild µA741 schematic. The primary signal path is comprised of two gain stages. The first gain stage is a differential pair with active load (transistors Q1–Q6). The second gain stage is a common-emitter amplifier (transistors Q16and Q17). The output buffer is a push-pull emitter follower (transistors Q14, Q20, and Q22).

    Compensation for OP-AMP

    (a) Simplified schematic of the uncompensated Fairchild µA741 op amp. (b) Simplified schematic of the Fairchild µA741 op amp with compensation capacitor.

    (d) Frequency response of uncompensated and compensated op amp. The two low-frequency poles in the uncompensated transfer function severely degrade the phase margin at crossover.

    (d) Equivalent circuit of uncompensated and compensated OP-Amp.

    A1 A2 1

    C

    Vin V0

    A1 A2 1Vin V0

    Compensated

  • 6

    課程講義:【電力電子】 DC-DC Converter - Modeling Techniques交通大學 808-電力電子實驗室 June 4, 2009

    台灣新竹‧交通大學‧電機與控制工程研究所‧808實驗室電源系統與晶片、數位電源、馬達控制驅動晶片、DSP/FPGA控制

    http://pemclab.cn.nctu.edu.tw/Lab-808: Power Electronic Systems & Chips Lab., NCTU, Taiwan

    RHP Zero of a Common-Emitter Amp

    (a) Common-emitter amp. (b) Equivalent circuit

    2121212

    21212211

    21

    )]([)]([1)(

    RRCCCCCsRRRRgCRCRCsRRgsC

    IV

    fmf

    mf

    i

    o

    There is a RHP Zero located at f

    m

    Cgs

    For typical values, for example, in the µA741 of and , VmAgm /8.6 pFCf 30

    MHzCgsf

    m 361030108.6

    12

    3

    The RHP zero is usually not a problem in bipolar op amps because it is at a much higher frequency than the dominant pole, and can be neglected!

    In a CMOS op amp, where transistor transconductances can be much lower, the right-half plane zero frequency can be quite close to the unity-gain frequency of the op amp.

    fC

    2CVgmiI

    oV

    2R1R 1CV

    B CfC

    B

    C

    12/26

    3-dB FrequencyPoles and Zeros Can Be Easily Determined

    If P1>> P2, P3, , Z1, Z2,then for frequencies near the midband:

    and, Otherwise,

    If P1>> P2, P3, , Z1, Z2,then for frequencies near the midband:

    and, Otherwise,

    High-Frequency ResponseLow-Frequency Response

    )()( sFAsA LM

    )())(()())((

    )(21

    21

    L

    L

    PnPP

    ZnZZL sss

    ssssF

    )()( sFAsA HM

    )1()1)(1()1()1)(1(

    )(21

    21

    H

    H

    PnPP

    ZnZZH sss

    ssssF

    pole)(Dominant 1

    )(P

    L sssF

    .1PL

    )(2 2 221

    22

    21 ZZPPL ωωωω

    2

    22

    12

    22

    1

    112111ZZPP

    H ωωωω

    pole)(Dominant 11

    1)(P

    H ssF

    .1PH

  • 7

    課程講義:【電力電子】 DC-DC Converter - Modeling Techniques交通大學 808-電力電子實驗室 June 4, 2009

    台灣新竹‧交通大學‧電機與控制工程研究所‧808實驗室電源系統與晶片、數位電源、馬達控制驅動晶片、DSP/FPGA控制

    http://pemclab.cn.nctu.edu.tw/Lab-808: Power Electronic Systems & Chips Lab., NCTU, Taiwan

    13/26

    3-dB FrequencyPoles and Zeros Cannot Be Easily Determined

    If a dominant pole exists (say, P1), then

    Thus,

    If a dominant pole exists (say, P1), then

    Thus,

    High-Frequency ResponseLow-Frequency Response

    11

    11)( nLnLnLnL

    L sessdssF

    111 PLPe and

    nL

    i isiL RC1

    1

    nL

    iioiH RC

    11

    11

    11

    PHP

    b

    and

    221

    221

    11)(

    sbsbsasasFH

    PnLPPe 211PnHPP

    b

    11121

    1

    nL

    i isiRCe

    11

    1

    nH

    iioiRCb

    11

    14/26

    Dominant Pole

    2121212

    21212211

    21

    )]([)]([1)(

    RRCCCCCsRRRRgCRCRCsRRgsC

    IV

    fmf

    mf

    i

    o

    If the RHP Zero be neglected,

    2121212

    21212211

    21

    )]([)]([1 RRCCCCCsRRRRgCRCRCsRRg

    IV

    fmf

    m

    i

    o

    If the two poles are two separated real poles,

    11

    21

    11pp

    m

    i

    o

    ssRRg

    IV

    1P2Pf

    m

    Cgs

  • 8

    課程講義:【電力電子】 DC-DC Converter - Modeling Techniques交通大學 808-電力電子實驗室 June 4, 2009

    台灣新竹‧交通大學‧電機與控制工程研究所‧808實驗室電源系統與晶片、數位電源、馬達控制驅動晶片、DSP/FPGA控制

    http://pemclab.cn.nctu.edu.tw/Lab-808: Power Electronic Systems & Chips Lab., NCTU, Taiwan

    15/26

    Dominant Pole

    If p1

  • 9

    課程講義:【電力電子】 DC-DC Converter - Modeling Techniques交通大學 808-電力電子實驗室 June 4, 2009

    台灣新竹‧交通大學‧電機與控制工程研究所‧808實驗室電源系統與晶片、數位電源、馬達控制驅動晶片、DSP/FPGA控制

    http://pemclab.cn.nctu.edu.tw/Lab-808: Power Electronic Systems & Chips Lab., NCTU, Taiwan

    17/26

    Miller Theorem

    Miller theorem describes the way to convert a floating load into two grounded loads, in such way that the voltages and currents are remained unchanged.

    X YZ

    I

    X Y

    Z1

    I I

    Z2

    X

    YYX

    VVA

    ZVVI ,

    X

    Y

    YXX

    VVZZ

    ZVVZIZV

    1111 A

    ZZ

    11

    Y

    X

    XYY

    VVZZ

    ZVVZIZV

    1222

    A

    ZZ 112

    18/26

    Miller Effect on the Compensation Capacitance

    (a) Common-emitter amp. (b) Equivalent circuit

    fC

    2CVgmiI

    oV

    2R1R 1CV

    B CfC

    B

    C

    (c) Equivalent circuit

    fC

    2CiI

    oV

    2R1R V

    B CVA

    2RgA mV 1C 2CiI

    oV

    2R1R V

    B C

    fV CA1C fC

  • 10

    課程講義:【電力電子】 DC-DC Converter - Modeling Techniques交通大學 808-電力電子實驗室 June 4, 2009

    台灣新竹‧交通大學‧電機與控制工程研究所‧808實驗室電源系統與晶片、數位電源、馬達控制驅動晶片、DSP/FPGA控制

    http://pemclab.cn.nctu.edu.tw/Lab-808: Power Electronic Systems & Chips Lab., NCTU, Taiwan

    19/26

    Poles Splitting By Miller Effect

    High-frequency model of the effective capacitive loading by the compensation capacitor. When the compensation capacitor C is removed from the circuit at left, the circuit is transformed into the circuit at right so that the capacitive loading on each stage is maintained.

    A1 A2 1

    C

    Vin V0

    increasing C

    '1 1 2 '2

    CV1 V0

    C1 C2 C2CC1C

    C2

    V0V1

    20/26

    Block Diagram of the OP-AMP Equivalent Circuit

    Block diagram of the op-amp equivalent circuit, including the feedforward current through the compensation capacitor. The feedforward term causes a right half-plane zero in the op-amp transfer function.

    1222

    sCRR

    11111

    sCRRGM

    1MGsC

    2MGinV OV

    sC

    Kent H. Lundberg, "Internal and External Op-Amp Compensation: A Control-Centric Tutorial," American Control Conference, 2004.

  • 11

    課程講義:【電力電子】 DC-DC Converter - Modeling Techniques交通大學 808-電力電子實驗室 June 4, 2009

    台灣新竹‧交通大學‧電機與控制工程研究所‧808實驗室電源系統與晶片、數位電源、馬達控制驅動晶片、DSP/FPGA控制

    http://pemclab.cn.nctu.edu.tw/Lab-808: Power Electronic Systems & Chips Lab., NCTU, Taiwan

    21/26

    RHP Zero of a Common-Source CMOS Amp

    CMOS: circuit design, layout, and simulation, R. Jacob Baker, IEEE Press, 2nd Ed., 2005.

    22/26

    Limitations Imposed by RHP Poles and Zeros

    The control handbook,Editor: W. S. Levine

  • 12

    課程講義:【電力電子】 DC-DC Converter - Modeling Techniques交通大學 808-電力電子實驗室 June 4, 2009

    台灣新竹‧交通大學‧電機與控制工程研究所‧808實驗室電源系統與晶片、數位電源、馬達控制驅動晶片、DSP/FPGA控制

    http://pemclab.cn.nctu.edu.tw/Lab-808: Power Electronic Systems & Chips Lab., NCTU, Taiwan

    23/26

    RHP Zero Compensation and Cancellation

    [REFERENCES][1] D. M. Sable, B. H. Cho, and R. B. Ridley, "Elimination of the positive zero in fixed frequency boost and flyback

    converters," IEEE APEC Proc., 1990.[2] Wei-Chung Wu, R. M. Bass, and J. R. Yeargan, "Eliminating the effects of the right-half plane zero in fixed frequency

    boost converters," IEEE PESC Con. Rec., 1998.[3] Right half-plane zero compensation and cancellation for switching regulators, Inventor: David W. Ritter,

    Assignee: Micrel, Incorprated, San Jose, CA., Patten No.: US 2007/0252570 A1, Nov. 1, 2007.

    24/26

    RHP Zero Compensation and CancellationUS 2007/0252570 A1, Nov. 1, 2007.

    Abstract—An improved method of canceling a RHPZ of a switching regulator can include detecting a predetermined error signal provided to a pulse width modulation (PWM) circuit, wherein the predetermined error signal is associated with the RHPZ. Once a RHPZ is detected, a ramp waveform provided to the PWM circuit can be temporarily lengthened, thereby canceling the RHPZ. Notably, temporarily lengthening the ramp waveform can be based on adjusting an RZ*CZ time constant. In one embodiment, the ramp waveform can be lengthened to create a left half-plane zero (LHPZ), which improves stability.

  • 13

    課程講義:【電力電子】 DC-DC Converter - Modeling Techniques交通大學 808-電力電子實驗室 June 4, 2009

    台灣新竹‧交通大學‧電機與控制工程研究所‧808實驗室電源系統與晶片、數位電源、馬達控制驅動晶片、DSP/FPGA控制

    http://pemclab.cn.nctu.edu.tw/Lab-808: Power Electronic Systems & Chips Lab., NCTU, Taiwan

    25/26

    Summary RHP Zero

    Split LC switching converters operating in CCM will have RHP zero due to the lagging inductor effect! RHP zero CAN NOT be eliminated with current mode control! EHP zero can be eliminated by using variable frequency control.

    26/26

    References: About RHP Zero

    [1] Lloyd H. Dixon, Right-Half-Plane Zero - A simplified explanation, Unitrode Power Supply Design Seminar, 1984.[2] C. Basso, Understanding the Right-Half-Plane Zero, Power Electronics Technology, 2009.[3] Brian Lynch, Under the Hood of a DC-DC Boost Converter, 2008-09 Power Supply Design Seminar - SEM1800.

    [4] D. M. Sable, B. H. Cho, and R. B. Ridley, "Elimination of the positive zero in fixed frequency boost and flyback converters," IEEE APEC Proc., 1990.

    [5] Wei-Chung Wu, R. M. Bass, and J. R. Yeargan, "Eliminating the effects of the right-half plane zero in fixed frequency boost converters," IEEE PESC Con. Rec., 1998.

    [6] Right half-plane zero compensation and cancellation for switching regulators, Inventor: David W. Ritter, Assignee: Micrel, Incorprated, San Jose, CA., Patten No.: US 2007/0252570 A1, Nov. 1, 2007.