2009 2009 finalfinalfinal programprogramprogramhartenstein.de/fdl/fdl-09.pdf · 2009 2009...

2009 2009 2009 2009 FinalFinalFinalFinal ProgramProgramProgramProgram

Sophia AntipolisSophia AntipolisSophia AntipolisSophia Antipolis, France, France, France, France

September 22September 22September 22September 22ndndndnd----24242424

thththth, 2009, 2009, 2009, 2009

General Chair:General Chair:General Chair:General Chair:

Prof. Dominique Borrione - TIMA Laboratory, France

FDLFDLFDLFDL is an event!

2222

Welcome ................................................................................................................................. 3

Chairs & Speakers ................................................................................................................. 4

Program Committee ............................................................................................................... 5

Technical Area Overview ....................................................................................................... 6

Conference Area Map ............................................................................................................ 7

Conference Program.............................................................................................................. 8

UMES1: Model-driven Approaches for Embedded System Performance Evaluation and Architecture Exploration ....................................................................................... 8

CSD1: Design Exploration ..................................................................................................... 8 ESCUG: 20th European SystemC User's Group Meeting ......................................................... 9 Keynote: Getting Turned On By Low Power Electronics - The Unified Power Format ................ 9 CSD2: Emulation, Simulation, Debugging in System Level Modelling .................................. 10 CSD3: Alternative Modelling Paradigms .............................................................................. 10 Joint Session: High-Level Synthesis and Code Generation for Embedded

Systems Applications ............................................................................................... 11 Embedded Tutorial: Formal Assertion Based Verification ....................................................... 12 ABD1: Assertions in Hardware Synthesis and Verification ................................................... 13 EAMS1: Co-simulation and Modelling of Heterogeneous Domains......................................... 13 ABD2: SystemC Verification Techniques ............................................................................. 14 EAMS2: Verification and Modelling Issues in EAMS Design ................................................... 14 Panel: Model-Based Hardware Testing ............................................................................... 15 Interactive Sessions: Poster Presentations ............................................................................ 16

FDL Books ............................................................................................................................ 16

FDL Schedule ....................................................................................................................... 17

DASIP Schedule ................................................................................................................... 18

S4D Schedule ....................................................................................................................... 18

Embedded Workshops and Fringe Meetings .................................................................... 19

Practical Information ........................................................................................................... 20

FDL 2009 will be co-located with:

DASIP 2009 conference: www.ecsi.org/dasip S4D 2009 conference: www.ecsi.org/s4d

SAME 2009 conference www.same-conference.org

Technical co-sponsorship:

Table of ContentsTable of ContentsTable of ContentsTable of Contents

2009200920092009

3333

More than ever, FDL is the place for researchers, developers, industry designers, academia, and EDA

tool companies to present and to learn about the latest scientific achievements, practical applications and users experiences in the domain of specification and design languages. Furthermore FDL covers the modelling and design methods, and their latest supporting tools, for complex embedded systems, systems on chip, and heterogeneous systems. FDL 2009 is the twelfth in a series of events that were held in Lausanne, Lyon, Tübingen, Marseille, Frankfurt am Main, Lille, Barcelona and Stuttgart. This year, FDL is organized together with the DASIP (Design and Architectures for Signal and Image Processing) Conference and the SAME Conference. The three events convene at the same time and in the same attractive south of France area of Sophia Antipolis. All to create a synergy effect and new exchanges between the scientific communities traditionally addressed by these events. In addition to the technical conference sessions, the common exhibition floor will be open to tools and services providers in the system design domain and their customers to enable in-depth technical talks and exchanges, making the exhibition an important part of the FDL, DASIP and SAME events.

FDL 2009 is organized around four Thematic Areas (TA) and includes working sessions, poster sessions, embedded tutorials, panels and technical discussions. Fringe meetings such as user group or standardization meetings are also held in conjunction with the Forum.

The keynote address, given by Stephen Bailey, will present the motivations for, and the semantic features of the newly approved IEEE standard "Unified Power Format". Crossing all individual technical areas, the topic of power requirements and management is of the broadest interest to the FDL attendance.

EAMS TA: Embedded Analog and Mixed-Signal System Design: The two regular sessions and the session shared with the CSD TA cover a large variety of modelling and co-simulation approaches for heterogeneous circuits, on September 23rd and 24th.

ABD TA: Assertion Based Design, Verification & Debug: Two regular sessions on the use of formal properties for verification, synthesis and stimuli generation are preceded by an embedded tutorial on formal assertion based verification, all on September 24th.

UMES TA: UML and MDE for Embedded System: One regular session on system level evaluation followed by one panel on model based testing are scheduled on September 22nd and September 24th respectively.

CSD TA: C/C++-Based System Design: This area of interest again attracted the largest number of submissions, and features three regular sessions, plus one shared with the next TA. The 20th meeting of the European SystemC User's Group is organized in cooperation with the CSD TA, that spans over September 22nd and 23rd.

Two poster sessions are given dedicated time slots, for the interactive presentation of new ideas and on-going works, at the first two afternoon breaks.

FDL 2009 will offer also opportunities for other fringe meetings, and for attending the keynote and panel common with SAME and DASIP.

All the organizing committee wishes the FDL attendants a fruitful event and an enjoyable visit in the beautiful surroundings of Sophia Antipolis.

General Chair: General Chair: General Chair: General Chair:

Prof. Dominique Borrione, TIMA LaboratoryProf. Dominique Borrione, TIMA LaboratoryProf. Dominique Borrione, TIMA LaboratoryProf. Dominique Borrione, TIMA Laboratory, France, France, France, France

Dominique Borrione has been a Professor at the University of Grenoble since 1988. Since January 2007, she is the director of TIMA Laboratory. From the University of Grenoble, she received the MSc in Computer Science in 1972, the PhD in Computer Science in 1976, and the Thèse d'Etat in 1981.Before joining TIMA, she was director of the ARTEMISLaboratory from 1991 to 1995. She was a team leader at ARTEMIS (1988-1995), then at TIMA (1996-2006). From Dec. 1983 to August 1988, she was a Professor at the University of Marseille. She developed the theme of formal methods in hardware design, particularly taking as input designs described in VHDL. Most of her research has been supported by contracts, through industrial and academic cooperative projects in the context of the ESPRIT and MEDEA European programs. Professor Borrione has published over 90 refereed journal papers, international refereed conference papers, and book chapters. She has been a member of numerous working groups, and program committees of international conference and workshop series (CHDL, CHARME/FMCAD, DATE, SBCCI, VLSI-SOC). She was program chair of CHDL'81, DATE'99, CHARME'05.

WelcomeWelcomeWelcomeWelcome to FDL 2009to FDL 2009to FDL 2009to FDL 2009

4444

Technical Area ChairsTechnical Area ChairsTechnical Area ChairsTechnical Area Chairs

KeynoteKeynoteKeynoteKeynote & Tutorial& Tutorial& Tutorial& Tutorial SpeakerSpeakerSpeakerSpeaker

Tutorial SpeakerTutorial SpeakerTutorial SpeakerTutorial Speaker

Chairs & SpeakersChairs & SpeakersChairs & SpeakersChairs & Speakers

UMES TA Chair: Pierre Boulet earned a DEA d'Informatique Fondamentale (Master) in 1993 and a PhD in computer science in 1996 from the École Normale Supérieure de Lyon, France. He is currently professor of computer science at the Université des Sciences et Technologies de Lille, France in the Laboratoire d'Informatique Fondamentale de Lille. He is also a member of the INRIA project team DaRT. His interests range from parallelism, compilation, co-design of embedded system to model driven engineering and synchronous languages. He is currently the secretary of ECSI.

ABD TA Chair: Hans Eveking received his PhD in Electrical Engineering and his habilitation in Computer Science from the Technische Universität Darmstadt. In 1991, he became professor for Design Methodologies at the Department of Computer Science of the J.-W. Goethe University, Frankfurt. In 1995, he became professor for Computer Systems at the Department of Electrical Engineering of the Technische Universität Darmstadt. His main research areas are formal verification and assertion-based design.

CSD TA Chair: Frank Oppenheimer received his Diploma in 1997 and 2005 his PhD in Computing Science from the Carl v.Ossietzky University Oldenburg where he worked as researcher at the Department of Computing Science until 2001. In late 2001 he became Manager of the System Design Methodology Group and in 2008 Director in the R&D division Transportation at the OFFIS e.V. Institute for Information Technology. Since 2005 he is the Chair of the CSD thematic area of the FDL conference and is reviewing member of several other program committees. Frank's prime interests in research are hardware/software interface modelling, programming models for multicore/multiprocessor platforms and synthesis and design methods for heterogeneous, adaptive systems.

Claudia Blank received her diploma in Computer Science in 1996 from J.-W. Goethe University, Frankfurt, Germany, and her PhD in Electrical Engineering in 2002 from Technische Universität Darmstadt, Germany. After having worked for 6 years in research on formal verification, Claudia went to industrial application of formal methods for hardware verification in 2002. Up until 2004 she was engaged as an independent verification engineer in several projects for Infineon Technologies as well as Siemens. In 2004 Claudia joined Infineon Technologies AG, Munich, Germany, where she drove the functional verification methodology on formal methods, had different assignments as expert in formal verification at chip development projects, and co-facilitated the Infineon Institute Verification Community. Since 2008, Claudia has been engaged as Principal Engineer Field Application at OneSpin Solutions, Munich, Germany. Her field of interest is functional hardware verification with focus on formal assertion based verification. Before entering hardware verification in 1996, Claudia gained 9 years of practical business exposure as a software designer and implementation project manager.

Steve Bailey is the Director of Product Marketing for the Design Verification and Technology division of Mentor Graphics. He and his product marketing team are responsible for Mentor’s core functional verification solutions. Steve has been active in the EDA standards community, specifically in the areas of language design through participation in the VHDL, PSL and UPF IEEE standardization efforts and as chairman of the VHDL and UPF working groups. He has also been active in the organization of technical conferences serving as Technical Program Chair and General Chair of the Design & Verification Conference (DVCon) as well as authoring and presenting numerous papers on a variety of topics related to EDA standards, and electronics design and verification over the course of his career.

EAMS TA Chair: Sorin A. Huss studied electrical engineering at TU München, Germany. In 1976 he earned the Dipl.-Ing. degree in EE and in 1982 the Dr.- Ing. degree, all from the same university. He worked from 1982 until 1990 with AEG as a manager of CAE methods for mixed signal circuits. Since 1990 Dr. Huss is a full professor in the Computer Science Dept. of TU Darmstadt, and, in addition, a faculty member of the Electrical Engineering Dept. of the same university. He authored or co-authored two books, several book chapters, and more than 50 reviewed journal and conference papers. He was General Chair of FDL’06 and served as a member of the program committees of many conferences and editorial boards. His current research interests are in the areas of embedded systems engineering and of high-level design methodology for IT security applications.

5555

Embedded Analog Embedded Analog Embedded Analog Embedded Analog

and Mixedand Mixedand Mixedand Mixed----Signal Signal Signal Signal

System Design System Design System Design System Design

TA CommitteeTA CommitteeTA CommitteeTA Committee

TA Chair: Sorin A. Huss

Martin Barnasconi NXP Semiconductors Ernst Christen Umberto Gatti Nokia-Siemens Christoph Grimm TU Wien Joachim Haase FhG IIS/EAS Dresden Lars Hedrich University of Frankfurt Tom Kazmierski U Southampton Piero Malcovati University of Pavia Egbert Molenkamp University of Twente Guido Schreiner MathWorks Serge Scotti ST Microelectronics David W. Smith Synopsys Peter Wilson U Southampton

Assertion Based Assertion Based Assertion Based Assertion Based

Design, VerificDesign, VerificDesign, VerificDesign, Verification & ation & ation & ation &

Debug TA CommitteeDebug TA CommitteeDebug TA CommitteeDebug TA Committee

TA Chair: Hans Eveking

El Mostapha Aboulhamid U Montreal Valeria Bertacco University of Michigan Claudia Blank OneSpin Solutions Slava Bulach Robert Bosch Eduard Cerny Synopsys Emmanuelle Encrenaz University Paris 6 Harry Foster Mentor Graphics Franco Fummi University of Verona Marcello Lajolo NEC Laboratories Pierre Laurence University of Grenoble Ashraf Salem Ain Shams University Pablo Sanchez U Cantabria Julien Schmaltz Radboud U Nijmegen

UML and MDE for UML and MDE for UML and MDE for UML and MDE for

Embedded System Embedded System Embedded System Embedded System

SSSSpecification & pecification & pecification & pecification &

Design TA CommitteeDesign TA CommitteeDesign TA CommitteeDesign TA Committee

TA Chair: Pierre Boulet Gjalt De Jong ArchWorks Grant Martin Tensilica Peter Green UMIST, Manchester Jan Jurjens The Open University Julio Medina U Cantabria Mauro Prevostini Lugano University Ralf Seepold Univ Carlos III de Madrid Robert de Simone INRA Sophia-Antipolis Francois Terrier CEA Dragos Truscan Turku University Yves Vanderperren K.U. Leuven Jeroen Voeten Eindhoven UT

C/C++C/C++C/C++C/C++----Based System Based System Based System Based System

Design TA CommitteeDesign TA CommitteeDesign TA CommitteeDesign TA Committee

TA Chair: Frank Oppenheimer

Jean-Philippe Babau INSA Lyon Luis Baldez Hewlett-Packard Tomas Bautista IUMA Las Palmas Mladen Berekovic U Braunschweig Axel Braun U Tuebingen Peter Flake Elda Joachim Gerlach Robert Bosch Daniel Große University of Bremen Christian Haubelt U Erlangen-Nurnberg Fernando Herrera U Cantabria Wolfgang Klingauf TU Braunschweig Lars Kruse ChipVision Marcos Martinez DS2 Bernhard Niemann Fraunhofer IIS Martin Radetzki Universitaet Stuttgart Sandeep Shukla Virginia Tech. Yves Vanderperren K.U. Leuven Geert Vanmeerbeeck IMEC

Program CommitteeProgram CommitteeProgram CommitteeProgram Committee

6666

UMES TA: UMES TA: UMES TA: UMES TA: UML and MDE for Embedded system UML and MDE for Embedded system UML and MDE for Embedded system UML and MDE for Embedded system

Specification & DesignSpecification & DesignSpecification & DesignSpecification & Design Chair: Pierre Boulet – LIFL, Lille, France, [email protected] Model driven methods, mostly based on the Unified Modelling Language; increasingly support semi-formal methods for system level design of complex embedded systems including highly programmable platforms and heterogeneous Systems-on-Chip. Current design methods do not close the gap from specification to (automatic) synthesis yet. UMES related research topics in this field are Executable UML, model driven development, model transformations, UML semantics, meta-modelling (e.g., for SystemC and other System Description Languages or HDLs), UML profiles (SysML, MARTE, UML for SoC, ...), formalization of UML towards domain specific languages for simulation and synthesis. Other welcomed topics are standardization work, modelling languages for real-time and embedded systems, model driven techniques for performance analysis, validation and verification, SDL, AADL, OCL, XMI and practical design experiences with UML or model driven engineering (MDE) approaches.

CSD TA: C/C++CSD TA: C/C++CSD TA: C/C++CSD TA: C/C++----Based System DesignBased System DesignBased System DesignBased System Design Chair: Frank Oppenheimer – OFFIS, Germany, [email protected] The CSD TA addresses language-based modelling and design techniques for simulation, debugging, transformation, and analysis of hardware/software embedded systems. C/C++ based design methodologies are entering productive industrial design flows especially after the IEEE standardization of SystemC. Hence, the lion’s share of contributions uses SystemC and its extensions to illustrate the scientific approach. However, articles using languages like UML, functional languages, System Verilog are very welcome, especially if they address interoperability between modelling languages and heterogeneous models of computations. Topics of interest also include embedded software modelling techniques and technology or domain specific approaches, e.g. for signal processing applications or reconfigurable computing platforms. New mechanisms for abstraction like transaction level modelling (TLM) or IP-XACT and their implications on IP-based system design or system synthesis are in the scope of this workshop as well as innovative industrial case studies.

ABD TA: Assertion Based Design, VerificationABD TA: Assertion Based Design, VerificationABD TA: Assertion Based Design, VerificationABD TA: Assertion Based Design, Verification & Debug& Debug& Debug& Debug Chair: Hans Eveking – Technische Universität Darmstadt, Germany [email protected] The assertion of formal properties provides a uniform expression of expected system behaviour, or constraints that are assumed on the environment, for a variety of design tasks: verification of functional correctness, generation of test stimuli, synthesis of observation monitors and on-line tests, model checking on the reachable state space, direct synthesis from assertions, etc. Standardized formalisms such as PSL and SystemVerilog assertions were initially intended for synthesizable RTL; their application is now considered at transaction levels and for mixed system designs. The ABD Thematic Area welcomes research contributions, tool demonstrations, reports on standardization activities and effective applications in all aspects of innovative property expression and processing, with an emphasis on frontier design levels, verification, automatic synthesis and mechanized debug aids.

EAMS TA: Embedded Analog and MixedEAMS TA: Embedded Analog and MixedEAMS TA: Embedded Analog and MixedEAMS TA: Embedded Analog and Mixed----Signal SystemSignal SystemSignal SystemSignal System

DesignDesignDesignDesign Chair: Sorin A. Huss – Technische Universität Darmstadt, Germany [email protected] Modern information processing systems frequently combine analog, RF, power electronic, or even non-electrical components with complex digital hardware and an increasing share of software into an embedded system. The aggregation and tight interaction of such components within one data processing system is a challenge: specification, modelling, simulation, (symbolic) analysis, verification, design, (virtual) prototyping, or even synthesis of analog, mixed-signal, and heterogeneous systems, i.e., embedded systems processing both discrete and continuous signals, are highly complex issues. Furthermore, physical effects are of an increasing impact and have to be considered even at system level. Languages, models, representations, and tools such as VHDL-AMS, Verilog-AMS, SystemC-AMS, Modelica, Matlab/Simulink, Hybrid Automata or even SysML are emerging to support such issues starting from transistor level analog circuit up to system level design. The EAMS Thematic Area aims at presenting latest research activities, design experiences, and standardization issues related to these topics.

Technical Area OverviewTechnical Area OverviewTechnical Area OverviewTechnical Area Overview

7777

Conference Conference Conference Conference Area Area Area Area MapMapMapMap

8888

Tuesday – September 22, 2009

14:00-15:30 Room: Marconi

Opening Session UMES1: Model-driven Approaches for Embedded System Performance Evaluation and Architecture Exploration Chair: Pierre Boulet, LIFL, France Co-chair : Robert de Simone, INRIA, France

Abstract The three papers of the section propose to use models and model transformation to support the rapid evaluation of hardware/software embedded systems, by providing timing requirement annotations, by coupling service-based design with workload models or integrating hardware/software partitioning analysis with a model-driven design flow.

Semi-Automated HW/SW Codesign for Embedded Systems: from MARTE Models to SystemC Simulators Luis Gabriel Murillo, Marcello Mura and Mauro Prevostini

Linking GENESYS Application Architecture Modeling with Platform Performance Simulation Subayal Khan, Susanna Pantsar, Jari Kreku, Kari Tiensyrjä and Juha-Pekka Soininen

IP-XACT Components with Abstract Time Characterization Aamir Mehmood Khan, Frédéric Mallet, Charles André and Robert de Simone



Session CSD1: Design Exploration Chair: Daniel Große, University of Bremen, Germany Co Chair: Sandeep Shukla, Virginia Tech, USA

Abstract Efficient design exploration is a very important task in embedded system design since the correction of wrong design decisions in later design phases results in enormous costs. In the first paper of this session a SystemC-based approach for memory design space exploration is presented. The flexibility offered by reconfigurable architectures for the design of application specific processors is addressed by a new model in the second paper. The last paper shows the application of high-level synthesis for rapid prototyping.

Exploration of Embedded Memories in SoCs using SystemC-based Functional Performance Models Hans-Peter Loeb and Christian Sauer

Design Automation Model for Application-Specific Processors on Reconfigurable Fabric Bayram Kurumahmut, Gokhan Kabukcu, Roza Ghamari and Arda Yurdakul

Rapid Prototyping of a DVB-SH Turbo Decoder Using High-Level-Synthesis Marko Roessler, Hailu Wang, Nur Engin, Wolfram Drescher and Ulrich Heinkel

Conference ProgramConference ProgramConference ProgramConference Program

9999



ESCUG 20th European SystemC User's Group Meeting Chair: Axel Braun, University of Tübingen, Germany

Abstract The 20th European SystemC User's Group Meeting will be co-located with FDL Conference 2009 in Sophia Antipolis (France) and will take place on Tuesday, September 22nd, 2009. This meeting will focus on the latest development of SystemC including TLM-2.0 interoperability and the standardization process. Besides the OSCI update, user and vendor presentations will give deep insights into the work and application of SystemC.

Wednesday – September 23, 2009


Keynote: Getting Turned On By Low Power Electronics - The Unified Power Format Chair: Dominique Borrione, TIMA Laboratory, France Speaker: Stephen Bailey, Mentor Graphics, USA

Abstract At the Design Automation Conference (DAC) in 2006, leading electronics companies called members of the Electronic Design Automation (EDA) industry to a meeting of their organization. What electronics crisis had erupted and led the EDA user community to take such unusual action? The transition to sub-100nm manufacturing processes had caught the electronics industry a bit unaware: static leakage of power had moved center stage to become the dominant constraint in electronics. The industry had earlier innovated and evolved techniques to manage dynamic power consumption. Dynamic power management techniques easily fit into existing HDL-based design, verification and implementation flows. With the transition to sub-100nm designs, the industry found that existing design and verification flows could not easily accommodate static power management techniques as those techniques required direct manipulation of power; a detail which had been abstracted out of RTL/HDL design flows in the days when power was cheap and functionality, area and timing were expensive! The electronics design industry called together the leaders of the EDA industry to address the urgent need to develop a new standard for the portable and interoperable specification of low power electronic systems. The electronics users and EDA community, with the sponsorship of Accellera and the IEEE, responded with the Unified Power Format (UPF). In recognition of the urgency of the situation, Accellera completed the first version of UPF in an unprecedented period of 7 months. IEEE approved the 2nd version of UPF as IEEE 1801-2009, approximately 2 years after Accellera’s approval of UPF 1.0.

This keynote address will explore the requirements that initially drove and then evolved the UPF standard. Although pragmatically defined syntactically as TCL commands, HDL packages and attributes, UPF has several interesting semantic capabilities driven by requirements that more than compensate for its lack of syntactic innovation or interest.

10101010



Session CSD2: Emulation, Simulation, Debugging in System Level Modeling Chair: Sandeep Shukla, Virginia Tech, USA Co-Chair: Peter Flake, ELDA, UK

Abstract More widespread adoption of System Level Modeling for electronic system design can be further facilitated by effective modeling techniques for large and complex system architecture, efficient simulation and emulation techniques, and useful debugging facility at he system level. This session brings together three papers dealing with exactly these three issues. The first paper shows modeling of a rather complex, multi-standard and multi-application radio communication system at the transaction level for architecture exploration purposes. Given the rising interest in cognitive and software defined radios, this is quite timely, and illustrative. The second paper shows how to make virtual platforms with SystemC for early software development, by plugging SystemC components into emulation platform offered by QEMU. The final paper, reports preliminary work on providing facilities of check-pointing and restoring for stop and play debugging of SystemC models which is long awaited by SystemC users.

Transaction Level Modeling of an Adaptive Multi-standard and Multi-Application Radio Communication System Anthony Barreteau, Sebastien Le Nours, Olivier Pasquier and Jean-Paul Calvez

Mixed Simulation Kernels for High Performance Virtual Platforms Màrius Montón and Mark Burton

Checkpoint and Restore for SystemC Models Màrius Montón, Jakob Engblom and Mark Burton



Session CSD3: Alternative Modeling Paradigms Chair: Peter Flake, ELDA, UK Co Chair: Daniel Große, University of Bremen, Germany Abstract This session considers various ways of making models configurable. The first paper discusses the impact of different implementation mappings of an application. The second paper discusses various refinements of a model, including the addition of assertions. The third paper uses Haskell to create a configurable model for cache performance analysis.

The Application of Aspectual Feature Module in the Development and Verification of SystemC Models Jun Ye, Tun Li, Marko Rosenmuller and Qingpin Tan

Another Take on Functional System-Level Design and Modeling Tomasz Toczek, Dominique Houzet and Stéphane Mancini

Efficient Approximately-Timed Performance Modeling for Architectural Exploration of MPSoCs Martin Streubühr, Jens Gladigau, Christian Haubelt and Jürgen Teich

11111111



Joint Session: High-Level Synthesis and Code Generation for Embedded Systems Applications Chair: Sorin A. Huss, TU Darmstadt, Germany Co-Chair: Frank Oppenheimer, OFFIS, Germany

Abstract Design methodologies for modern embedded systems need to cope with their increasing complexity by raising the abstraction level and by providing related synthesis and code generation tools. The first paper proposes a new SystemC superset for high-level synthesis purposes. The second contribution introduces a framework for data flow specifications and C code synthesis. Finally, the third paper addresses an exploitation of abstract models of computation for embedded systems specification and their mapping into synthesizable VHDL code.

A SystemC Superset for High-Level Synthesis Maxim Smirnov and Andres Takach

EmCodeSyn: A Visual Framework for Multi-rate Data Flow Specifications and Code Synthesis for Embedded Applications Bijoy Jose, Jason Pribble, Lemaire Stewart and Sandeep Shukla

DEVS2VHDL: Automatic Transformation of XML-specified DEVS Model of Computation Into Synthesizable VHDL Code Hans Gregor Molter, André Seffrin and Sorin Alexander Huss

12121212

Thursday – September 24, 2009


Embedded Tutorial: Formal Assertion Based Verification Chair: Harry Foster, Mentor Graphics, US Speaker: Claudia Blank, OneSpin Solutions, Germany

Abstract Assertion Based Verification (ABV) sees rapid adoption in many companies' verification flow, becoming mainstream technology. After successful introduction of ABV for simulation, today more and more Formal ABV is employed, not only to increase quality but also to accelerate overall verification closure for SoC, ASIC and FPGA designs. This tutorial introduces the audience to the practice of formal ABV based on two 45-minutes parts: "Introduction to SVA based Formal ABV - Get Going in a Day" teaches people new to formal ABV where and how to get started requiring minimal learning effort, based on use cases best suited for starters. This part introduces attendees to: (1) Automatic RTL code analysis (2) Early block-level verification to achieve baseline quality and speed-up integration verification as well as (3) fast analysis of coverage gaps in simulation. Part 1 is suitable for design-, verification- and integration-engineers and managers; no prerequisites in ABV are required. "Recent Advances in SVA based Formal ABV - Get More with Less" shows how to increase formal ABV productivity and quality. This part addresses new root cause analysis techniques, easing and speeding property and design debugging, as well as techniques allowing for efficient exhaustive operation- and transaction-level verification, taking formal ABV to the next productivity and quality level. Part 2 addresses the work of formal ABV users; novices can get an idea of advanced applications.

13131313



Session ABD1: Assertions in Hardware Synthesis and Verification Chair: Laurence Pierre, TIMA Laboratory, France Co-Chair: Daniel Große, University of Bremen, Germany

Abstract This session shows new and advanced concepts and areas of application for assertion-based design. A method for the synthesis of circuits from a set of assertions is presented. A re-use methodology for the verification of protocols defined by sets of assertions is introduced. The application of assertions for asynchronous designs is demonstrated.

High-level Synthesis Using Operation Properties Jan Langer, Ulrich Heinkel A Re-Use Methodology for Formal SoC Protocol Compliance Minh D. Nguyen, Max Thalmaier, Markus Wedler, Dominik Stoffel, Wolfgang Kunz RAT-based Formal Verification of QDI Asynchronous Controllers Khaled Alsayeg, Katell Morin-Allory, Laurent Fesquet


11:00-12:30 Room: Lumière

Session EAMS1: Cosimulation and Modeling of Heterogeneous Domains Chair : Tom Kazmierski, Southampton U, UK Co-Chair: Christoph Grimm, Vienna TU, Austria

Abstract This session presents a range of approaches to co-simulation and HDL-based mixed-signal modelling. In the first paper an approach is proposed to address inter-language run-time switching of simulation models during co-simulation. The second paper describes a co-simulation methodology that relies the SystemC synchronization layer to support user defined solvers and simulators. The final presentation concerns a modeling methodology for the top-down/bottom-up design of RF systems based on reusable VHDL-AMS models. Optimizing HW/SW Co-Simulation based on Run-Time Model Switching

Michael Karner, Christian Steger, Reinhold Weiss and Eric Armengaud Fast and Unified SystemC AMS - HDL Simulation Yaseen Zaidi, Christoph Grimm and Jan Haase A VHDL-AMS Modeling Methodology for Top-Down/Bottom-Up Design of RF Systems Torsten Maehne, Alain Vachoux, Frédéric Giroud and Matteo Contaldo

14141414



Session ABD2: SystemC Verification Techniques Chair: Claudia Blank, OneSpin Solutions, Germany Co-Chair: Hans Eveking, Technische Universität Darmstadt, Germany

Abstract The three papers address various aspects of SystemC-based verification. The first contribution introduces a new technique for stimuli generation for SystemC descriptions based on satisfiability modulo theories (SMT). The second paper shows how assertions written in PSL can be dynamically verified on SystemC transaction-level models. Finally, a method for increasing the scheduling coverage is presented.

SMT-based Stimuli Generation in the SystemC Verification Library Robert Wille, Daniel Grosse, Finn Haedicke, Rolf Drechsler ISIS: Runtime Verification of TLM Platforms Luca Ferro, Laurence Pierre Local Application of Simulation Directed for Exhaustive Coverage of Schedulings in SystemC Specifications Fernando Herrera, Eugenio Villar


14:00-15:30 Room: Lumière

Session EAMS2: Verification and Modeling Issues in EAMS Design Chair: Alain Vachoux, EPFL, Switzerland Co-Chair: Sorin A. Huss, TU Darmstadt, Germany

Abstract: This session addresses three specific aspects of the heterogeneity of Embedded AMS systems. The first paper presents a system-level verification approach using statistical Design of Experiment methodology and SystemC(-AMS). The goal is to determine key parameters that impact system performance more quickly than using directed testing. The second paper presents the modeling of a microsensor node that is intended to work in wireless environments. Particular emphasis is done on efficient modeling of power consumption relatively to possible node modes of operation. The third paper gets down further in abstraction and presents an efficient compact device model of a carbon nanotube transistor supporting ballistic and non-ballistic effects.

Design of Experiments for Effective Pre-silicon Verification of Automotive Electronics Monica Rafaila, Christoph Grimm, Christian Decker and Georg Pelz

A Top-Down Approach for the Design of Low-Power Microsensor Nodes for Wireless Sensor Network Guillaume Terrasson, Renaud Briand, Skandar Basrour and Valérie Dupé

HSPICE Implementation of a Numerically Efficient Model of CNT Transistor Tom Kazmierski, Dafeng Zhou and Bashir Al-Hashimi

15151515

Panel: Model-Based Hardware Testing Presenters: 1. Zainalabedin Navabi - University of Tehran 2. Paolo Prinetto - Politecnico di Torino 3. Hans-Joachim Wunderlich - Stuttgart University



Abstract Model-based Testing plays a key role in both Software and Hardware Communities. The panel aims at presenting the relevant aspects of today's most significant applications of Model-based Hardware Testing in advanced industrial applications. In particular, referring to the target system abstraction level representation, models used from the system level down to the device level will be analyzed. Referring to the role of testing with respect to the product life cycle, the panel shall focus on models used for end-of-production, in-field, and diagnostic testing, respectively. Models adopted to represent physical defects and their related test approaches for different families of components will eventually be presented, including random logic, memories, and processors.

Closing Session: Dominique Borrione - TIMA Laboratory, France Tom Kazmierski – Southampton University, UK



16161616

Languages for Embedded Systems and their Applications Selected Contributions from FDL ‘08 Radetzki, Martin (Ed.) 2009, XIV, 326p., Hardcover ISBN: 978-1-4020-9713-3

Tuesday & Wednesday – September 22 & 23, 2009

15:30-16:30 Room: Conference Hall Interactive Session: Poster Presentations

Proposal to Extend Frequency Domain Analysis in VHDL-AMS Joachim Haase, Ewald Hessel, Heinz-Theo Mammen

Transaction Level Modeling of a FlexRay Communication Network Sebastien Le Nours, M. Cheikhwafa, Olivier Pasquier, Jean-Paul Calvez

Reuse of a HW/SW CoVerification Environment During the Refinement Process of a Functional C Model Down to an Executable HW/SW Specification Markus Winterholer, Florian Schäfer

Understanding Physical Models in VHDL-AMS Abdulhadi Shoufan, Sorin Huss Evaluation of SystemC-AMS Modeling Capabilities of RF Front-End non-linearities: Satellite Receiver Case Study Rami Khouri, Benjamin Nicolle, Lucas Alves Da Silva, William Tatinian, Gilles Jacquemod

A Generic Hardware / Software Communication Middleware for Streaming Applications on Shared Memory Multi Processor Systems-on-Chip Alain Greiner, Etienne Faure, Nicolas Pouillon, Daniela Genius Extension of SystemC Framework Towards Power Analysis Giovanni B. Vece, Massimo Conti and Sara Colazilli

Analysis of Sense Finger Dynamics for Accurate Sigma-Delta MEMS Accelerometer Modelling in VHDL-AMS Chenxu Zhao and Tom Kazmierski

SystemC-based Power Simulation of Wireless Sensor Networks Jan Haase, Markus Damm, Johann Glaser, Javier Moreno and Christoph Grimm

A SystemC TLM2 Model of Communication in Wormhole Switched Networks-on-Chip Adan Kohler and Martin Radetzki

FDL BooksFDL BooksFDL BooksFDL Books

Applications of Specification and Design Languages for SoCs Selected papers from FDL’05 Vachoux, Alain. (Ed.) 2006, XXII, 312 p., Hardcover ISBN: 978-1-4020-4997-2 Design and Specification Languages for SoCs Selected Contributions from FDL'04 Boulet, Pierre (Ed.) 2005, X, 305 p., Hardcover ISBN: 978-0-387-26149-2

Embedded Systems Specification and Design Languages Selected Contributions from FDL’07 Villar, Eugenio 2008, X, 278 p., Hardcover ISBN: 978-1-4020-8296-2 Advances in Design and Specification Languages for Embedded Systems Selected Contributions from FDL’06 Huss, Sorin A. (Ed.) 2007, X, 358 p., Hardcover ISBN: 978-1-4020-6147-9

17171717

FDL ScheduleFDL ScheduleFDL ScheduleFDL Schedule

FD

LR

eg

istr

ati

on

SA

ME

Co

nfe

ren

ce

Key

no

te

SA

ME

Pa

ne

ls +

E

xh

ibit

ion

13:4

5F

DL

Welc

om

e

Ro

om

: M

arc

on

i

UM

ES

Mo

del-

dri

ven

Ap

pro

ach

es fo

rE

mb

ed

ded

S

yste

m P

erf

orm

an

ce E

valu

ati

on

an

d

Arc

hit

ectu

re E

xp

lora

tio

n

Ro

om

: M

arc

on

i

Co

ffe

e B

rea

k &

In

tera

ctiv

e S

es

sio

nR

oo

m:

Lu

nch

Are

a

CS

D1

De

sig

n E

xp

lora

tio

n

Ro

om

: M

arc

on

i

ES

CU

G

Ro

om

: M

arc

on

i

Em

be

dd

ed

Tu

tori

al

Fo

rmal A

ssert

ion

Bas

ed

Veri

ficati

on

Ro

om

: M

arc

on

i

Co

ffe

e B

reak

AB

D1

Assert

ion

s in

HW

S

yn

thesis

&

Veri

ficati

on

Ro

om

: M

arc

on

i

Lu

nch

Ro

om

: L

un

ch

Terr

ace

Pa

ne

l Dis

cu

ssio

nM

od

el-

Based

H

ard

ware

Tes

tin

g

Ro

om

: M

arc

on

i

Clo

sin

g S

es

sio

n

Ke

yn

ote

Gett

ing

Tu

rned

On

By L

ow

Po

wer

Ele

ctr

on

ics

Th

e U

nif

ied

Po

wer

Fo

rmat

Ro

om

: M

arc

on

i

CS

D2

Em

ula

tio

n, S

imu

lati

on

, D

eb

ug

gin

g in

Syste

m L

evel

Mo

delin

g

Ro

om

: E

dis

on

R

oo

m: M

arc

on

i

Lu

nch

Ro

om

: L

un

ch

Terr

ac

e

CS

D3

Alt

ern

ati

ve M

od

ellin

g P

ara

dig

ms

Ro

om

: M

arc

on

i

Co

ffe

e B

reak

&

Inte

rac

tive

Se

ssio

nR

oo

m:

Lu

nch

Are

a

Jo

int

Se

ss

ion

Hig

h-L

evel S

yn

thesis

an

d C

od

e G

en

era

tio

n

for

Em

bed

ded

Syste

ms A

pp

licati

on

s

Ro

om

: M

arc

on

i

So

cia

l E

ven

t

Co

ffee

Bre

ak

2009

2009

2009

2009

EA

MS

1C

osim

ula

tio

n &

M

od

eli

ng

of

He

tero

gen

eo

us

Do

main

sR

oo

m: L

um

ière

AB

D2

Syste

mC

V

eri

ficati

on

T

ech

niq

ues

Ro

om

: M

arc

on

i

EA

MS

2V

eri

ficati

on

an

d

Mo

delin

g Is

su

es in

E

AM

S D

esig

n

Ro

om

: L

um

ière

18181818

DASIPDASIPDASIPDASIP & S4D& S4D& S4D& S4D SchedulesSchedulesSchedulesSchedules

Research Session 1 Room: Edison

Research Session 1 (Cont)System and Software Debug

Room: Edison

Lunch & Parallel Demonstrations

Room: Lunch Terrace

Industrial SessionIndustrial Needs & Requirements for Debug Technology

Room: Edison

Coffee Break & Parallel Demonstrations

Interactive Room

EDA SessionEDA Tool Presentations

Room: Edison

Social Event

Room: Lunch Terrace

Keynote 2: Debug Requirements for Future Generation Systems

Room: Edison

Standardization Session Room: Edison

Coffee Break

Standardization Session (Cont)

Room: Edison

Lunch & Parallel Demonstrations

Room: Lunch Terrace

Research Session 2SoC and Silicon Debug

Room: Edison

Coffee Break & Parallel Demorations

Interactive Room

Coffee Break

2009200920092009

Keynote 1: Standardizing Debug for a Whole Industry

Room: Edison

DASIP Registration

SAMEConferenceKeynote

SAMEPanels + Exhibition

13:45 DASIP Welcome Room: Bell

Session 1Special SessionReconfigurable VideoCoding - 1 Room: Bell

Coffee Break Interactive Session

Room: Lunch Area

Session 2Signal and Image Processing

Room: Bell

ESCUG 20th European SystemC User's Group Meeting

Room: Marconi

Keynote 2Secure and Efficient Cryptographic Hardware: From Designs to Implementations Room: Bell

Coffee Break

Session 6Special SessionReconfiguarble Video Coding - 2 Room: Bell

Lunch

Room: Lunch Terrace

Closing Session

Keynote 1Dataflow Programming for Algorithm and Architecture Adaptation on Concurrent Platforms Room: Bell

Session 3Embedded Systems

Room: Bell

Lunch

Room: Lunch Terrace

Session 4Special SessionDynamic and Partial Reconfiguration

Room: Bell

Coffee Break Interactive Session

Room: Lunch Area

Session 5Arithmetic Design

Room: Bell

Social Event

Coffee Break

Session 7Sensors and Embedded Systems

Room: Bell

2009200920092009

19191919

MARTE Users’ Group (MUG) Tuesday - September 22nd at 10:00 The MARTE User Group will have its second meeting where the progress of the finalization task force (the beta 3 document has been presented at the OMG and should become the 1.0 version) will be presented. The current projects using the MARTE UML profile will be discussed as well as the actions the MARTE User Group has accomplished during the last year and the proposals for actions for next year. Contact: Pierre Boulet, [email protected]

IEEE P1076.1 Working Group Meeting Tuesday - September 22nd at 19:00 The IEEE P1076.1 Working Group has been created under the auspices of the IEEE Design Automation Standards Committee (DASC) with the charter to maintain the IEEE 1076.1 standard, also informally known as the VHDL-AMS hardware description language, and other related IEEE standards. The VHDL-AMS language is an extension of the IEEE 1076 (VHDL) standard that supports the description and the simulation of analog, digital, and mixed-signal circuits and systems. The working group is now developing the next 201X revision of the VHDL-AMS standard by collecting new requirements and aligning to the 1076-2008 standard. The meeting is open to all interested people. More details on http://www.eda.org/vhdl-ams. Contact: Alain Vachoux, [email protected]

SPICE Workshop Wednesday - September 23rd 9:00-18:00 Model-based Construction, Analysis and Verification of Mission Critical Systems. The session will report on recent work addressing the use of precise modelling for engineering software-intensive real-time embedded systems. Analysis, prediction, and verification activities, coupled to component-based implementation beneficial to the development process for high-integrity systems will be detailed. The use of AADL (an SAE standard) as modelling language and its usage modalities, as well as a component-based embedded software technology for the respective engineering activities will be covered. Experience reports will be provided. Link to certification criteria as DO178B will be highlighted. Contact: Vincent Seignole, [email protected]

OSCI AMS Working Group Meeting Wednesday September 23rd at 11:00 Friday September 24th at 9:00 The OSCI AMS Working Group is responsible for the standardization of the SystemC AMS extensions, defining and developing the language, methodology and class libraries for analog, mixed-signal and RF modeling in SystemC. OSCI has released the AMS Draft 1 Standard introducing system-level design and modeling of embedded Analog/Mixed-Signal (AMS) systems. The group is currently enhancing its documentation for clarity and will update the AMS language reference manual. Next steps for the group include the development of a user's guide and to promote the creation of implementations of the SystemC AMS extensions. The meeting is open to all interested people. More details: http://www.systemc.org/apps/group_public/workgroup.php?wg_abbrev=amswg. Contact: Alain Vachoux, [email protected]

Embedded Workshops and MeetingsEmbedded Workshops and MeetingsEmbedded Workshops and MeetingsEmbedded Workshops and Meetings

FDL SponsorsFDL SponsorsFDL SponsorsFDL Sponsors

20202020

Welcome Welcome Welcome Welcome

to Sophia Antipolisto Sophia Antipolisto Sophia Antipolisto Sophia Antipolis

LanguageLanguageLanguageLanguage The language of the forum will be English.

HoursHoursHoursHours Registration Hours:

• Tuesday 8:00–12:00 • Wednesday 8:30–9:00 • Thursday 8:30–9:30

Conference Hours: 9:00–18:00

Social EventSocial EventSocial EventSocial Event • Bus leaves from CICA at 18:30 • Social Event tickets are distributed

at registration

CoCoCoContact Infontact Infontact Infontact Info

PROF. DOMINIQUE BORRIONE General Chair [email protected]

DR ADAM MORAWIEC ECSI Director [email protected]

ECSI OFFICE Parc Equation - 2, Avenue de Vignate 38610 Gieres, France Phone: +33 4 76 63 49 34 Fax: +33 4 76 42 87 87 www.ecsi.org

Practical InformationPractical InformationPractical InformationPractical Information

Sophia Antipolis is a technology park northwest of Antibes and southwest of Nice, France. Much of the park falls within the commune of Valbonne. Created in 1970-84, it houses primarily companies in the fields of computing, electronics, pharmacology and biotechnology. Several institutions of higher learning are also located here, along with the European headquarters of W3C.

This year’s event will take place in Grasse where we will explore our senses. Our first stop will take us to Galimard Perfumerie where we will explore our sense of smell by learning the process of making perfumes by some of the best French noses in the world. After we will delight in our sense of taste with a 3 course traditional French meal in a 13th century village with beautiful sights of the countryside. There you will have the sense of feeling like you have gone back in time five centuries and all you will need to bring along is your sense of humor.

2009 2009 finalfinalfinal programprogramprogramhartenstein.de/fdl/fdl-09.pdf · 2009 2009...

Documents