TRNG AI HOC BACH

FL061KHOA C KHB MN C IN T

Lp trnh ngt PORTB, SLEEP v WAKE-UP trn Kit PICDEM

1. Gii thiu Interrupts, thng c gi l ngt, l mt tn hiu khn cp gi n b x l, yu cu b x l tm ngng tc khc cc hot ng hin ti nhy n mt ni khc thc hin mt nhim v khn cp no , nhim v ny gi l trnh phc v ngt ISR (Interrupt Service Routine ). Sau khi kt thc nhim v trong ISR, b m chng trnh s c tr v gi tr trc b x l quay v thc hin tip cc nhim v ang c thc hin khi trc khi ngt xy ra. Nh vy, ngt c mc u tin x l cao nht, ngt thng c dng x l cc s kin bt ng nhng khng tn qu nhiu thi gian. Cc tn hiu dn n ngt c th xut pht t cc thit b bn trong chip (ngt bo b m timer/counter trn, ngt bo qu trnh gi d liu bng RS232 kt thc) hay do cc tc nhn bn ngoi (ngt bo c 1 button c nhn, ngt bo c 1 gi d liu c nhn)Trong bi th nghim ta s s tp trung vo vic s dng module ngt I/O trn bo mch thc hnh Kit PICDEM. c th tin hnh vic th nghim, sinh vin cn trang b cc thit b sau: Bo mch Kit PICDEM Mechatronics Mch np Pickit Phn mm vit code cho vi iu khin ( MPLab + Cxx Compiler, Hi-TechC, CCS-C hoc MicroC )

Mc tiu: c tn hiu t bn ngoi vo vi iu khin thng qua x l ngt (PortB). Hin thc chng trnh thit lp PIC ch SLEEP v WAKEUP PIC s dng ngt.

2. Thi gian thc hin:Thi lng: 3 tit cho mi nhm sinh vin3. Ni dung th nghim3.1. Bi th nghim 1: Lp trnh vi ngt PORTB bi: Hy vit mt on chng trnh cho vi iu khin thc hin nhim v: nhn nt SW3 th PIC ch SLEEP, nhn nt SW2 th PIC ch WAKEUP v lm thay i trng thi n led D0 (sng thnh tt, tt thnh sng)Thc hin kt ni cc chn nh sau: Kt ni chn SW2 => RB5 Kt ni chn SW3 => RB4 Kt ni chn RD7 => R36

Chng trnh: #include #device adc=8#FUSES NOWDT //No Watch Dog Timer#FUSES HS //High speed Osc (> 4mhz for PCM/PCH) (>10mhz for PCD)#FUSES NOPUT //No Power Up Timer#FUSES NOPROTECT //Code not protected from reading#FUSES MCLR //Master Clear pin enabled#FUSES NOCPD //No EE protection#FUSES NOBROWNOUT //No brownout reset#FUSES IESO //Internal External Switch Over mode enabled#FUSES FCMEN //Fail-safe clock monitor enabled#FUSES NODEBUG //No Debug mode for ICD#use delay(internal=8M) //#include #bit bitRB0 = 0x06.0#bit bitRB4 = 0x06.4#bit bitRB5 = 0x06.5#bit bitRD7 = 0x08.7#bit bitRD6 = 0x08.6short sleep_mode; //---------------------------------------------------------------------------------------//------------------------- interupts ---------------------------------------------------#INT_RB void rb_isr() { if(bitRB4 == 0){ sleep_mode=TRUE;} if(bitRB5 == 0){ sleep_mode=FALSE; } delay_ms(100);} //==================== end ==========================================================void main(){ SET_TRIS_B( 0b11111111 ); //set RB0 as input, RB1 to RB7 as input SET_TRIS_D( 0b00000000 ); //set RD0 to RD7 as output sleep_mode=TRUE; // init sleep flag //ext_int_edge(H_TO_L); // init interrupt triggering for button press port_b_pullups (0); enable_interrupts(INT_RB4);// turn on interrupts enable_interrupts(INT_RB5);// turn on interrupts enable_interrupts(GLOBAL); while (1) { if(sleep_mode) // if sleep flag set sleep(); // make processor sleep delay_ms(100); bitRD7 ^= 1; }}

Yu cu:Sinh vin vit li cc on code trn v np vo vi iu khin tr li cc cu hi trong phn bo co kt qu th nghim

3.2. Thc hin chng trnh sau:Sinh vin thc hin kt ni 3 nt nhn SW2, SW3, SW4 n 3 chn input RB4-RB6 ca vi iu khin, kt ni 3 chn Output n cc n D0,D1,D2. Vit chng trnh cc ngt PORTB nhn tn hiu cho vi iu khin: Nhn SW2: D0 sng. Cc n khc tt. Nhn SW3: D1 sng. Cc n khc tt. Nhn SW4: D2 sng. Cc n khc tt.

3.3. Thc hin chng trnh sau:Sinh vin thc hin kt ni 3 nt nhn SW2, SW3, SW4 n 3 chn input RB4-RB6 ca vi iu khin, kt ni 3 chn Output n cc n D0,D1,D2. Vit chng trnh thit lp ch lun lun SLEEP cho PIC v s WAKEUP PIC mi khi c mt trong cc nt nhn SW2, SW3, SW4 c nhn v: Nhn SW2 : D0 sng. Nhn SW3 : D1 sng. Nhn SW4 : D2 sng.

4. Kt qu thc hnh, th nghim (Lu : Sinh vin np li t ny cho Ging vin hng dn sau bui th nghim) Bi th nghim 3.1:

Cu hi

1. C bao nhiu interrupt PORTB vi PIC16F917?Gii thch:C 2 interrupt PORTB

2. Cu lnh port_b_pullups (0); c nga g? Nu thit lp cu lnh port_b_pullups (1); trong chng trnh trn c c khng?Gii thch:port_b_pullups (0): deactivate the input pullupsport_b_pullups (1): activate the input pull-upsc

3. Nhng s kin no c th WAKEUP PIC ch SLEEP?Gii thch:1. Khi reset chn MCLR2. WatchDog Timer c kch hot3. Ngt ngoi t chn RB0/INT/SEG0, ngt thay i Port B

4. Ti sao interrupt PORTB, interrupt ngoi RB0 khng cn thit lp bit PEIE?Gii thch: page 198V ngt port B v PEIE c cng mc u tin (v RBIE v PEIE i vo cng logic OR trc khi vo ngt CPU) nn khi ngt port B xy ra khng cn cn thit lp bit PEIE

5. Trong chng trnh trn, hy tm cc on code tha m khi b ra khng nh hng n hot ng ca mch? Gii thch v sao?Gii thch:#device adc=8#FUSES NOWDT //No Watch Dog Timer#FUSES HS //High speed Osc (> 4mhz for PCM/PCH) (>10mhz for PCD)#FUSES NOPUT //No Power Up Timer#FUSES NOPROTECT //Code not protected from reading#FUSES MCLR //Master Clear pin enabled#FUSES NOCPD //No EE protection#FUSES NOBROWNOUT //No brownout reset#FUSES IESO //Internal External Switch Over mode enabled#FUSES FCMEN //Fail-safe clock monitor enabled#FUSES NODEBUG //No Debug mode for ICD//#include

Bi th nghim 3.2:Khng chy Chy khng hon chnh Chy tt

kin khc:

Bi th nghim 3.3:Khng chy Chy khng hon chnh Chy tt

kin khc:

H v tn sinh vin:MSSV:Nhm:..Ngy thc hnh / th nghim:.K tn: 5. Ti liu tham kho[1] PICDEM Mechatronics Demonstration Board Users Guide.

Faculty of Mechanical Engineering @HCMUT4