3. singlebus_multibus
TRANSCRIPT
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Control Unit
CS1251Computer Organization
Carl Hamacher
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Control Unit
ALUIR
MAR
MEM
PC
MDR
R0
R1
.
.
.
Rn-1
Control
Processor
MAR - Memory Address Register
MDR - Memory Data Register
PC - Program Counter
IR - Instruction Register
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Fetch and Execute
Fetch MAR [PC] PC [PC] + 1 MDR [MEM([MAR])] IR [MDR]
Execute MAR NUM1 MDR [MEM([MAR])] R1 [MDR]
MOVE NUM1,R1
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Single-Bus Architecture
12
PC
IR
REGS
A B
RALU
MDR
MARMEM
BUS A
Y
Z
1 2
MUX
21
1
MUX
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Instruction Execution
Perform one or more of the following operations in some specified sequence Transfer a word of data from one processor register to
another or to the ALU Perform an arithmetic or logic operation and store the
result in a processor register Load the contents of a given memory location into a
processor register Store a word of data from a processor register into a
given memory location
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Memory Timing
MOVE NUM1,R1
1. MAR NUM12. MDR [MEM([MAR])]3. R1 [MDR]
One Clock Cycle ? Clock Cycles One Clock Cycle
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Memory Detail
RAM
ADDRESS
DATA_OUT
DATA_IN
Read
Write
MEM
MDR
REG_2PORTDATA_OUT1
Enable_In1
DATA_IN2
Enable_Out2
Enable_Out1
DATA_IN1 DATA_OUT2
Enable_In2CLK CLK
REGDATA_OUTEnable_Out
DATA_INEnable_InCLK
MAR BUS_A
MFC
MFC = Memory-Function-Completed
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Memory Timing
Step RTN Control Signals
1 MAR NUM1
2MDR [MEM([MAR])]
3 R1 [MDR]
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Memory Timing
Step RTN Control Signals
1 MAR NUM1 MAR_En_In, IR_En_Out1
2MDR [MEM([MAR])] MEM_Read, MDR_En_In1,
Wait MCF3 R1 [MDR] MDR_En_Out2, REGS_Sel,
REGS_Write
Clock
MAR_En_In
Address
MEM_Read
MDR_En_In1
Data_Out
MFC
MDR_En_Out2
Step 1 2 3
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Another Example
Fetch MAR [PC] PC [PC] + 1 MDR [MEM([MAR])] IR [MDR]
Execute MAR [R3] MDR [MEM([MAR])] Y [R1] Z [Y] + [MDR] R1 [Z]
ADD (R3),R1
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Control Signals
Step RTN Control Signals
1 MAR [PC],PC [PC] + 1
2 MDR [MEM([MAR])]
3 IR [MDR]
4 MAR [R3]
5 MDR [MEM([MAR])],Y [R1]
6 Z [Y] + [MDR]
7 R1 [Z]
ADD (R3),R1
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Control Signals
Step RTN Control Signals
1 MAR [PC],PC [PC] + 1
MAR_En_In, PC_En_Out,PC_Inc
2 MDR [MEM([MAR])] MEM_Read, MDR_En_In13 IR [MDR] MDR_En_Out2, IR_En_In14 MAR [R3] MAR_EN_In, REGS_Sel, REGS_Read5 MDR [MEM([MAR])],
Y [R1]MEM_Read, MDR_En_In1, REGS_Sel, REGS_Read, Y_En_In1
6 Z [Y] + [MDR] Y_En_Out1, MDR_En_Out2, ALU_Op = Add, Z_En_In
7 R1 [Z] Z_En_Out, REGS_Sel, REGS_Write
ADD (R3),R1
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Branch Instructions
MOVE N,R1 MOVE #NUM1,R2 MOVE #0,R0LOOP ADD (R2),R0 ADD #1,R2 ADD #-1,R1 BGTZ LOOP MOVE R0,SUM HALT
BGTZ -4 PC
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Branch Instructions
Execute if CC>0, PC [PC] + [IR]
Condition Code Z = 0, N = 0
BGTZ LOOP
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Multiple Bus Architecture
A
B
R
1 12
A1 A2
PC
IR
1
22
22
REGS
ALU
MDR3 1
MAR
MEM
NZVC
BUS A BUS B BUS C
MU
X
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Example Revisited
Fetch MAR [PC] PC [PC] + 1 MDR [MEM([MAR])] IR [MDR]
Execute MAR [R3] MDR [MEM([MAR])] R1 [MDR] + [R1]
ADD (R3),R1
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Control Signals
Step RTN Control Signals
1 MAR [PC],PC [PC] + 1
2 MDR [MEM([MAR])]
3 IR [MDR]
4 MAR [R3]
5 MDR [MEM([MAR])]
6 R1 [MDR] + [R1]
ADD (R3),R1
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Control Signals
Step RTN Control Signals
1 MAR [PC],PC [PC] + 1
MAR_En_In, PC_En_Out, ALU_Op = Pass_B, PC_Inc
2 MDR [MEM([MAR])] MEM_Read, MDR_En_In13 IR [MDR] MDR_En_Out2, IR_En_In1,
ALU_Op = Pass_A4 MAR [R3] MAR_EN_In, REGS_Read1,
ALU_Op = Pass_A5 MDR [MEM([MAR])] MEM_Read, MDR_En_In16 R1 [MDR] + [R1] MDR_En_Out2, REGS_Read2,
ALU_Op = Add, REGS_Write
ADD (R3),R1
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Questions?