PEAR-LAB Utsunomiya Univ.

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PEAR-LAB Utsunomiya Univ.

]_

SCOPE 152103014

• FPGA

•• 27 29

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PEAR-LAB Utsunomiya Univ.

PRUD

•• SLAM Deep Learning•

•FPGA*

• Field Programmable Gate ArrayLSI

• & [1]

• FPGA ו FPGA

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[1] Li, F., Lin, Y., He, L., and Cong, J., “Low-power FPGA using pre-defined dual-Vdd/dual-Vtfabrics,” In Proceedings of the 2004 ACM/SIGDA 12th international symposium on Field programmable gate arrays (pp. 42-50). ACM, 2004.

PEAR-LAB Utsunomiya Univ.

PRON

• FPGAcReComp

• cReComp creator for Reconfigurable Component• FPGA ROS

• ROS (Robot Operating System) •

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PEAR-LAB Utsunomiya Univ.

ROSH@FPGA�,&.!,�[2]

• FPGA ROS ו ROS

• Programmable SoC (CPU FPGA) • CPU-FPGA

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FPGA

( )

CPU FPGA

ROS

ROS

ROS

Topic

Topic

[2] Kazushi Yamashina, Takeshi Ohkawa, Kanemitsu Ootsu and Takashi Yokota : “Proposal of ROS-compliant FPGA Component for Low- Power Robotic Systems - case study on image processing application -”, Proceedings of 2nd International Workshop on FPGAs for Software Programmers, FSP2015, pp. 62-67, 2015.

PEAR-LAB Utsunomiya Univ.

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����(�����) FPGA (�����)ROS

Topic

Topic

ROSComponent

(software only)

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ROS FPGA

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��������Topic

• FPGA•• FPGA I/F• PWM• HW-SW• FPGA• FPGA HW-SW

PEAR-LAB Utsunomiya Univ.

cReCompfcreator for Reconfigurable Componentg

• FPGA ROS FPGA

• HW-SW

•Python or scrp

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git clone https://github.com/kazuyamashi/cReComp.git

pip install crecomp

PEAR-LAB Utsunomiya Univ.

cReComp��,�.$���J?(�*

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•• HDL• HW-SW• scrp (specification for cReComp )• Python

•• (HDL)•

(C++)• ROS msg

••• SW HW • HW SW ••

HW I/FSW I/FROS

*.v

ROS FPGA

*.cpp

( )

I/F

cReComp*.scrp or *.py

*.v*.msg

PEAR-LAB Utsunomiya Univ.

cReComp�L��aM$+.

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crecomp -s sensor_ctl.scrp -u sonic_sensor.v

crecomp -b sensot_ctl.scrp

sensor_ctl/+--hardware/+----sensor_ctl.v+----sonic_sensor.v+--software/+----lib_cpp.h+----Makefile+----sensor_ctl.cpp+----ros_package/

PEAR-LAB Utsunomiya Univ.

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SoftwareInterface

(C++)

FIFO 32-bits

sig_outHardwareInterface

(Verilog-HDL)

sonic_sensor( )

writeread

HW→SWSW→HW

/

Sensor

ROS Pub/Sub

CPU FPGA

req_in

sensor_data32

32

finish_flag

busy_flag

cReComp

PEAR-LAB Utsunomiya Univ.

6ShcReComp�YXJK>�Z1:e[4]fcReComp�I#.�),��8�#.�),g•• cReComp

scrp• 6• FPGA 3 • C++ 1 6 • Linux 1 3

•1. cReComp2. Scrp3.

( )•• 5

(5 × 4 ×3 2 1 )

••

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0:000:020:050:080:110:140:170:20

1

2

3

4

5

cReComp Scrp

()

(5 1 )

Zedboard AvnetProgrammable SoC Zynq-7020 Xilinx ARM 666MHzOS xillinux-1.3 Ubuntu12.04ROS groovy

Parallax PING Ultrasonic Distance Sensor

FPGA42

[4] FPGA ROS ,” 60 , 2016.

×

PEAR-LAB Utsunomiya Univ.

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• FPGAcReComp

• cReComp• FPGA ROS FPGA

• HW-SW

••• 10• Visual SLAM FPGA “

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PEAR-LAB Utsunomiya Univ.

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cReComp : git clone https://github.com/kazuyamashi/cReComp.git

pip install crecomp

FPGA ROS

FPGA ROS : OpenRerochttps://github.com/Kumikomi/OpenReroc

OpenReroc FPGA ROS

PEAR-LAB Utsunomiya Univ.

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*

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