8051 pres

7/30/2019 8051 pres

1/126

7/30/2019 8051 pres

2/126

Microprocessor vs. Microcontroller

Microprocessor

CPU is stand-alone, RAM,ROM, I/O, timer are separate

designer can decide on theamount of ROM, RAM and I/Oports.

expansive

versatility

general-purpose

Microcontroller

CPU, RAM, ROM, I/O andtimer are all on a singlechip

fix amount of on-chipROM, RAM, I/O ports

for applications in whichcost, power and space are

critical

single-purpose

7/30/2019 8051 pres

3/126

FEATURES

8-bitCPU optimized for control applications

Extensive Boolean processing (Single-bit logic) capabilities

64K Program Memory address space

64K Data Memory address space 4K bytes of on-chip Program Memory

128 bytes of on-chip Data RAM

32 bidirectional and individually addressable 1/0 lines

Two 16-bit timer/counters

Full duplex UART

6-source/5-vector interrupt structure with two priority levels

On-chip clock oscillator

7/30/2019 8051 pres

4/126

PIN DETAILS

7/30/2019 8051 pres

5/126

Interrupt

Control

CPU

4K

ROM128

RAM

OSC BusControl

4 I/O PortsSerial

Port

Timer 1

Timer 0

BLOCK DIAGRAM

TXD RXDP0 P1 P2 P3

7/30/2019 8051 pres

6/126

7/30/2019 8051 pres

7/126

INTERNAL RAM STRUCTURE

Direct &

Indirect

Addressing

Inirect

Addressing

Only

Direct

Addressing

Only SFR

128 Byte

Internal RAM

7/30/2019 8051 pres

8/126

128 BYTE RAM

128 BYTE

INTERNAL RAM

Register Banks

Reg Bank 0

Reg Bank 1

Reg Bank 2

Reg Bank 3

BIT AddressableArea

General Purpose

Area

7/30/2019 8051 pres

9/126

7/30/2019 8051 pres

10/126

REGISTER BANK STRUCTURE

R0 R1 R2 R3 R4 R5 R6 R7Bank 0




CY AC F0 RS1 RS0 OV - P

Program Status Word - PSW

7/30/2019 8051 pres

11/126

F8 FFF0 B F7

E8 EF

E0 Acc E7

D8 DF

D0 PSW D7

C8 CF

C0 C7

B8 IP BF

B0 P3 B7

A8 IE AF

A0 P2 A7

98 SCON SBUF 9F

90 P1 97

88 TCON TMOD TL0 TL1 TH0 TH1 8F

80 P0 SP DPL DPH PCON 87

SFR

7/30/2019 8051 pres

12/126

Flash Memory

Flash memory (sometimes called "flash RAM") is a type ofconstantly-powered nonvolatile memory that can be erasedand reprogrammed in units of memory called blocks. It is avariation of electrically erasable programmable read-onlymemory (EEPROM) which, unlike flash memory, is erasedand rewritten at the byte level, which is slower than flash

memory updating.

memory gets its name because the microchip is organizedso that a section of memory cells are erased in a singleaction or "flash." The erasure is caused by Fowler-Nordheim

tunneling in which electrons pierce through a thin dielectricmaterial to remove an electronic charge from a floatinggate associated with each memory cell. Intel offers a formof flash memory that holds two bits (rather than one) ineach memory cell, thus doubling the capacity of memory

without a corresponding increase in price.
http://searchstorage.techtarget.com/sDefinition/0,,sid5_gci212668,00.htmlhttp://whatis.techtarget.com/definition/0,,sid9_gci211945,00.htmlhttp://whatis.techtarget.com/definition/0,,sid9_gci211945,00.htmlhttp://whatis.techtarget.com/definition/0,,sid9_gci211945,00.htmlhttp://whatis.techtarget.com/definition/0,,sid9_gci211945,00.htmlhttp://searchstorage.techtarget.com/sDefinition/0,,sid5_gci212668,00.html

7/30/2019 8051 pres

13/126

Crystal Ocillator

7/30/2019 8051 pres

14/126

Oscillator Circuit

The 8051 uses the crystal for precisely that: tosynchronize its operation.

A single machine cycle is the minimum amount oftime in which a single 8051 instruction can be

executed.8051 has an on-chip oscillator. It needs an external

crystal that decides the operating frequency of the8051.

The crystal is connected to pins 18 and 19 withstabilizing capacitors. 12 MHz(11.059MHz) crystal isoften used and the capacitance ranges from 20pFto 40pF.

7/30/2019 8051 pres

15/126

A cycle is 12 pulses of crystal

If crystal pulse is 11,059,000 times persecond, instruction cycles per second is11,059000/12=921,583khz

Ie 1/921.6khz=1.085 s

7/30/2019 8051 pres

16/126

TIMERS

SERIAL PORT

INTERRUPTS

7/30/2019 8051 pres

17/126

TIMERS

SERIAL PORT

INTERRUPTS

7/30/2019 8051 pres

18/126

Timer 0

Mode 3

Mode 2

Mode 1

Mode 0

Mode 2

Mode 1

Mode 0

Timer 1

TIMERS

7/30/2019 8051 pres

19/126

M0M1C/GateM0M1C/GateTMOD

IT0IE0IT1IE1TR0TF0TR1TF1TCON

Timer 0Timer 1

InterruptTimers

SFRs Related to TIMER

7/30/2019 8051 pres

20/126

TIMERS

SERIAL PORT

INTERRUPTS

7/30/2019 8051 pres

21/126

SERIAL PORTMode 0

The Serial Port in Mode-0 has the following

features:

Serial data enters and exits through RXD

TXD outputs the shifl clock

8 bits are transmitted / received

The baud rate is fixed at (1/12) of the

oscillator frequency

7/30/2019 8051 pres

22/126

SERIAL PORTMode 1

The Serial Port in Mode-1 has the following features:

Serial data enters RXD

Serial data exits through TXD

On receive, the stop bit goes into RB8 in SCON


Start bit (0)

Data bits (8)

Stop Bit (1)

Baud rate is determined by the Timer 1 overflow rate.

7/30/2019 8051 pres

23/126

SERIAL PORTMode 2The Serial Port in Mode-2 has the following features:



9th data bit (TB8) can be assign value 0 or 1

On receive, the 9th data bit goes into RB8 in SCON


Start bit (0)

Data bits (9)

Stop Bit (1)

Baud rate is programmable (1/32) or (1/64)of the oscillator frequency

7/30/2019 8051 pres

24/126

SERIAL PORTMode 3The Serial Port in Mode-3 has the following features:



9th data bit (TB8) can be assign value 0 or 1

On receive, the 9th data bit goes into RB8 in SCON


Start bit (0)

Data bits (9)

Stop Bit (1)

Baud rate is determined by the Timer 1over flow rate.

7/30/2019 8051 pres

25/126

RITIRB8TB8RENSM2SM1SM0SCON

IDLPDGF0GF1---SMODPCON

SFRs Related to SERIAL PORT

7/30/2019 8051 pres

26/126

TIMERS

SERIAL PORT

INTERRUPTS

7/30/2019 8051 pres

27/126

INTERRUPTS

The Interrupt structure has the following features:

6 sources / 5 vectored interrupts

Each interrupts can be individually programmable

Each interrupts can have two priority levels

Priority levels can be programmed

All interrupts can be masked by a single bit - EA

External interrupt type can be programmed

Edge triggered

Level Triggered

7/30/2019 8051 pres

28/126

1INT

TIMER / COUNTER

0INT

0TF

1TF

TI

RI

INTERRUPT

SOURCES

IE0

IE1

7/30/2019 8051 pres

29/126

1INT

TIMER / COUNTER

0INT

0TF

1TF

TIRI

IE0

IE1

Individual

Enable

Global

Disable

Low PriorityInterrupt

High Priority

Interrupt

InterruptPolling

Sequence

IE Reg IP Reg

0IT

1IT

0

0

1

1

7/30/2019 8051 pres

30/126

EX0ET0EX1ET1ES--EAIE

PX0PT0PX1PT1PS---IP

SFRs Related to INTERRUPTS

IE0TF0IE1TF1RI / TILOW HIGH

Priority Within Level

IT0IE0IT1

IE1TR0TF0TR1

TF1

TCON

7/30/2019 8051 pres

31/126

7/30/2019 8051 pres

32/126

MEMORY INTERFACING

External RAM Interfacing :-

MCS 51ALE

EXTRAM

Data

Address

RDWR RD WR

ALE

P0

P2

P1

P3

7/30/2019 8051 pres

33/126

MEMORY INTERFACING

External RAM Interfacing :-

D

CLK

Q

D

CLK

Q

D

CLK

Q

D

CLK

Q

AD0

AD1

AD2

AD3

D0

D1

D2

D3

A0

A1

A2

A3

7/30/2019 8051 pres

34/126

MEMORY INTERFACING

External ROM Interfacing :-

MCS 51ALE

EXTROM

Instr

Address

PSEN CE

ALE

P0

P2

P1

P3

EA

EEPROM

7/30/2019 8051 pres

35/126

7/30/2019 8051 pres

36/126

Registers

The AccumulatorThe Accumulator, as its name suggests, is used as a general register toaccumulate the results of a large number of instructions. It can hold an8-bit (1-byte) value and is the most versatile register the 8052 has due tothe sheer number of instructions that make use of the accumulator.More than half of the 8052's 255 instructions manipulate or use the

Accumulator in some way. The "R" Registers

The "R" registers are sets of eight registers that are named R0, R1,through R7. These registers are used as auxiliary registers in manyoperations. To continue with the above example, perhaps you areadding 10 and 20. The original number 10 may be stored in the

Accumulator whereas the value 20 may be stored in, say, register R4. Toprocess the addition you would execute the command:

7/30/2019 8051 pres

37/126

Registers

The B RegisterThe "B" register is very similar to the Accumulator in the sense that itmay hold an 8-bit (1-byte) value. The "B" register is only used implicitlyby two 8052 instructions: MUL AB and DIV AB. Thus, if you want toquickly and easily multiply or divide A by another number, you maystore the other number in "B" and make use of these two instructions.

The Program CounterThe Program Counter (PC) is a 2-byte address that tells the 8052 wherethe next instruction to execute is found in memory. When the 8052 isinitialized PC always starts at 0000h and is incremented each time aninstruction is executed. It is important to note that PC isn't always

incremented by one. Since some instructions are 2 or 3 bytes in lengththe PC will be incremented by 2 or 3 in these cases.

7/30/2019 8051 pres

38/126

Registers

The Data PointerThe Data Pointer (DPTR) is the 8052s only user-accessible16-bit (2-byte) register. The Accumulator, "R" registers, and"B" register are all 1-byte values. The PC just described is a16-bit value but isn't directly user-accessible as a working

register. The Stack Pointer

The Stack Pointer, like all registers except DPTR and PC,may hold an 8-bit (1-byte) value. The Stack Pointer is used toindicate where the next value to be removed from the

stack should be taken from.

7/30/2019 8051 pres

39/126

Instruction Set

5 Groups

Arithmetic Operation Group

Logical Operation Group

Data Transfer Group

Boolean Variable Manipulation GroupProgram Branching Group

7/30/2019 8051 pres

40/126

Instruction Set

5 Groups



Data Transfer Group


7/30/2019 8051 pres

41/126


ADD A,Direct

ADD A,Rn

ADD A,@Ri

ADD A,#Data

7/30/2019 8051 pres

42/126


ADDC A,Direct

ADDC A,Rn

ADDC A,@Ri

ADDC A,#Data

7/30/2019 8051 pres

43/126


SUBB A,Direct

SUBB A,Rn

SUBB A,@Ri

SUBB A,#Data

7/30/2019 8051 pres

44/126


INC A

INC Direct

INC Rn

INC @Ri

7/30/2019 8051 pres

45/126


DEC A

DEC Direct

DEC Rn

DEC @Ri

7/30/2019 8051 pres

46/126


INC DPTR

MUL AB

DIV AB

DA A

I i S

7/30/2019 8051 pres

47/126

Instruction Set

5 Groups



Data Transfer Group


7/30/2019 8051 pres

48/126

The SJMP command can only jump to an addresswithin +/- 128 bytes of the SJMP command.

The AJMP command can only jump to an address

that is in the same 2k block of memory as the AJMPcommand. That is to say, if the AJMP command isat code memory location 650h, it can only do ajump to addresses 0000h through 07FFh (0

through 2047, decimal).

7/30/2019 8051 pres

49/126


ANL A,Direct

ANL A,Rn

ANL A,@Ri

ANL A,#Data

ANL Direct,A

ANL Direct,#Data

7/30/2019 8051 pres

50/126


ORL A,Direct

ORL A,Rn

ORL A,@Ri

ORL A,#Data

ORL Direct,A

ORL Direct,#Data

7/30/2019 8051 pres

51/126


XRL A,Direct

XRL A,Rn

XRL A,@Ri

XRL A,#Data

XRL Direct,A

XRL Direct,#Data

7/30/2019 8051 pres

52/126


CLR A

CPL A

RL ARLC A

RR ARRC A

SWAP A

I t ti S t

7/30/2019 8051 pres

53/126

Instruction Set

5 Groups



Data Transfer Group


7/30/2019 8051 pres

54/126

Data Transfer Group

MOV A,DirectMOV A,Rn

MOV A,@RiMOV A,#Data

MOV Rn,DirectMOV Rn,@Ri

MOV Rn,#Data

7/30/2019 8051 pres

55/126

Data Transfer Group

MOV Direct,DirectMOV Direct,Rn

MOV Direct,@RiMOV Direct,#Data

MOV Direct,AMOV @Ri,A

MOV @Ri,#Data

7/30/2019 8051 pres

56/126

Data Transfer Group

MOV @Ri,DirectMOV DPTR,#DATA16

MOVC A,@A+DPTRMOVC A,@A+PC

MOVX A,@RiMOVX @Ri,A

MOVX @DPTR,A

7/30/2019 8051 pres

57/126

Data Transfer Group

PUSH DirectPOP Direct

XCH A,RnXCH A,Direct

XCH A,@RiXCHD A,@Ri

Instruction Set

7/30/2019 8051 pres

58/126

Instruction Set

5 Groups



Data Transfer Group


7/30/2019 8051 pres

59/126

Boolean Variable Manipulation Group

CLR CCLR bit

SETB CSETB bit

CPL CCPL bit

7/30/2019 8051 pres

60/126


ANL C,bitANL C,/bit

ORL C,bitORL C,/bit

MOV C,bitMOV bit,C

7/30/2019 8051 pres

61/126


JC relJNC rel

JB bit,relJNB bit,rel

JBC bit,rel

Instruction Set

7/30/2019 8051 pres

62/126

Instruction Set

5 Groups



Data Transfer Group


7/30/2019 8051 pres

63/126

immediate Addressing MOV A,#20h

Direct AddressingMOV A,30h

Indirect AddressingMOV A,@R0

External DirectMOVX A,@DPTR

External IndirectMOVC A,@A+DPTR

7/30/2019 8051 pres

64/126

Program Branching Group

ACALL addr11

LCALL addr16

RETRETI

AJMP addr11LJMP addr16

SJMP rel

7/30/2019 8051 pres

65/126


JMP @A+DPTR

JZ rel

JNZ relCJNE A,Direct,rel

CJNE A,#Data,relCJNE Rn,#Data,rel

CJNE @Ri,#Data,rel

7/30/2019 8051 pres

66/126


DJNZ Rn,rel

DJNZ Direct,rel

NOP

7/30/2019 8051 pres

67/126

UNIT - IV

7/30/2019 8051 pres

68/126

UNIT - IV

8255

7/30/2019 8051 pres

69/126

8255Programmable Peripheral Interface

24 Programmable I/O pins

Three Configurable Ports - A,B & CBSR Mode

TTL Compatible

8255

7/30/2019 8051 pres

70/126


8255

7/30/2019 8051 pres

71/126


8255

7/30/2019 8051 pres

72/126


A1 A0 Select

0 0 PA0 1 PB

1 0 PC

1 1 Control reg.

8255

7/30/2019 8051 pres

73/126


Group B

PortC (Lower)

1 = Input

0 = Output

PortB

1 = Input0 = Output

Mode Selection

0 = Mode 0

1 = Mode 1

Group A

PortC (Upper)

1 = Input

0 = Output

PortA

1 = Input0 = Output

Mode Selection

00 = Mode 0

01 = Mode 1

1x = Mode 2

D0D1D2D3D4D5D6D7Control Word - General

BSR Mode Select

0 = BSR Mode Enabled

1 = BSR Mode Enabled

8255

7/30/2019 8051 pres

74/126


X X XNot Used

Bit Select000 = Bit 0

001 = Bit 1010 = Bit 2

011 = Bit 3

100 = Bit 4

101 = Bit 5

110 = Bit 6

111 = Bit 7

D0D1D2D3D4D5D6D7

0BSR Mode Selected

Control Word

BSR Mode

Bit Set/Reset1 = Set

0 = Reset

8255

7/30/2019 8051 pres

75/126


Mode 0 :-

8255

7/30/2019 8051 pres

76/126


Mode 1 :-

8255

7/30/2019 8051 pres

77/126


Mode 2 :-

8253

7/30/2019 8051 pres

78/126

8253Programmable Interval Timer

3 Independent 16bit Counters

DC - 2.6MHzBCD or Binary Counting

Programmable Counting Modes

Single Supply Operations

8253

7/30/2019 8051 pres

79/126


Pin Diagram :-

8253

7/30/2019 8051 pres

80/126


Block Diagram :-

8253

7/30/2019 8051 pres

81/126


System Interface :-

8253

7/30/2019 8051 pres

82/126


Mode Select000 = Mode 0001 = Mode 1

X10 = Mode 2

X11 = Mode 3

100 = Mode 4

101 = Mode 5

BCDM0M1M2RL0RL1SC0SC1

Select Counter00 = Select Counter 0

01 = Select Counter 1

10 = Select Counter 2

11 = Illegal

Control Word

Binary / BCD1 = BCD

0 = BinaryRead / Load00 = Counter Latching

01 = Read/Load MSB only

10 = Read/Load LSB only

11 = Read/Load LSB first then MSB

8253

7/30/2019 8051 pres

83/126


Mode 0 :-

8253

7/30/2019 8051 pres

84/126

Mode 1 :-


8253

7/30/2019 8051 pres

85/126

Mode 2 :-


8253

7/30/2019 8051 pres

86/126

Mode 3 :-


8253

7/30/2019 8051 pres

87/126

Mode 4 :-


8253

7/30/2019 8051 pres

88/126

Mode 5 :-


8279

7/30/2019 8051 pres

89/126

8279Programmable Keyboard / Display Interface

Simultaneous Keyboard & Display DriveScanned Keyboard Mode

Scanned Sensor Mode

8-Character Keyboard FIFO

Duel 8 / 16 Numerical Display

R / L Entry 16 bit Display RAM

Mode Programmable From CPU

Programmable Scan Timing

Interrupt Output on Key Entry

8279

7/30/2019 8051 pres

90/126

Pin Diagram :-


8279

7/30/2019 8051 pres

91/126

Signal Diagram :-


8279

7/30/2019 8051 pres

92/126

Block Diagram :-


8279

7/30/2019 8051 pres

93/126

System Interface :-


8251

7/30/2019 8051 pres

94/126

8251Programmable Communication Interface

Pin Diagram :-

8251

7/30/2019 8051 pres

95/126

Block Diagram :-


8251

7/30/2019 8051 pres

96/126

System Interface :-


8251

7/30/2019 8051 pres

97/126


Mode Instruction Format

8251

7/30/2019 8051 pres

98/126

8 5Programmable Communication Interface

Command Instruction Format

UNIT V

7/30/2019 8051 pres

99/126

UNIT - V

1) Stepper Motor Control

7/30/2019 8051 pres

100/126

1)Stepper Motor Control

2)Matrix Keyboard3)Dynamic 7 Segment Display

4)Analog to Digital converter5)DC Motor Control

6)LCD Display7)Serial Data Transfer

STEPPER MOTOR CONTROL

7/30/2019 8051 pres

101/126


Stepper Motor Winding Diagram

Specifications

Rotation / Excitation methods

Clockwise / Anti Clockwise Sequence

Single & Multi Winding Excitation

Driving unit Digital & Analog


7/30/2019 8051 pres

102/126


W1 W2 W3 W4

1 1 0 0

0 0 1 1

1 0 0 1

0 1 1 0

0 0 1 1

1 0 0 1

1 1 0 0

0 1 1 0


7/30/2019 8051 pres

103/126


MATRIX KEYBOARD

7/30/2019 8051 pres

104/126

MATRIX KEYBOARD

General Keyboard Structure Adv & Disadv of General Keyboard

Layout of Matrix Keyboard

Scanning and Sense Lines

Scan Sequence

Key De-bounce Methods

MATRIX KEYBOARD

7/30/2019 8051 pres

105/126

MATRIX KEYBOARD

1 2 3

4 5 6

7 8 9

0 #

Scan

Lines

Sense

Lines

MATRIXKEY

BOARDDRIVER

MATRIX KEYBOARD

7/30/2019 8051 pres

106/126

MATRIX KEYBOARD

1 2 3

4 5 6

7 8 9

0 #

RL0

RL1

SL0

RL2

SL1

SL2

SL3

Scan

Lines

Sense

Lines

MATRIX KEYBOARDRL0RL1RL2SL0SL1SL2SL3

7/30/2019 8051 pres

107/126

1000

100

RL0RL1RL2SL0SL1SL2SL3

010

001

1

2

3

0100

100

010

001

4

56

0010

100

010

001

7

8

9

00001

100

010

001

0

#

1 2 3

4 5 6

7 8 9

0 #

RL0

RL1

SL0

RL2

SL1

SL2

SL3

1 2 3

4 5 6

7 8 9

0 #

RL0

RL1

SL0

RL2

SL1

SL2

SL3

MATRIX KEYBOARD

7/30/2019 8051 pres

108/126

MATRIX KEYBOARD

MATRIX KEYBOARD

7/30/2019 8051 pres

109/126

MATRIX KEYBOARD

DYNAMIC 7 SEGMENT DISPLAY

7/30/2019 8051 pres

110/126


Seven Segment Display

Eight LEDs

Two types Common Anode & Common Cathode

Dynamic Seven Segment Display

Scan Sequence


7/30/2019 8051 pres

111/126


V

Seven Segment Display

a

b

c

d

e

f

g

dp

a b c d e f g dp Common


7/30/2019 8051 pres

112/126



7/30/2019 8051 pres

113/126



7/30/2019 8051 pres

114/126


ANALOG TO DIGITAL CONVERTER

7/30/2019 8051 pres

115/126


ADC

Working

Types Applications

Specifications No of Bits, i/p, o/p etc


7/30/2019 8051 pres

116/126


DIGITAL TO ANALOG CONVERTER

7/30/2019 8051 pres

117/126

DIGITAL TO ANALOG CONVERTER

DC MOTOR CONTROL

7/30/2019 8051 pres

118/126

DC MOTOR CONTROL

DC Motor

Speed Control Methods

Advantage of PWM Method Driving Circuit

DC MOTOR CONTROL

7/30/2019 8051 pres

119/126

O O O O

LCD DISPLAY

7/30/2019 8051 pres

120/126

Principle of LCD 16x2 LCD

LCD Module Driver & Screen

RAM

Character Molding

Display Type Cursor, L/R Entry etc

LCD DISPLAY

7/30/2019 8051 pres

121/126

LCD DISPLAY

7/30/2019 8051 pres

122/126

LCD DISPLAY

7/30/2019 8051 pres

123/126

Pin number Symbol Level I/O Function

7/30/2019 8051 pres

124/126

1 Vss - - Power supply (GND)

2 Vcc - - Power supply (+5V)

3 Vee - - Contrast adjust

4 RS 0/1 I0 = Instruction input,

1 = Data input

5 R/W 0/1 I0 = Write to LCD module,

1 = Read from LCD module

6 E 1, 1->0 I Enable signal

7 DB0 0/1 I/O Data bus line 0 (LSB)

8 DB1 0/1 I/O Data bus line 1






14 DB7 0/1 I/O Data bus line 7 (MSB)

Instruction

Code

DescriptionExecuti

on timeRS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

Clear0 0 0 0 0 0 0 0 0 1

Clears display and returns cursor to the home position (address1 64 S

7/30/2019 8051 pres

125/126

display0 0 0 0 0 0 0 0 0 1

p y p (

0).1.64mS

Cursor

home0 0 0 0 0 0 0 0 1 *

Returns cursor to home position (address 0). Also returns

display being shifted to the original position. DDRAM contents

remains unchanged.

1.64mS

Entry mode

set0 0 0 0 0 0 0 1 I/D S

Sets cursor move direction (I/D), specifies to shift the display

(S). These operations are performed during data read/write.40uS

Display

On/Off

control0 0 0 0 0 0 1 D C B

Sets On/Off of all display (D), cursor On/Off (C) and blink of

cursor position character (B).40uS

Cursor/disp

lay shift0 0 0 0 0 1 S/C R/L * *

Sets cursor-move or display-shift (S/C), shift direction (R/L).

DDRAM contents remains unchanged.40uS

Function

set0 0 0 0 1 DL N F * *

Sets interface data length (DL), number of display line (N) and

character font(F).40uS

Set

CGRAM

address0 0 0 1 CGRAM address

Sets the CGRAM address. CGRAM data is sent and received

after this setting.40uS

Set

DDRAM

address0 0 1 DDRAM address

Sets the DDRAM address. DDRAM data is sent and received

after this setting.40uS

Read busy-flag and

address

counter

0 1 BF CGRAM / DDRAM addressReads Busy-flag (BF) indicating internal operation is being

performed and reads CGRAM or DDRAM address counter

contents (depending on previous instruction).

0uS

Write to

CGRAM or

DDRAM1 0 write data Writes data to CGRAM or DDRAM. 40uS

Read from

CGRAM or

DDRAM1 1 read data Reads data from CGRAM or DDRAM. 40uS

LCD DISPLAY

7/30/2019 8051 pres

126/126

8051 pres

Documents