8086 lecture notes 13

1DEVELOPMENT OF THE INTEL X86 FAMILY MICROPROCESSOR

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DEVELOPMENT OF THE INTEL X86 FAMILY MICROPROCESSOR

13.1 Introduction13.2 Programming Model13.3 Addressing Modes13.4 Instruction Set13.5 The X86 Hardware13.6 PC Motherboard Architecture

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13.1 Introduction

The 8088 and 8086 evolved into faster versions, versions with greater memory addressing space, versions which process 32-bit data words.

IBM introduced the PC/AT using the 80286 in 1984. One of the features introduced with the 80286 was real and protected modes of operation, and yet another feature added hardware multitasking.

The 80386 has a 32-bit data bus and a 32-bit address bus, and it uses 32-bit internal registers.

The 386 microprocessors offered advance virtual memory, advanced protected mode, and higher speeds.

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13.1 Introduction

The 486 is basically a large integrated circuit which contains a fast 386 processor, a math coprocessor, a memory management unit (MMU), and an 8-Kbyte cache memory.

The 486 achieves its high-speed operation from faster clock speeds, an internal pipelined architecture, and the use of reduced instruction set computing (RISC) to speed up the internal microcode.

Intel elected to name the 586 device Pentium. The Pentium uses superscalar architecture incorporating a dual-pipelined processor which lets the Pentium process more than one instruction per clock cycle.

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13.1 Introduction

The Pentium are implemented with 8-Kbyte data and 8-Kbyte code caches on chip that is also a feature designed to improve processing speed.

The Pentium has a 64-bit data bus. This means that it can perform data transfers with an external device twice as fast as a processor with a 32-bit data bus.

A new advanced computing technique used in the Pentium is called branch prediction. Using branch prediction, the Pentium makes an educated guess where the next instruction following a conditional instruction will be.

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13.1 Introduction

Major attributes of the X86 processorsAttribute 8088 8086 80286 386SX 386DX 486SX 486DX Pentium

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13.2 Programming Model

The 8088 and 8086 define the base programming model for the entire X86 family of microprocessors.

The 386, 486, and Pentium uses 32-bit registers. The 8 general-purpose registers are called the EAX, EBX, ECX, EDX, ESI, EDI, ESP, EBP registers. Each register can be addressed in 1-, 8-, 16-, or 32-bit modes.

The first five bits of the X86 flag register are identical to the flag bits in the 8085 8-bit microprocessor.

To give the X86 processors even greater speed, the processors include various levels of instruction prefetching and data caching.

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13.2 Programming Model The X86 programming model as described by the

base register set

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13.2 Programming Model The X86 flag (status) register

80858086

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13.3 Addressing Modes

The X86 processors can address immediate data, I/O ports, registers, and memory locations using different addressing modes.

The 8088/8086 addresses 1 Mbyte (220). The 286 addresses 16 Mbytes (224), and members after the 386 can address 4 Gbytes (232).

The X86 processors have a separate ALU to perform calculation of memory address, so the main ALU is free to perform data calculation.

Each of the newer X86 processors has two fundamental modes of operation. They are called the real mode and protected mode.

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In the real mode, all processors are limited to addressing 1 Mbyte of memory. In this mode they work just like the 8086. In the protected mode, they are able to address many more memory locations.

To put an X86 processor in the protected mode, the protection enable bit (bit 0) in the machine status register must be set to logic 1.

Once the protection enable bit is set, it can be cleared only by resetting the processor. This makes entering the protected mode a one-way street.

In the protected mode, the X86s MMU is used to allow the processor to address physical memory greater than 1 Mbyte and to allow the programmer to use virtual memory.

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In the protected mode, the address in the segment register points to a memory location called a segment descriptor table. Data in this table is used in place of the segment base address data to build the memory address.

The segment descriptor table gives the X86 programmer one more way to keep different addressing for different kinds of use and therefore to protect the data.

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The upper 13 bits of the segment register data are used to select a particular segment descriptor. The first three bits request a priority level (RPL0, RPL1) and select either a global descriptor table or a local descriptor table.

13-bit segment description address

3 2 1 0

RPL0RPL1GDT or LDT

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Each segment descriptor table contains 8 bytes. The 8 bytes provide a 24-bit (286) or 32-bit (386 and higher) segment base address plus additional information.

The structure of the segment descriptor table

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Addressing memory using the segment descriptor tables

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There is one segment descriptor register for each segment register.

If the memory does not really exist, then a subprogram is used to load the needed information from mass storage into the appropriate section of physical memory.

Segments for the 286 are limited to 64 Kbytes. Segments for the 386 and newer processors can be either up to 1 Mbyte or up to 4 Gbytes long.

The X86 processors offer four levels of privilege for any form of memory access. This is used to help the programmer when writing operation system software and software for a multi-user or multitasking environment.

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The X86 privilege levels. PL0 is the highest privilege; PL3 is the lowest privilege.

PL3

PL2

PL1

PL0

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Different privilege layers for a multi-user or multitasking operating system.

Applications

Operatingsystems

System

Kernel most

privilege

Services

Extensions

Software

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13.4 Instruction Set

The X86 processors are upwardly compatible; that is, software written for an earlier version will always run on a later version. The newer processors have a special mode (the real mode) which allows them to operate as though they were an 8086.

There are eight major types of X86 instructions: Data transfer Arithmetic Logical and shift-rotate String manipulation Bit manipulation Control transfer High-level language support Processor control

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13.4 Instruction Set Evolution of the X86 family instruction set

BaseInstruction

set

8086

Base +extendedInstruction

set


set

System controlInstruction set

80286

Protected mode

Real mode


set

Base +Extended + 80386Specific Instruction

set


80386

Protected mode

Real mode


set

Base + Extended + 80386 + 80486

Specific Instructionset


80486

Protected mode

Real mode

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13.4 Instruction Set The X86 data transfer instructions

Mnemonic Description 8088/ 286 386 486 Instruction8086 Subtype

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13.4 Instruction Set The X86 data transfer instructions


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13.4 Instruction Set The X86 data transfer instructions some

new instructionsPOPA, PUSHA Exchange all register data with

the stack.BSWP Byte swap, reorder the 4 bytes in a 32-

bit word.LAR Load the access rights from a segment

descriptor table into a general-purpose register.LGDT, LIDT, LLDT, SGDT, SIGT, SLGT

Transfer the contents of a segment descriptor table (Global, Interrupt, Local).LMSW Load machine status word.

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13.4 Instruction Set The X86 arithmetic instructions


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13.4 Instruction Set The X86 arithmetic instructions


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13.4 Instruction Set The X86 logical instructions

Mnemonic Description 8088/ 286 386 486 8086

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13.4 Instruction Set The X86 shift and rotate instructions


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13.4 Instruction Set The X86 string manipulation instructions


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13.4 Instruction Set The X86 bit manipulation instructions


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13.4 Instruction Set The X86 control transfer instructions


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13.4 Instruction Set The X86 control transfer instructions Five

unconditional jumps

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13.4 Instruction Set The X86 control transfer instructions Five

unconditional jumps

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13.4 Instruction Set The X86 control transfer instructions Four iteration

control instructions

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13.4 Instruction Set The X86 control transfer instructions Interrupt vector

Interrupt Vector Instruction or Condition Which First ProcessorNumber Interrupt Type Can Cause Interrupt to Use This

Interrupt

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13.4 Instruction Set The X86 high-level language support instructions


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13.4 Instruction Set The X86 processor control instructions


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13.5 The X86 Hardware The maximum and minimum mode of the 8088/8086

was dropped from the 286 and from later versions of the X86 processor family.

The 286 and newer processors do not use a multiplexed address-data bus.

The newer microprocessors in the X86 family are usually packaged as:Pin grid array (PGA)Quad flat pack (QFP)Plastic leadless chip carrier (PLCC)

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13.5 The X86 Hardware Typical packages of newer X86 processors

A 114-pin pin grid array package A 132-pin quad flat pack

A 132-pin plastic leadless chip carrier

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PGA

PLCC

QFP

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The X86 processor packages and pin count

Attribute 8088 8086 286 386SX 386DX 486DX Pentium

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13.5 The X86 Hardware The X86 processor pin assignment

Processor Signal Input or 8086 (Max 286 386 486Function Output Mode)

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13.5 The X86 Hardware The X86 processor pin assignment

Processor Signal Input or 8086 (Max 286 386 486Function Output Mode)

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13.5 The X86 Hardware The 80486SX processor pin layout

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13.5 The X86 Hardware The 80486SX processor pin numbering

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13.5 The X86 Hardware The 80486SX processor block diagram

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13.5 The X86 Hardware Block diagram of a maximum mode 8086 system

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13.5 The X86 Hardware Implementing the 486DX-based PC with VLSI parts

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13.5 The X86 Hardware 80286 processor summary 2nd generation processor Introduced in 1981 CPU behind IBM AT Throughput of original IBM AT (6MHz) was about 500% of

IBM PC (4.77MHz) Level of integration: 134k transistors (29k in 8086) 16-bit processor, available in higher clock frequencies: 25MHz Fully backwards compatible to 8086 Improved instruction set and execution Real mode and protected mode 16MB addressable physical memoryOn-chip MMU (1GB virtual memory) Non-multiplexed address-bus and data-bus

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13.5 The X86 Hardware 80386 processor summary 3rd generation processor Introduced in 10/1985 Full 32-bit processor 275k transistors. CMOS. 132-pin PGA package Clock speeds: 16-33MHz Protected Mode for Multitasking support Real mode (native 8086 mode) Processor powers up in real mode

System management mode Power management or system security Processor switches to separate address space, while

saving the entire context of the currently running program or task

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13.5 The X86 Hardware 80486 processor summaryIntroduced in 1989High integration

On-chip 8K Code and Data cache Floating Point Unit Paged, Virtual Memory Management

Multiprocessor support Multiprocessor Instructions Cache Consistency Protocols

Longer prefetch queue (32-bytes as opposed to 16 on the 80386)Higher frequency operation: up to 120MHz>1.2M transistors, 0.8m CMOS. 168-pin PGA.

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13.5 The X86 Hardware Pentium processor summary 32-bit Microprocessor

32-bit addressing 64-bit data bus

Superscalar architecture Two pipelined integer units Capable of under one clock per instruction Pipelined floating point unit

Separate code and data caches 8K code, 8K write back data 2-way 32-byte line size MESI cache consistency protocol

Advance design features Branch prediction

237-pin PGA

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13.6 PC Motherboard Architecture Top level PC system architecture

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13.6 PC Motherboard Architecture Top level PC system architectureThe integration of chipset has reduced a chipset

to just 2 main components--the North Bridge (NB) and the South Bridge (SB). In the case of the North Bridge, the chip connects

the front side bus [FSB] of the CPU to the DRAM bus, the AGP graphics bus, and the South Bridge.The South Bridge is intended as the place to

integrate all the (slower) peripherals like IDE, ISA, USB, etc.The North Bridge is also called the Memory

Controller Hub, and the South Bridge has become the I/O Controller Hub.

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13.6 PC Motherboard Architecture The North BridgeFour interface buses

CPU interface The South Bridge interface The DRAM system memory interface The Accelerated Graphics Port interface

The function of the chip is to serve as a traffic cop for data moving between the four buses.With enough buffering and some complex

arbitration circuitry, a good North Bridge can provide enough concurrency to insure that the DRAM is used efficiently.

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13.6 PC Motherboard Architecture The North BridgeNorth Bridge is interfaced to the South Bridge with

PCI interface. New interfaces include INTELs SB interface

which is an 8-bit port, running at 66 MHz and transferring 4 bytes per clock, and AMDs HyperTransport Technology that provides 2 channels for full-duplex operation. VIA has defined their own South Bridge interface

that they call "V-Link". Very similar to Intel's approach, this interface provides 266 MBs/sec of bandwidth.

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13.6 PC Motherboard Architecture The North BridgeRight now, the Pentium 4 chipsets only support

RDRAM, though Intel is working on a SDRAM version (code-named "Brookdale").For now, most chipsets support PC133 SDRAM's

and provide 1.064 GB/sec of memory bandwidth from the 64-bit, 133MHz memory interface. Support for DDR DRAM doubles this to 2.1 GB/sec.INTEL developed the AGP interface as a way to

help control the system partitioning for graphics.AGP would allow a graphics controller to use

system memory for storing graphics texture information.

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13.6 PC Motherboard Architecture The North BridgeOriginally designed as a 66 MHz interconnect,

architecturally similar to a dedicated PCI bus, AGP performance soon scaled to allow 2 samples/clock (AGP 2X) and then 4 samples/clock (AGP 4X). With a 32-bit (4 byte) data path running at 66MHz and capable of 4 transfers per clock, the 4X interface yields 1.056 GBs/sec). Some low-cost motherboard implementations

remove the graphics memory entirely and run with a "Unified Memory Architecture (UMA)".

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13.6 PC Motherboard Architecture The South BridgeWhile the North Bridge handles high-speed

memory arbitration, the South Bridge connects with all the disparate peripherals.Many new motherboards have dropped the ISA

bus entirely, but a lot of South Bridge chips still provide the bus as an option for the motherboard designer.The PCI devices are integrated into the South

Bridge of many chipsets, including the IDE controller, USB controller, SMBus controller, etc.Most chipsets create an internal PCI-to-PCI

bridge, so that these devices don't take up resources from the main PCI bus.

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13.6 PC Motherboard Architecture The South BridgeINTEL invented the Low Pin Count Interface

(LPC) for the South Bridge that is a simple 4-bit interface and is mainly used for connecting to the Super I/O chip. The Super I/O is where the really old legacy

devices live, including the serial ports, parallel port, game port, PS/2 mouse/keyboard, infrared interface, and floppy disk controller.

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13.6 PC Motherboard Architecture The South BridgeThe BIOS is low-level software that controls

devices on the motherboard. The processor executes the BIOS code when the PC is first booted, allowing memory testing and configuration of peripherals. INTEL calls their BIOS chip the Firmware Hub

(FWH), but it is basically the BIOS running in FLASH (reprogrammable) memory. On an INTEL chipset, the FWH shares pins with the LPC interface.

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13.6 PC Motherboard Architecture The South BridgeThe South Bridge chip usually have one or two

USB controllers, each able to manage 2 motherboard connectors. USB is designed to daisy-chain through external

hubs to minimize the number of wires that must be connected to the PC. The term Integrated Drive Electronics (IDE)

means that most of the control for disk drive has been integrated onto the drive's circuitry, instead of being part of the motherboard or add-in card.

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13.6 PC Motherboard Architecture The South BridgeThe Audio Codec (AC) Link chipset is designed to

allow a digital connection to simple off-chip mixed signal (analog/digital) electronics for audio and telephony (modem/networking).The current version is AC'97 2.2, and it provides a

5-signal interface to an external codec (compression/decompression). In the case of audio, the AC Link would connect to a chip that includes a codec and digital-to-analog (D/A) converters for driving audio speakers and analog-to-digital (A/D) converters for sampling a microphone or other audio analog inputs.

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13.6 PC Motherboard Architecture The South BridgeIntegrated internet controller

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13.6 PC Motherboard Architecture Other motherboard featuresVRM (Voltage Regulator Module)

The VRM is a programmable voltage regulator, taking a set of 5 VID (voltage identification) signals that are coded to generate a precise voltage.

ClocksConnectorsJumpers

Most new motherboards now offer a "jumper-less" mode where all functions are controlled through the BIOS.

Riser cards Low-cost cards that provide external connectors to audio

devices, modems or networking.

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13.6 PC Motherboard Architecture Motherboard case study:Intel D815EEA

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13.6 PC Motherboard Architecture Motherboard case study: Intel D815EEA

Processor Socket 82815E Graphics and Memory Controller Hub (GMCH) 82801BA I/O Controller Hub (ICH2) 82802AB Firmware Hub (FWH) SMSC LPC47M102 I/O Controller PCI and CNR Slots Memory Sockets AGP Connector Optional Audio Chips Digital Video Out (DVO) Connector IDE and Floppy Connectors Onboard Speaker and Battery Front Panel Connectors Rear Panel Connectors Jumpers Power Supply

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13.6 PC Motherboard Architecture Motherboard case study:ASUS A7M266

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13.6 PC Motherboard Architecture Motherboard case study: ASUS A7M266Support for AMD Socket A Processor, 266 MHz

FSB and a Big HeatsinkSpecial ASUS Chip for Hardware Monitoring AMD 760 North Bridge with a VIA VT82C686B

South Bridge BIOS Allows 1 MHz Frequency Increments Audio Modem Riser (AMR) Allows Low-Cost

Audio or Modem

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13.6 PC Motherboard Architecture Motherboard case study: (2007)ASUS M2N32-SLI Deluxe

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13.6 PC Motherboard Architecture Motherboard case study: ASUS M2N32-SLI DeluxeBased on the NVIDIA nFOrce 590 MCP

Northbridge chipset.With support for 32 and 64-bit computing. Supports dual PCI Express x16 slots running at

full speed to liberate graphics cards from the narrow bandwidth platform of x8 speed only4 DIMM sockets using Dual Channel 240-pin

DDR2 with a total capacity of up to 4GB Built in IDE facilities that support Ultra DMA

33/66/100/133

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13.6 PC Motherboard Architecture Features of modern motherboardsSystem on a chip (SOC)A sealed-box PC with Device Bay to allow

peripheral connections.Quad-Rate DRAMUSB 2.0PCI-X for 1 GB/sec of bandwidthMultiple processors

Reference: http://www.extremetech.com/PC Motherboard Technology by J. Scott Gardner

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8086 lecture notes 13

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