14.1: A 0.048-mm2 3-mW Synthesizable Fractional-N PLL with a Soft Injection-Locking Technique© 2015 IEEE International Solid-State Circuits Conference 0 of31

A 0.048-mm2 3-mW Synthesizable

Fractional-N PLL with a Soft

Injection-Locking Technique

Wei Deng, Dongsheng Yang, Aravind

Tharayil Narayanan, Kengo Nakata,

Teerachot Siriburanon, Kenichi Okada, and

Akira Matsuzawa

Tokyo Institute of Technology, Japan

14.1: A 0.048-mm2 3-mW Synthesizable Fractional-N PLL with a Soft Injection-Locking Technique© 2015 IEEE International Solid-State Circuits Conference 1 of31

Outline

• Introduction

• Concept of Soft Injection Locking

• Circuit Implementations

• Measurement Results

• Conclusion

14.1: A 0.048-mm2 3-mW Synthesizable Fractional-N PLL with a Soft Injection-Locking Technique© 2015 IEEE International Solid-State Circuits Conference 2 of31

Introduction

• Why High Performance PLL

– Clock generation/distribution

• Key Specifications for SoC Clocking

– Small area

– Low power consumption

– Low jitter

– Insensitive over environment variations

– Scalable with technology advancement

14.1: A 0.048-mm2 3-mW Synthesizable Fractional-N PLL with a Soft Injection-Locking Technique© 2015 IEEE International Solid-State Circuits Conference 3 of31

All-digital PLLs

• TDC-based architecture

– Taking advantages of digital circuits

– Compact chip area

– Cannot fully utilize digital design flow

• Layout uncertainty caused by Auto Place &

Route degrades TDC and DCO linearity.

14.1: A 0.048-mm2 3-mW Synthesizable Fractional-N PLL with a Soft Injection-Locking Technique© 2015 IEEE International Solid-State Circuits Conference 4 of31

Injection Locking Technique

𝒇𝐢𝐧𝐣 = 𝟔 (𝑵(𝑵 − 𝟏))

𝟐𝝅· 𝒇𝐫𝐞𝐟

[N.D. Dalt, TCAS II 2014]

Offset Frequency

Ph

as

e n

ois

e

Injection

locked

Free-running

VCO

REF Injection

locked

14.1: A 0.048-mm2 3-mW Synthesizable Fractional-N PLL with a Soft Injection-Locking Technique© 2015 IEEE International Solid-State Circuits Conference 5 of31

Phase Noise Comparison

• JitterTDC-PLL=6.4ps JitterIL-PLL=1.5ps

Freqref =100MHz

FreqDCO=1GHz

FOMDCO=-153 dB

(-90dBc/Hz at 1MHz,

0.5mW)

Frequency Offset [Hz]

Ph

as

e N

ois

e [

dB

c/H

z]

10M 100M1M100k

-70

-90

-110

-130

IL-PLL

TDC-PLL

Free-running

oscillator

BW=2MHz

BW=40MHz

14.1: A 0.048-mm2 3-mW Synthesizable Fractional-N PLL with a Soft Injection-Locking Technique© 2015 IEEE International Solid-State Circuits Conference 6 of31

Injection Method

• Pulse Injection [B. Helal, et al., JSSC 2009]

• Multiplying DLL [S. Ye, et al., JSSC 2002]

• Edge Injection [W. Deng, et al., ISSCC 2014]

14.1: A 0.048-mm2 3-mW Synthesizable Fractional-N PLL with a Soft Injection-Locking Technique© 2015 IEEE International Solid-State Circuits Conference 7 of31

Integer-N Operation

Reference

VCO

Reference

D D D D...

e.g. N=3

14.1: A 0.048-mm2 3-mW Synthesizable Fractional-N PLL with a Soft Injection-Locking Technique© 2015 IEEE International Solid-State Circuits Conference 8 of31

Sub-Integer-N Operation

[P. Park, et al., ISSCC 2012]

Reference

D D D D...

...

P0 P1 P2

e.g. N=3+(1/M)

Reference

VCO

P0

P1

P2

...

14.1: A 0.048-mm2 3-mW Synthesizable Fractional-N PLL with a Soft Injection-Locking Technique© 2015 IEEE International Solid-State Circuits Conference 9 of31

Phase Domain (Integer-N)

P0 P0 P0 P0 P0 P0 P0 …

2·Tref 3·Tref

N·2π

2N·2π

4N·2π

fPLL=N·fref

Tref 4·Tref 5·Tref

fPLL

t

3N·2π

P0

P0

P0

P0

P0

14.1: A 0.048-mm2 3-mW Synthesizable Fractional-N PLL with a Soft Injection-Locking Technique© 2015 IEEE International Solid-State Circuits Conference 10 of31

Phase Domain (Sub-Integer-N)

P0 P1 P2 P3 … P0 P1 …

fPLL=(N+1/M)·fref

(N+1/M)·2π

2·Tref 3·TrefTref 4·Tref 5·Tref

fPLL

t

2·(N+1/M)·2π

3·(N+1/M)·2π

4·(N+1/M)·2π

P1

P2

P3

P4

P0

14.1: A 0.048-mm2 3-mW Synthesizable Fractional-N PLL with a Soft Injection-Locking Technique© 2015 IEEE International Solid-State Circuits Conference 11 of31

Phase Domain (Fractional-N)

P0 P0 P1 P1 P2 P2 P3 …

fPLL=(N+0.5/M)·fref

N·2π

2·Tref 3·TrefTref 4·Tref 5·Tref

fPLL

t

(2·N+1/M)·2π

(3·N+1/M)·2π

(4·N+2/M)·2π

P0

P1

P1

P2

P0

14.1: A 0.048-mm2 3-mW Synthesizable Fractional-N PLL with a Soft Injection-Locking Technique© 2015 IEEE International Solid-State Circuits Conference 12 of31

Time Domain (Fractional-N)

• Spur is caused by “hard” switching

Reference

VCO

P1

P2

...

...

14.1: A 0.048-mm2 3-mW Synthesizable Fractional-N PLL with a Soft Injection-Locking Technique© 2015 IEEE International Solid-State Circuits Conference 13 of31

Proposed Soft Injection

Soft

Injection

ReferenceInjection

Signal

Reference

Locked

Soft

Injection signal

14.1: A 0.048-mm2 3-mW Synthesizable Fractional-N PLL with a Soft Injection-Locking Technique© 2015 IEEE International Solid-State Circuits Conference 14 of31

“Hard” vs “Soft” InjectionInjection at f10 Injection at f0

Soft injection

f10 w/o inj

f10 w/ inj

Reference

f10 w/o inj

f10 w/ inj

Conventional “hard” injection

Proposed “soft” injection

14.1: A 0.048-mm2 3-mW Synthesizable Fractional-N PLL with a Soft Injection-Locking Technique© 2015 IEEE International Solid-State Circuits Conference 15 of31

Injection Strength

• Soft injection signal level determines

injection strength

• Stronger injection strength leads to

larger phase shift

Soft Injection Signal

14.1: A 0.048-mm2 3-mW Synthesizable Fractional-N PLL with a Soft Injection-Locking Technique© 2015 IEEE International Solid-State Circuits Conference 16 of31

Fractional-N Operation (Hard)

(3N+ 5/28)·2π

(3N+ 4/28)·2π

(3N+4.5/28)·2π

fPLL

(3N+ 3/28)·2π

(3N+ 6/28)·2π

(3N+ 7/28)·2π

(3N+ 2/28)·2π

Available injection phaseSelected injection phase

3·Tref t

fPLL=(N+1.5/28)·fref

14.1: A 0.048-mm2 3-mW Synthesizable Fractional-N PLL with a Soft Injection-Locking Technique© 2015 IEEE International Solid-State Circuits Conference 17 of31

Fractional-N Operation (Soft)

(3N+ 5/28)·2π

(3N+ 4/28)·2π

(3N+4.5/28)·2π

fPLL

(3N+ 3/28)·2π

(3N+ 6/28)·2π

(3N+ 7/28)·2π

(3N+ 2/28)·2π

Available injection phaseSelected injection phase

3·Tref t

fPLL=(N+1.5/28)·fref

14.1: A 0.048-mm2 3-mW Synthesizable Fractional-N PLL with a Soft Injection-Locking Technique© 2015 IEEE International Solid-State Circuits Conference 18 of31

PLL with Soft Injection

• Cascading topology

Gating

DSM

Soft-Injection

Frequency-

locked Loop

MDLL

Reference

Clock

0.8-

1.7GHz

3 28

Phases1× ~ 12×

100-600MHz

14.1: A 0.048-mm2 3-mW Synthesizable Fractional-N PLL with a Soft Injection-Locking Technique© 2015 IEEE International Solid-State Circuits Conference 19 of31

Soft Injection Generator

VDD

...

MU

X

MU

X

Injection

signal

Digital varactor

...

...

D Q

Reset

N1·REF Gating

Array

• Effective soft injection signal is generated by soft

injection generator and gating array.

14.1: A 0.048-mm2 3-mW Synthesizable Fractional-N PLL with a Soft Injection-Locking Technique© 2015 IEEE International Solid-State Circuits Conference 20 of31

Fractional-N Controller

DSM

FCW

Deglitching

Mapping

Sub

IntegerDither

MDLL

Retimer

REFGating

Array

14.1: A 0.048-mm2 3-mW Synthesizable Fractional-N PLL with a Soft Injection-Locking Technique© 2015 IEEE International Solid-State Circuits Conference 21 of31

Gating Array

...

Interpolative phase coupled DCO

GatingGating Gating

PI PI

PI

PI

DAC

Frac-N

Controller

Soft Injection

generator

14.1: A 0.048-mm2 3-mW Synthesizable Fractional-N PLL with a Soft Injection-Locking Technique© 2015 IEEE International Solid-State Circuits Conference 22 of31

Interpolative phase coupled DCO

[W. Deng, et al., ISSCC 2014]

PI

• Standard cell design

• Interpolative phase

coupling for

accurate phase

14.1: A 0.048-mm2 3-mW Synthesizable Fractional-N PLL with a Soft Injection-Locking Technique© 2015 IEEE International Solid-State Circuits Conference 23 of31

Design Procedure

Verilog netlist

(gate-level)

Verilog

RTL

Verilog netlist

(gate-level)

DCO DAC

Logic

Logic

Logic Synt. Tool

GDSII

P&R Tool

Netlist

14.1: A 0.048-mm2 3-mW Synthesizable Fractional-N PLL with a Soft Injection-Locking Technique© 2015 IEEE International Solid-State Circuits Conference 24 of31

Chip Microphotograph

65nm CMOS technology

275mm175m

m

14.1: A 0.048-mm2 3-mW Synthesizable Fractional-N PLL with a Soft Injection-Locking Technique© 2015 IEEE International Solid-State Circuits Conference 25 of31

Phase Noise

Frequency: 1.2576 GHz

Integrated Jitter: 2.5 ps

PDC: 2.9 mW

14.1: A 0.048-mm2 3-mW Synthesizable Fractional-N PLL with a Soft Injection-Locking Technique© 2015 IEEE International Solid-State Circuits Conference 26 of31

Spur against Inj. Strength

(Soft) (Hard)

14.1: A 0.048-mm2 3-mW Synthesizable Fractional-N PLL with a Soft Injection-Locking Technique© 2015 IEEE International Solid-State Circuits Conference 27 of31

Jitter against Inj. Strength

(Soft) (Hard)

14.1: A 0.048-mm2 3-mW Synthesizable Fractional-N PLL with a Soft Injection-Locking Technique© 2015 IEEE International Solid-State Circuits Conference 28 of31

Comp. of Synthesizable PLLs

This work [1] [2]

Technology 65nm 65nm 65nm

Power

[mW]2.9

@1.2576GHz

0.78 @0.9GHz

13.7@2.5GHz

Area [mm2] 0.048 0.0066 0.04

Integ. Jitter [ps] 2.5 1.7 3.2*

FOM [dB] -227 -237 -219*

Topology Soft-IL IL TDC-based

Type Frac-N Integer-N

Synthesized? YES

[1] W. Deng, et al., ISSCC 2014 [2]Y. Park, et al., CICC 2011

*FOM is calculated based on RMS jitter.

14.1: A 0.048-mm2 3-mW Synthesizable Fractional-N PLL with a Soft Injection-Locking Technique© 2015 IEEE International Solid-State Circuits Conference 29 of31

Performance Comparison

14.1: A 0.048-mm2 3-mW Synthesizable Fractional-N PLL with a Soft Injection-Locking Technique© 2015 IEEE International Solid-State Circuits Conference 30 of31

Conclusion

• A synthesizable fractional-N PLL with

a soft-injection locking technique is

presented.

• The soft injection locking technique

provides potentials for future clock

generation circuit designs.

14.1: A 0.048-mm2 3-mW Synthesizable Fractional-N PLL with a Soft Injection-Locking Technique© 2015 IEEE International Solid-State Circuits Conference 31 of31

Acknowledgement

This work is partially supported by

STARC, MIC, SCOPE, MEXT, STAR, and

VDEC in collaboration with Cadence

Design Systems, Inc., Synopsys, Inc., and Mentor Graphics, Inc.