a 212mpixels/s 4096×2160p multiview video encoder chip for 3d/quad hdtv applications
DESCRIPTION
A 212MPixels/s 4096×2160p Multiview Video Encoder Chip for 3D/Quad HDTV Applications. The way to provide more vivid and complete scene perception to users Larger TV resolution Quad Full HDTV (QFHD) More dimensions of view point 3D HDTV Challenges. Proposed Architecture. Results. - PowerPoint PPT PresentationTRANSCRIPT
A 212MPixels/s 4096×2160p Multiview Video Encoder Chip for 3D/Quad HDTV Applications
• The way to provide more vivid and complete scene perception to users– Larger TV resolution Quad Full HDTV (QFHD)– More dimensions of view point 3D HDTV
• Challenges
19
System Bus
ProcessorMemoryInterface
Off-ChipMemory
IntegerME
FractionalME
IntraPrediction
EntropyCoding/
Deblocking
1st Stage 2nd Stage 3rd Stage 4th Stage
1st Stage 2nd Stage 3rd Stage
On-Chip SRAM
Y.-W. Huang et. al. “A 1.3TOPS H.264/AVC single-chip encoder for HDTV applications,” ISSCC2005
High System Memory Bandwidth: 5.12GB/s
Large On-Chip SRAM area: 1.1MB High On-Chip
SRAM Access: 52GB/s
Large Hardware Cost: 10.6M gates
Low throughput: 27.6M pixel/s << 212M pixels/s
Cannot support complex MVC structures
Proposed Architecture
IMDE: Integer ME/DE
FMDE: Fractional ME/DE
IP: Intra Prediction
MDC: Motion/DisparityCompensation
REC: Reconstruction
EC: Entropy Coding
DB: Deblocking
Pf: Prefetch
IPCore
RECCore
View-Parallel MB-Interleaved CTRL
Cur. MBBuf.
Cur. MBBuf.
128-Bit System Bus Interface
Stage 4: FMDE Pf
Stage 2: IMDEle Stage 1: IMDE Pf
Stage 5:FMDE
Stage 7:REC
Stage 8:Dual-EC&DB
Stage 3: NOPpp
ECCore 1
123123Bitstream Buf.
ECCore 2
123123Bitstream Buf.
DBCore
DB MB SRAM
MDCCore
MVC Encoder Chip
Video InputProcessorBus Mater/SlaveDRAM Controller ExternalBus
System ExternalMemory
View Cache SRAM 1View Cache SRAM 1View Cache SRAM 1View2 Cache SRAM
FMDECore
Cur. LumaMB Buf.
IMDEPrefetch
View Cache SRAM 1View Cache SRAM 1View Cache SRAM 1View1 Cache SRAM
IMDECore
Cur. LumaMB Buf.
FMDEPrefetch
ResidueMB SRAM
ResidueMB SRAM
EC Select
MDC MBSRAM
Rec. MBSRAM
Stage 6:IP&
MDC
ResultsEC1
EC2IMDE
FMDE
LUMAMDC
REC
CACHECTRL1
CACHECTRL2
DB
IP
CHROMAMDC
VPMBICTRL
VIEW1CACHESRAM
VIEW2CACHESRAM
DB SRAM
EC1SRAM
EC2SRAM
MDC SRAM
• High performance– H.264/AVC Multiview High Profile compression– Quad HDTV 4096×2160p, 24fps@280MHz on 11.46mm2
• Efficient techniques– VPMBI scheduling with 8-stage MB pipelining– Cache analogy to search window buffer
10
100
1000
Full Search
Hierarchical Search
1080p720p 4096x2160p
MVCChip
ISSCC05
ISSCC07
ISSCC08
On-chip SRAM Size (KB)
Previous Work
MVC Chip
39%Reduction
79%Reduction
83%Reduction
94%Reduction
0.1
1
10
100
Full Search
Hierarchical Search
1080p720p 4096x2160p
External Memory Bandwidth (GB/s)
ISSCC05
ISSCC07
ISSCC08
Previous Work
MVC Chip
MVCChip
Processing Capability (Resolution)
39%Reduction
79%Reduction