Matsuzawa& Okada Lab.

Matsuzawa Lab.Tokyo Institute of Technology

Matsuzawa& Okada Lab.

Matsuzawa Lab.Tokyo Institute of Technology

A Fractional-N Sub-Sampling PLL using Pipelined Phase-Interpolator

with a FoM of -246dB�

A.T. Narayanan, M. Katsuragi, K. Kimura, S. Kondo, K. T. Korkut, K. Nakata, W. Deng,

K. Okada, and A. Matsuzawa �

Tokyo Institute of Technology Japan�

1 ESSCIRC2015 41th European Solid-State Circuits Conference

[C4L-A] A Fractional-N Sub-Sampling PLL using a Pipelined Phase-Interpolator with a FoM of -246dB

Contents

!  Motivation !  Conventional Fractional-N PLLs !  Brief Noise Analysis !  Proposed Architecture !  Building Blocks !  Measurement !  Conclusion

2 ESSCIRC2015 41th European Solid-State Circuits Conference

[C4L-A] A Fractional-N Sub-Sampling PLL using a Pipelined Phase-Interpolator with a FoM of -246dB

Motivation !  Wireless carrier generation requires fractional-N PLL.

!  Fractional operation introduces additional noise.

!  Conventional synthesizer architectures:

!  CP Based: Poor close-in phase noise.

!  TDC Based: Power-jitter trade-off.

!  Injection Locking: Large spurious.

!  Sub-sampling: Power-jitter tradeoff.

Aim: Low-power high-purity fractional-N SS-PLL

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[C4L-A] A Fractional-N Sub-Sampling PLL using a Pipelined Phase-Interpolator with a FoM of -246dB

Fractional-N SS-PLL: Prior Art

[1] G. Marucci, ISSCC 2014, [2] Po-Chun Huang, ISSCC 2014, [3] K. Raczkowski, RFIC 2014]

DTC facilitates fractional-N operation

SSPDDTCOutRef

LPF

Dither

Frequency-Locked Loop

CP

Ref

Ref_DTC

Ref_DTC

VCO

D0 D0D1 Dk

TDR,DTC

fout = (N+n)×fref; N- Integer part; n- fractional part

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[C4L-A] A Fractional-N Sub-Sampling PLL using a Pipelined Phase-Interpolator with a FoM of -246dB

DTC only architecture requires large dynamic range

Inpu

t [V]

Out

put [

V]

t

t+Δτdτd

Error in Threshold-crossing

DTC

TVCO

DTC Only

Conventional Frac.-N SSPLL: Challenges

!!",!"# ≥ !!"# !

Inpu

t [V]

Out

put [

V]

t

t+Δτdτd

Error in Threshold-crossing

DTC

TVCO

DTC Only[4] A. Abidi, JSSC 2006

!!!! = 4kTγ!!!!!(!!! − !!")!

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[C4L-A] A Fractional-N Sub-Sampling PLL using a Pipelined Phase-Interpolator with a FoM of -246dB

Highly linear phase-interpolator + DTC results in lower noise

Proposed Technique

Required dynamic range(dr)

!!",!"#!!" = !!"#4

12!

!_!"

!!!+!

!!!"# ∙ 2!_!"# − 1 !

Inpu

t [V]

Out

put [

V]

t

t+Δtdtd

Error in Threshold-crossing

PI

DTCDTC

DTC

DTC

DTC

DTCDTC

DTC

PI

PI

PI

PI

PI

Phase Interpolator+DTC

PI

PI

!!",!"# ≥ !!"# !

Error in threshold-crossing

!!!"! = 4kTγ!!!"!!(!!! − !!")!

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[C4L-A] A Fractional-N Sub-Sampling PLL using a Pipelined Phase-Interpolator with a FoM of -246dB

Dynamic Range Comparison

Dynamic range requirements are relaxed

Dyna

mic

Ran

ge [n

s]

1

0.01

0.1

0.1 1VCO Cycle [ns]

DTC

DTC+Phase-Interpolator

0.25psResolution:

5ps10ps

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[C4L-A] A Fractional-N Sub-Sampling PLL using a Pipelined Phase-Interpolator with a FoM of -246dB

Intrinsic Jitter Comparison

eg: Fvco = 4GHz, required resolution=250fs, DSM: second order RMS Jitter: DTC only = ~150fs DTC+PI = ~50fs

RMS

Jitte

r [fs

]

220

20

60

140

180

100

0.1 1VCO Cycle [ns]

0.25psResolution:

5ps10ps

DTC

DTC+Phase-Interpolator

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[C4L-A] A Fractional-N Sub-Sampling PLL using a Pipelined Phase-Interpolator with a FoM of -246dB

Power and area wastage is minimized

Pipelined Phase-Interpolator

00

900Out

1800

2700

Stage-1

Phase

Interpolator

Φi1Φo1

Φo2

Φo3Φi2

Stage-2

Phase

Interpolator

Φi1Φo1

Φo2

Φo3Φi2

Stage-M

Phase

Interpolator

Φi1Φo1

Φo2

Φo3Φi2

[5] S. Kumaki, APCCAS 2010

!  No. of stages: Tournament type: 2N_PI – 1

!  No. of stages: Pipelined: N_PI+1

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[C4L-A] A Fractional-N Sub-Sampling PLL using a Pipelined Phase-Interpolator with a FoM of -246dB

Issue of Conventional Phase-Interpolator

Ix Ix

Ix Ix

Φin

1

Φin

2

Φo2

Φi1

Φo1

PI

PIPI

Phase Interpolator(one stage)

PI

C

C

C

Φo2

Φo3

Φi2

Φin1

Φin2

Φo

Φin1

Φin2

Φo

Φin1

Φin2

Φo

00

900

450

00

PI

PI

Phase Interpolator(one stage)

PI

C

C

C

900

Φin1

Φin2

Φo

Φin1

Φin2

Φo

Φin1

Φin2

Φo

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[C4L-A] A Fractional-N Sub-Sampling PLL using a Pipelined Phase-Interpolator with a FoM of -246dB

Conventional Phase-Interpolator

Ix Ix

Ix Ix

Φin

1

Φin

2

Φin1Φin2

Φo1

time

Φo1

Φi1

Φo1PI

PI

PI

Phase Interpolator(one stage)

PI

C

C

C

Φo2

Φo3

Φi2

Φin1

Φin2

Φo

Φin1

Φin2

Φo

Φin1

Φin2

Φo

time

2Ixdvdt

= C

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[C4L-A] A Fractional-N Sub-Sampling PLL using a Pipelined Phase-Interpolator with a FoM of -246dB

Conventional Phase-Interpolator

Ix Ix

Ix Ix

Φin

1

Φin

2

Φin1Φin2

Φo3

time

Φo3

Φi1

Φo3PI

PI

PI

Phase Interpolator(one stage)

C

C

Φo2

Φi2

time

PIC Φo1

Φin1

Φin2

Φo

Φin1

Φin2

Φo

Φin1

Φin2

Φo

2Ixdvdt

= C

12 ESSCIRC2015 41th European Solid-State Circuits Conference

[C4L-A] A Fractional-N Sub-Sampling PLL using a Pipelined Phase-Interpolator with a FoM of -246dB

Conventional Phase-Interpolator

Ix(1-δ)

Ix Ix

Ix Ix

Φin

1

Φin

2

Φin1Φin2

Φo2

IdealActual

dv

dt= C

time

Φo2

timeΦi1

Φo1

PI

PIPI

Phase Interpolator(one stage)

PI

C

C

C

Φo2

Φo3

Φi2

Ixdvdt

=C

Φin1

Φin2

Φo

Φin1

Φin2

Φo

Φin1

Φin2

Φo

δIxsh

ort c

ircui

t cu

rren

t

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[C4L-A] A Fractional-N Sub-Sampling PLL using a Pipelined Phase-Interpolator with a FoM of -246dB

Conventional Phase-Interpolator

Short circuit current results in phase error

Ix Ix

Ix Ix

Φin

1

Φin

2

Φin1Φin2

Φo2

IdealActual

time

Φo2

timeΦi1

Φo1

PI

PIPI

Phase Interpolator(one stage)

PI

C

C

C

Φo2

Φo3

Φi2

2Ixdvdt

= CIxdv

dt=C

Φin1

Φin2

Φo

Φin1

Φin2

Φo

Φin1

Φin2

Φo

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[C4L-A] A Fractional-N Sub-Sampling PLL using a Pipelined Phase-Interpolator with a FoM of -246dB

Proposed Short-Current-Free Topology

Short-circuit current is avoided

Φin1Φin2

time

Φo2

Φo2

timeΦi1

Φo1

PI

PIPI

Phase Interpolator(one stage)

PI

C

C

C

Φo2

Φo3

Φi2

Φin1

Φin2

Φo

Φin1

Φin2

Φo

Φin1

Φin2

Φo

Ixdvdt

=C

Ix Ix

Ix Ix

ΔC

Φin2Φin1

Φin1 Φin2

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[C4L-A] A Fractional-N Sub-Sampling PLL using a Pipelined Phase-Interpolator with a FoM of -246dB

Proposed Short-Current-Free Topology

INL of < 0.5 LSB is achieved

[6] T. Saeki, JSSC 2000

Ixdvdt

=

Φin1Φin2

C2Ixdv

dt= C

time

Φo2

timeΦi1

Φo1

PI

PIPI

Phase Interpolator(one stage)

PI

C

C

C

Φo2

Φo3

Φi2

Φin1

Φin2

Φo

Φin1

Φin2

Φo

Φin1

Φin2

Φo

Ix Ix

Ix Ix

ΔC

Φin2Φin1

Φin1 Φin2

Φo2

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[C4L-A] A Fractional-N Sub-Sampling PLL using a Pipelined Phase-Interpolator with a FoM of -246dB

Proposed FN-SSPLL Architecture

SSPDRef

DTC LPFout

CP

3-Bit Pipelined Phase-Interpolator00

450135022503150

22.5011.250

0.35150

00

900

1800

1800

2700

Quad.Divider

Stag

e 1

Stag

e 2

Stag

e 3 Φi1Φo1

Φo2

Φo3

Φi2

Φi1Φo1

Φo2

Φo3

Φi2

Φi1Φo1

Φo2

Φo3

Φi2

td,s1td,s2td,s3

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[C4L-A] A Fractional-N Sub-Sampling PLL using a Pipelined Phase-Interpolator with a FoM of -246dB

Proposed FN-SSPLL Architecture SSPD

Ref

Ref

DTC LPFout

DSM

PSM

PSM: Power Save ModuleWS:Wave Shaper

PSWL: Phase Switch LogicIFCW: Integer Freq. Control WordFFCW: Fractional Freq. Control Word

WS

CP

FLLIFCW

IFCWR_DTC R_PI Reg

FFCW

Phase Switch Power Down

3-Bit Pipelined Phase-Interpolator

PSWL

RefCW

Register Bank

00

00

900

1800

1800

2700

Quad.Divider

Sta

ge1

Sta

ge2

Sta

ge3 Φi1

Φo1

Φo2

Φo3

Φi2

Φi1

Φo1

Φo2

Φo3

Φi2

Φi1

Φo1

Φo2

Φo3

Φi2

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[C4L-A] A Fractional-N Sub-Sampling PLL using a Pipelined Phase-Interpolator with a FoM of -246dB

Chip Micrograph

LC-VCO SPI

LPF

520 µm

380

µm PI

DTC

PSLSSLFLL&

0.2mm2 core area in Standard 65nm CMOS process

19 ESSCIRC2015 41th European Solid-State Circuits Conference

[C4L-A] A Fractional-N Sub-Sampling PLL using a Pipelined Phase-Interpolator with a FoM of -246dB

Measurement Results

-60

-40

-80

-100

-160

-140

-180

Phas

e No

ise

[dBc

/Hz]

-120

100k 1MFrequency [Hz]

10M10k

4.4716GHz from 40MHz reference [N=111.79]

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[C4L-A] A Fractional-N Sub-Sampling PLL using a Pipelined Phase-Interpolator with a FoM of -246dB

Performance Comparison of Fractional-N PLL This work [1] [2] [7]

Architecture SSPLL SSPLL MDLL TDC Freq. [GHz] 4.1-5.1 2.2-2.4 1.6-1.9 2.412-2.484

4.915-5.825 Power [mW] 3.3 17.3 3 9.5 Area [mm2] 0.2 0.75 0.4 0.3 Phase Noise (in-band)

-112 @400kHz

-112 @50kHz

-112 @100kHz

-106 @100kHz

Integrated Jitter 273fs 266fs 1.4ps 173fs

FoM [dB] -246.1 -239.1 -233.76 -245.5 CMOS Tech. 65nm 180nm 130nm 28nm FDSOI [1] Po-Chun Huang, ISSCC 2014 [2] G. Marucci, ISSCC 2014 [7] X. Gao, ISSCC 2015

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[C4L-A] A Fractional-N Sub-Sampling PLL using a Pipelined Phase-Interpolator with a FoM of -246dB

Performance Comparison of Fractional-N PLL

FoM = 10logJitter

1s

2 Power1mW( ( ( (×

Better

Jitte

r2 (p

s)2

W. Deng, ISSCC 2015

P. Park, ISSCC 2012

M. Gupta, ISSCC 2006

C. H. Lee, VLSI 2014

C. W. Yao, VLSI 2011

M. Talegaonkar, VLSI 2014

G. Marucci, ISSCC 2014

A. Elkholy, VLSI 2014

X. Gao, ISSCC 2015

This Work

10-2

10-1

100

100

101

101

102

102

Power Consumption [mW]

FoM=-220dB

FoM=-230dB

FoM=-240dB

FoM=-250dB

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[C4L-A] A Fractional-N Sub-Sampling PLL using a Pipelined Phase-Interpolator with a FoM of -246dB

Conclusion

!  A fractional-N SSPLL architecture is presented. !  Proposed architecture uses a combination of DTC

and phase-interpolator: !  Reduces jitter from the multi-phase generator. !  Power-jitter-resolution tradeoff is mitigated. !  FoM of -246.1dB is achieved.

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