a program for device model parameter extraction from gate capacitance and current of ultrathin and...

2118 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 53, NO. 9, SEPTEMBER 2006

A Program for Device Model Parameter Extractionfrom Gate Capacitance and Current of Ultrathin

SiO2 and High-κ Gate StacksFei Li, Student Member, IEEE, Leonard Franklin Register, Senior Member, IEEE,

Mohammad Mehedi Hasan, and Sanjay K. Banerjee, Fellow, IEEE

Invited Paper

Abstract—A modeling tool is demonstrated for fast and au-tomatic gate dielectric characterization and parameter extrac-tion for the 45-nm CMOS technology node and beyond. Themodel incorporates a nonlinear least squares fitting programwith the ability to extract nanometer-scale equivalent oxide thick-nesses (EOTs) SiO2 and high-dielectric-constant (high-κ) gatedielectrics from experimental gate capacitance (Cg–Vg ) and gateleakage current (Ig–Vg ) with high accuracy and efficiency. Amodified Levenberg–Marquardt algorithm was used as the op-timization approach. Improvements were made to reduce thechances of becoming stuck in local minima. A previously re-ported computationally efficient and accurate physically basedcompact model of self-consistent Cg–Vg and Ig–Vg model forboth ultrathin SiO2 and high-κ gate stacks of EOT down to∼ 0.5 nm is used as the basis for translating experimental Cg–Vg

and Ig–Vg data to material and device parameters. In just afew seconds, for single and double layer gate dielectrics, deviceparameters such as EOTs, surface substrate doping concentra-tions, flatband voltages, and polysilicon doping concentrations (ifapplicable) can be extracted from measured gate capacitance data,and parameters such as physical thickness, band offsets, dielectricconstants, and tunneling masses for the gate dielectrics can beextracted from measured gate current data. It was found thatsignificant correlation exists between the effects of certain combi-nations of model parameters, especially for gate tunneling current.Thus, in this program, parameters can be fixed selectively for thosealready obtained with high confidence from other measurements.Box constraints can also be imposed, at the price of somewhatlonger extraction time (up to ∼ 1–7 min), for parameters tobe optimized to improve the possibility of finding the correctparameters.

Index Terms—Gate tunneling currents, high-κ gate dielectrics,Levenberg–Marquardt method, MOS devices, nonlinear leastsquares fitting, parameter extraction, quantum mechanical effects.

Manuscript received January 30, 2006; revised May 9, 2006. This work wassupported in part by the Texas Advanced Materials Research Center funded bySEMATECH. The review of this paper was arranged by Editor S. Saha.

F. Li is with Synopsys Inc., Mountain View, CA 94043 USA.L. F. Register and S. K. Banerjee are with the Microelectronics Research

Center, Department of Electrical and Computer Engineering, University ofTexas at Austin, Austin, TX 78758 USA.

M. M. Hasan was with the Chemical Mechanical Polishing (CMP) Division,Applied Materials Inc., Austin, TX 78724 USA. He is now with the Microelec-tronics Research Center, Department of Electrical and Computer Engineering,University of Texas at Austin, Austin, TX 78758 USA.

Digital Object Identifier 10.1109/TED.2006.880373

I. INTRODUCTION

A S CMOS technology approaches the 45-nm node andbeyond, the equivalent oxide thickness (EOT) of the

gate dielectrics in MOS devices is projected to be as thin as∼ 1.0–0.5 nm to maintain gate control over the channel [1]. Theinterpretation of and parameter extraction from measured gatecapacitance (Cg–Vg) and gate current (Ig–Vg) data, as requiredfor device characterization and subsequent device and circuitsimulation, becomes increasingly complicated for the followingtwo reasons: 1) The increasing complexity of the essentialphysics of quantum–mechanical (QM) effects for such ultrathinEOT oxides poses increased challenges to modeling of gatecapacitance and tunneling, particularly to compact modeling.Compared to previous compact models originally designedfor larger devices (standard compact models include BSIM1[2], BSIM4 [3], and the PSP model [4]), explicit treatmentof quantum effects such as wave function penetration [5]–[8]and tunneling through the gate oxide [9] can no longer beignored in the analysis of future MOS devices. In addition, withreduced EOTs, polydepletion effects degrade MOS devicesperformance increasingly and metal gates are being studied as apossible substitute for polysilicon gates [1]. 2) Alternative high-dielectric-constant (high-κ) materials such as Si3N4, HfO2, andHfTaTiO are being studied as replacements for SiO2 as thedielectric layer to reduce tunneling leakage while maintainingsmall EOTs [10]–[14]. And as shown in Fig. 1, when high-κdielectrics are used, there is usually a thin interfacial layerbetween the high-κ material layer and the substrate [15], whichis often an intentionally added SiO2 or SiON layer for betterinterface quality [11].

The use of self-consistent Poisson–Schrödinger simulators[7], [9], [16] can be impractical for large-scale circuit sim-ulation or automatic parameter extraction from experimentalCg–Vg and Ig–Vg data. On the way to addressing this need,previously, we developed computationally efficient physics-based compact models for conventional oxides and high-κ gatestacks [17], [18]. These models produce results comparable tothose obtained via the numerical simulator, itself, with the samedevice and material parameters but on the order of 105–106

times faster. Indeed, a thousand separate simulated curves canbe produced in just a few seconds.

0018-9383/$20.00 © 2006 IEEE

LI et al.: DEVICE MODEL PARAMETER EXTRACTION FROM ULTRATHIN SiO2 AND HIGH-κ GATE STACKS 2119

Fig. 1. Band diagram for a high-κ gate stack. (Color version available onlineat http://ieeexplore.ieee.org.)

Continuing this effort, in this paper, we have made use of thatunderlying efficiency to develop a nonlinear least squares fittingprogram with the modified Levenberg–Marquardt algorithm[19] for an efficient and accurate extraction of device anddielectric material parameters such as EOTs, surface substratedoping concentrations (NB), polysilicon doping concentrations(NP ), and flatband voltages (VFB) from measured Cg–Vg dataand, for the first time, for the extraction of physical thicknesses,band offsets, and tunneling masses of each layer from measuredIg–Vg data. Both conventional and high-κ gate stacks forCMOS devices at and beyond the 45-nm node are considered.As compared to existing device parameter extraction programssuch as that found in [20], this program provides comparablespeed while addressing additional physics for very small EOTsand, through consideration of Ig–Vg , more parameters.

For gate capacitance–voltage characteristic fitting, as in gen-eral nonlinear least square fitting problems, local minima inthe quality of the fit can sometimes cause trouble for such aprogram to converge. This problem has been resolved by usinga more smooth objective function or error function. For gatecurrent fitting, the correlation between the effects of parameterssuch as physical thicknesses and tunneling effective massesof high-κ’s is strong, which may cause large inaccuracy indetermination of these parameters. Thus, here, parameters canbe fixed selectively for those already obtained with high confi-dence from other measurements. Alternatively, a method of boxconstraints [19] is incorporated into this program to limit therange of each parameter. Other aspects of this program address,e.g., reasonable initial guesses and scaling of the parameters.The extraction time is typically a few seconds or less forunconstrained fitting and up to a few minutes if box constraintsare imposed.

In Section II, the algorithm implementation will be intro-duced. The issues in and the results of parameter extractionfrom measured gate capacitance data and gate current datawill be presented in Sections III and IV, respectively. Theconclusion follows in Section V.

II. ALGORITHM IMPLEMENTATION

A nonlinear least squares algorithm is usually used to fitthe parameters of compact models to the measured data sothat meaningful parameters can be obtained; in turn, with thesemeaningful parameters, these compact models can be more reli-ably used to represent the device behavior in circuit simulators

[21]–[23]. For the set of M parameters p = (p1, p2, . . . , pM )used to fit a given p-dependent model function f(xi;p) of thegate capacitance or gate current to N data points f(xi) as afunction of discrete field or voltage values xi, the error functionassociated with the parameter set p is defined as

χ2(p) =N∑

i=1

[f(xi) − f(xi;p)]2

σ2i

(1)

where σi is the prescribed standard deviation of the ith datapoint. In this paper, σi has simply been set to unity for allconsidered data points, but it could be increased in “sensitive”regions to improve convergence, as will be discussed later.The parameter set p is then determined such that χ2(p) isminimized.

The Levenberg–Marquardt algorithm, which combines thesteepest descent algorithm and the Gauss–Newton method, isone of the standard methods for minimizing χ2(p) in (1) iter-atively with respect to the set of parameters p [23]–[25]. If theerror χ2(p) increases between iterations, a damping factor inthe Levenberg–Marquardt method is increased, and the methodmoves toward the steepest decent method, which is slow butguaranteed to converged. If the error decreases, the dampingfactor is reduced, and it moves toward the Gauss–Newtonmethod, which is less stable but faster. Since Marquardt’spaper in 1963 [26], there were many implementations of theLevenberg–Marquardt algorithm. In this paper, the modifiedLevenberg–Marquardt algorithm based on [19] was imple-mented for the purpose of parameter extraction from measuredgate capacitance and gate tunneling current data.

A block diagram that summarizes the flow of the parame-ter extraction program is demonstrated in Fig. 2. First, boththe user-controlled parameters and the measured Cg–Vg orIg–Vg data are input into the program. From these, initialparameter guesses p0, scaling factors for these parameters,and other optional parameters are provided and/or obtainedat this stage. Then, the Levenberg–Marquardt subroutine iscalled, and starting with the initial guesses p0, the programconverges to the final solution(s) pj-final iteratively throughreduction in χ2

j (p). The error function χ2j (p) of (1) is de-

fined in this subroutine. The functions that define the compactgate capacitance or gate tunneling current models might becalled from about 100 to several thousand times for the eval-uation of the error function and the Jacobians of the modelfunctions about the parameters p required for making thenext guess. Forward-finite-difference-approximated Jacobianswere used for derivative calculations. A standard linear al-gebra package LAPACK [27] was installed, and the singularvalue decomposition (SVD) method was chosen from it as thematrix solver. The iteration procedure continues until eitherχ2(p) reaches some predetermined small acceptable value,i.e., when some other stopping criterion is reached, whichindicates that the best available solution p has been found,or when some predefined maximum number of iterations isreached.


Fig. 2. (a) Block diagram for the parameter extraction program with amodified Levenberg–Marquardt algorithm. (b) Illustration of the error functionin extraction from gate capacitance or gate current data.

III. PARAMETER EXTRACTION FROM GATE CAPACITANCE

From one set of measured gate capacitance data, the para-meters of the MOS device under test to be extracted are EOT,flatband voltage (VFB), surface substrate doping concentra-tion (NB), and if applicable, the polysilicon doping concen-tration (NP ).

It was found that good initial guesses, scaling of parame-ters, and a modification of the error function for this problemare the keys for the program to converge toward the correctsolution. Usually, it is easier for such a program to determinethe EOTs more accurately than substrate doping concentrationsfrom measured gate capacitance data. To assure the robustnessof the parameter extraction, a careful approach is taken to findthe initial guesses for parameters. These initial guesses arethe starting point for iteration for the Levenberg–Marquardtalgorithm. Good initial guesses make it easier for the programto find the solution and are sometimes crucial to avoid localminima in nonlinear least squares problems. Due to the differ-ences in units and ordinary values for parameters to be extractedsuch as EOTs and doping concentrations in this paper, it hasbeen suggested to scale problems by choosing the units of thevariable space so that each component of pl will roughly have

Fig. 3. Gate capacitance from self-consistent Poisson–Schrödinger simula-tions of metal gate nMOS devices with EOTs from 5 to 0.5 nm and substratedoping concentrations of 1016 and 1018 cm−3.

TABLE ISTRATEGY TO ESTIMATE EOTS FOR THE INITIAL GUESSES IN

EXTRACTION FROM GATE CAPACITANCE

the same magnitude [24]. Therefore, in this paper, the initialguesses are also taken as the scaling factors for the parametersto be extracted.

As seen in the self-consistent Poisson–Schrödinger resultsfor gate capacitance simulations of ten nMOS devices withEOTs from 0.5 to 5 nm and substrate doping concentrationsof 1016 and 1018 cm−3 (Fig. 3), gate capacitance is strongly de-pendent on EOT and only very weakly dependent on substratedoping in the strong accumulation and inversion regimes. Fromboth this figure and simple device physics [28], the initial guessfor the EOT, which is denoted as EOT0, is obtained from themaximum gate capacitance Cmax as follows:

EOT0 =εoxε0

Cmax− ∆EOT (2)

where ∆EOT is a rough correction to εoxε0/Cmax and ischosen according to the value of εoxε0/Cmax as in Table I. Incomparison to self-consistent calculations, these initial guessesare up to 1 nm off from the actual EOTs of the gate stacks.

The initial guess for surface substrate doping concentra-tion (NB) is estimated from the minimum capacitance Cmin

(in farads per square centimeter) and EOT0. In depletionapproximation, the NB can be obtained from the maximum


Fig. 4. Error functions in extraction from gate capacitance (a) before and (b)after the “sensitive” points around threshold voltage are removed from (1).EOT is fixed to 1 nm. The actual parameters for the virtual nMOS devicegenerated by the self-consistent Poisson–Schrödinger simulation are givenas follows: EOT = 1.0 nm, VFB : −0.69 V, and NB : −1018 cm−3. Theremoval of the sensitive points removes the local minima. Note that the errorfunctions are in the log scale in these plots. (Color version available online athttp://ieeexplore.ieee.org.)

depletion width Wm as [28]

Wm ≈

√4εSikT ln(NB/ni)

q2NB. (3)

Wm can then be approximated via

1Cmin

≈ EOT0

εoxε0+

Wm

εSiε0. (4)

TABLE IIEXTRACTION OF DEVICE PARAMETERS BY MODIFIED

LEVENBERG–MARQUARDT ALGORITHM: (a) VIRTUAL nMOSAND (b) pMOS CAPACITORS GENERATED BY SELF-CONSISTENT

POISSON–SCHRÖDINGER SIMULATIONS WITH 1.0 nm EOTS AND

VARIOUS SUBSTRATE DOPING CONCENTRATIONS. A METAL GATE WORK

FUNCTION OF 4.5 eV FOR nMOS AND 4.7 eV FOR pMOS WAS USED,RESPECTIVELY. NOTE THAT NEGATIVE NUMBERS INDICATE p-TYPE AND

POSITIVE NUMBERS INDICATE n-TYPE FOR SUBSTRATE DOPING

CONCENTRATIONS IN THIS TABLE

Fig. 5. Example of parameter extraction from gate capacitance for a virtualpMOS device with an ultrathin gate stack.

However, the surface substrate doping concentration NB cannotbe determined from (3) and (4) explicitly. In reality, althoughNB may vary by several orders of magnitude, ln(NB) isrelatively constant (ln(NB) is 34.54 for NB = 1015 cm−3 and43.75 for NB = 1018 cm−3). To exploit this fact, ln(NB) is


Fig. 6. Example of parameter extraction from measured gate capacitance dataof an nMOSFET with an ultrathin HfO2 gate stack [32]. In this example,57 Levenberg–Marquardt iterations were needed for the convergence. Inset:Sample plot of the behavior of damping factor versus iteration number.

approximated as a middle value 39 in (3), and the initial guessfor NB is approximated as

NB0 ≈ 4kT

εSiq2×

[1

Cmin− EOT0

εoxε0

]−2

×(

Eg

2kT− 5.28

). (5)

It was found by the numerical simulation that NB0, which iscalculated from (5), is at most only about two times differentthan the actual surface substrate doping concentration in therange of interests, assuming that there is no large density ofinterface traps (Dit).

The initial guess of flatband voltage is determined fromthe slope of measured gate capacitance data similar to [29]; theflatband voltage is estimated as the gate voltage at which themaximum slope occurs on the left flank of the Cg–Vg curve fornMOS and on the right flank for pMOS, respectively.

It is well known that the undesired local minima in theerror function (1) often exist in optimization problems, whichmay cause the program to stop at an incorrect solution [24].To avoid local minima, stochastic methods such as simulatedannealing algorithm are often suggested [30], [31]. However,such programs are complicated, and usually, one may haveto use some heuristic techniques for his own problem. There-fore, instead, in this paper, the effort was put into smoothingthe error function (1) and minimizing the number of localminima. It was found that most local minima in the case ofparameter extraction from gate capacitance are caused by theinconsistencies between simulated and measured capacitancedata points around the threshold voltage. Around the thresholdvoltage, the capacitance increases sharply from Cmin to thelarge capacitances in strong inversion. Due to the large slope,local minima may be easily generated by either a slight noisein a few measured data points or a small inaccuracy in themodel, as indicated by the “sensitive” region in Fig. 2(b). Fur-thermore, inaccuracies in the models are probably most likelyaround threshold and flatband where the governing physics isin transition [17]. To illustrate this behavior, a self-consistentPoisson–Schrödinger simulation was made for a virtual metalgate nMOS device with EOT of 1.0 nm, NB of −1018 cm−3,and VFB of −0.69 V to represent the measured gate capacitance

Fig. 7. Fitting of gate current for parameter extraction for virtual nMOSdevices with ultrathin single layer gate stacks (see Table III) for: (a) 1.0-nmEOT SiO2 dielectric, in which parameters were fixed selectively, without boxconstraints; (b) same as (a) but with box constraints; (c) 1.0-nm EOT HfO2

dielectric, with parameters fixed selectively and with or without box constraints.


TABLE IIIPARAMETER EXTRACTION FROM GATE CURRENT OF VIRTUAL MOS DEVICES WITH SINGLE-LAYER (a) SiO2 AND (b) HfO2. IN SOME CASES, THE

PARAMETERS WERE SELECTIVELY FIXED AND BOX CONSTRAINTS WERE IMPOSED (SEE FIG. 7)

data. As shown in Fig. 4(a), there are many local minima in theerror function χ2(p) for the parameters NB and VFB , whichcauses problems in the extraction of them. If the sensitive datapoints about the threshold are removed from the error function(1), as done in this program, it becomes much smoother asshown in Fig. 4(b). Only the global minimum is located closelyabout the correct solution. Alternatively, these local minimamight also be removed by a modification to (1) to measure the“distance” of the data f(xi) to the nearest point on the modelcurve f(x;p) wherever that is, where x is quasi-continuous,as proposed in [31], rather than only to the specific valuef(xi;p). This could be effectively accomplished, however, bymaking the standard deviations σi in (1) a function of the slopes

∂f(xi)/∂x and/or ∂f(xi;p)/∂x so that the greater the slope,the greater the tolerable standard deviation, but this approachhas not yet been implemented.

To test this program, six “virtual” Cg–Vg curves weregenerated with self-consistent Poisson–Schrödinger simula-tions for both nMOS and pMOS metal gate capacitors with1.0 nm EOTs and substrate doping concentrations of 1016,1017 and 1018 cm−3, respectively, as shown in Table II.The EOTs, surface substrate doping concentrations NB , andflatband voltages VFB extracted are nearly identical to thoseof the virtual devices. The computation times are all withinonly about 1 s on a 3.0-GHz processor. The typical num-ber of Levenberg–Marquardt iterations for these extractions is


approximately 60. Furthermore, the robustness of this programwas tested to be good by manually changing the initial guessesto arbitrary values, although there was some variations inspeed. As shown in Fig. 5 as an example, the analyticallysimulated gate capacitance with the parameters extracted withthis program agrees very well with the virtual device data.The correlations—i.e., the similarity in effect—between theextracted parameters are not strong.

This program also worked well with the measured gatecapacitance data of a real nMOS device with a TaC gateelectrode, and a HfO2 gate stack [32], as shown in Fig. 6.Here, the leakage current is relatively low due to the largephysical thickness of high-κ gate dielectrics, and its impacton the measurement of gate capacitance has been ignored. Inthe presence of high leakage current, accurate measurement ofMOS transistor Cg–Vg may require correction such as usinga lossy transmission line model [33] before the parameterextractions in this paper are conducted. Also shown in the insetof Fig. 6 is a sample plot of the behavior of the damping factorversus iteration number for this set of measured data.

IV. PARAMETER EXTRACTION FROM GATE CURRENT

Due to many orders of magnitude variation in gate current,parameters are actually extracted according to the error function(1) in the logarithm of the gate current. Furthermore, deviceparameters such as the EOT, NB , and VFB are used as inputshere assuming that they have been extracted from measuredgate capacitance data. This makes the parameters extractedfrom the current calculations more meaningful, and this is oneof the advantages of employing self-consistent compact gatecapacitance and current models as used here [17], [18]. In thispaper, we have considered only single- and double-layer gatestacks. Still, from one set of measured gate current data, thenumber of parameters of the MOS device under test to beextracted could be up to five for single-layer gate stacks andten for double-layer gate stacks, including physical dielectricthicknesses (tphy,1, tphy,2), effective masses (mdiel,1,mdiel,2),band offsets in conduction band (∆Ec,diel1,∆Ec,diel2), bandoffsets in valence band (∆Ev,diel1,∆Ev,diel2)—even if onlyelectron tunneling is considered because the dielectric band gapis also required in the Franz two-band model of the dielectric—and dielectric constants (εdiel,1, εdiel,2). Here, the dielectriclayer close to the Si substrate is labeled as the first dielectriclayer and the one next to the gate electrode as the second layer.However, because, for example, for double-layer gate stacks,tphy,1, tphy,2, εdiel,1, εdiel,2 and EOT are constrained by

EOT =εox

εdiel,1× tphy,1 +

εox

εdiel,2× tphy,2 (6)

there are actually at most “only” four possible independentparameters to be extracted from gate current here for single-layer gate stacks and nine for double-layer gate stacks in thisprogram.

In addition, a significant issue in parameter extraction fromgate current is the strong correlations between the parameters.For example, variations in the physical thickness tphy of the

Fig. 8. Fitting of gate current for parameter extraction for a virtual nMOSdevice with ultrathin double-layer gate stacks (see Table IV) for a 1.36-nmEOT HfO2/Hf-silicate dielectric, with parameters fixed selectively and withbox constraints.

Fig. 9. Fitting of gate current to measured gate capacitance and gate currentof an n+poly/HfO2/SiON/p-Si structure [34]. Extracted parameters and otherdetails are provided in Table IV.


TABLE IVPARAMETER EXTRACTION FROM GATE CURRENT OF MOS DEVICES WITH DOUBLE-LAYER HfO2 GATE

STACK: VIRTUAL MOS DEVICE OF FIG. 8 AND REAL MOS DEVICE [34] OF FIG. 9

barrier can be largely (exactly in a combination of the parabolicand conventional Wentzel–Kramer–Brillouin (WKB) approxi-mations) compensated for in the tunneling current by inversechanges in the square of the effective mass and compensated forexactly in its contribution to the EOT by proportional changesin εdiel. Therefore, the parameter set solution to this nonlinearleast squares fitting problem may not be unique or only weaklyso. Although not as straightforward as for gate capacitance,the approach of this paper is still useful for studying thegate current-related properties of the gate dielectrics if part ofthe parameter set is already known or known at least withinsome range such that box constraints can be imposed on theparameters.

Again, tests on parameter extraction from gate current datawere performed for virtual MOS devices generated by self-consistent Poisson–Schrödinger simulations. A series of sixtests each for nMOS devices with single-layer 1.0-nm EOTSiO2 and HfO2 gate stacks are demonstrated in Fig. 7 andTable III. All parameter sets produce excellent fits to the data.However, when many parameters are extracted and few con-straints applied, the extraction can be quite inaccurate becauseof the correlations discussed above between the parameters.Clearly, for meaningful parameter extraction, the set of para-meters needs to be minimized or at least constrained based onindependent information such as physical thickness from trans-mission electron microscopy (TEM) measurements or priorknowledge (or at least assumptions) of material properties.Without that, again, the covariance of the extracted parametersis available for users as a measure of the reliability of theresults.

The tests for nMOS devices with double-layer 1.36-nmEOT HfO2/Hf-silicate gate stacks (with parameters for theself-consistent Poisson–Schrödinger simulation from [9]) aredemonstrated in Fig. 8 and Table IV. Again, trying to extractall parameters simultaneously can lead to inaccuracy in theparameters despite excellent data fits. However if the mater-

ial properties of HfO2 are known well enough, the physicalthicknesses of each dielectric can be determined accurately.Alternatively, if we know the properties of the high-κ well,this program could perhaps help to determine the parametersof its silicate in ultrathin gate stacks, a challenging but stillunresolved issue for both device design and circuit simulation.

Finally, this program was used to extract EOT, NB , VFB ,and NP from measured gate capacitance and then materialparameters of each dielectric from measured gate current datafor a real n+poly/HfO2/SiON/p-Si structure [34] (Fig. 9 andTable IV). The extracted HfO2 thickness and some other prop-erties agree well with its measurements and literature [9]. Thetypical number of Levenberg–Marquardt iterations is on theorder of 101–102 for unconstrained optimization and 102–103

with box constraints, depending on the number of parametersto be extracted.

V. CONCLUSION

A fast program with the modified Levenberg–Marquardtalgorithm has been demonstrated for parameter extraction frommeasured gate capacitance and gate current data for ultrathinSiO2 and high-κ gate stacks (EOTs down to 0.5 nm). EOT,flatband voltage (VFB), surface substrate doping concentration(NB), and if applicable, the polysilicon doping concentration(NP ) can be extracted accurately from measured Cg–Vg datawithin a few seconds. For the first time, up to five materialparameters for single-layer gate stacks and ten for double-layergate stacks can be determined with this program from measuredIg–Vg data. However, although Ig–Vg data can be fit very welland quickly in the process of extracting all relevant parameters,the parameter solutions themselves may not be unique or onlyweakly unique and thus inaccurate due to strongly correlatedeffects of adjusting parameters such as m and tphy. Thus, forparameter extraction from Ig–Vg, this extraction program isbest used in combination with other sources of information


such as physical layer thickness from TEM measurementsand/or prior knowledge of material parameters such as high-κdielectric constants to reduce the number of parameters or atleast constrain some of the parameters.

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Fei Li (S’04) received the B.S. and M.S. degrees in physics from PekingUniversity, Beijing, China, in 1996 and 1999, respectively, and the M.S.E.E.degree from the University of Notre Dame, Notre Dame, IN, in 2001. Hereceived the Ph.D. degree in electrical and computer engineering based on astudy on compact modeling of advanced gate stacks at the University of Texasat Austin, in 2006.

He joined Synopsys Inc., Mountain View, CA, in 2005.

Leonard Franklin (Frank) Register (S’85–M’89–SM’00) received the B.S. degrees both inphysics and in electrical engineering and the Ph.D.degree in electrical and computer engineering fromNorth Carolina State University.

After graduation, he served as a Research Sci-entist with the Computational Electronics Group,Beckman Institute, University of Illinois at Urbana-Champaign. From there, he joined the faculty of theDepartment of Electrical and Computer Engineering,University of Texas at Austin, in 2000, where he is

currently an Associate Professor. His current research focuses on the theoryand simulation of charge transport in deep submicrometer and nanoscaleddevices, particularly “nonclassical” CMOS, including quantum and “quantum-corrected” transport. He has also published in the areas of device reliability,scattering theory, lasers, and single electronics.


Mohammad Mehedi Hasan received the B.S. degree in electrical engineeringfrom the University of Texas at Austin in 2004, where he is currently workingtoward the Ph.D. degree in electrical engineering.

From August 2004 to August 2005, he was with the Chemical MechanicalPolishing (CMP) Division, Applied Materials Inc., Austin, where he worked onlatest generation CMP tools. His research focuses on the tunneling effects insemiconductor devices, and two- and three- dimensional simulation of devicecharacteristics.

Sanjay K. Banerjee (S’80–M’83–SM’89–F’96) re-ceived the B.Tech. degree from the Indian Institute ofTechnology, Kharagpur, India, in 1979, and the M.S.and Ph.D. degrees from the University of Illinois atUrbana-Champaign, in 1981 and 1983, respectively,all in electrical engineering.

He is the Cockrell Family Regents ChairProfessor of Electrical and Computer Engineeringand Director of the Microelectronics Research Cen-ter, University of Texas at Austin. He was a memberof Technical Staff, Corporate Research, Develop-

ment and Engineering, Texas Instruments Incorporated, from 1983 to 1987. Heworked on polysilicon transistors and dynamic random access trench memorycells used by Texas Instruments in the world’s first 4-Mb DRAM. He hasbeen an Assistant Professor (1987–1990), Associate Professor (1990–1993),and Professor (1993 up to the present) at the University of Texas at Austin.He has over 500 archival refereed publications/talks, 6 books/chapters, and26 U.S. patents. He has supervised 38 Ph.D. and 50 M.S. students. He iscurrently active in the areas of ultra-high-vacuum and remote plasma-enhancedchemical vapor deposition for silicon–germanium–carbon heterostructureMOSFETs and nanostructures. He is also interested in the areas of ultrashallowjunction technology and semiconductor device modeling.

Prof. Banerjee was a corecipient of the Best Paper Award in the IEEEInternational Solid State Circuits Conference in 1986. He also received the En-gineering Foundation Advisory Council Halliburton Award in 1991, the TexasAtomic Energy Fellowship (1990–1997), Cullen Professorship (1997–2001),and the NSF Presidential Young Investigator Award in 1988. His recent awardsinclude the ECS Callinan Award of 2003, the IEEE Millennium Medal of2000, and the SRC Inventor Recognition Award of 2000. He is a DistinguishedLecturer for the IEEE Electron Devices Society and was the General Chair ofthe IEEE Device Research Conference in 2002.

a program for device model parameter extraction from gate capacitance and current of ultrathin and...

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