A Test-Per-Clock LFSR Reseeding Algorithm for Concurrent Reduction on

Test Sequence Length and Test Data Volume

Adviser：蔡亮宙Student；蔡政宏

This paper proposes a new test-per-clock BIST (built-in self-Testing) method that attempts to minimize the test

sequence length and the test data volume simultaneously.

An efficient LFSR reseeding algorithm is developed by which each determined seed together with its derived patterns can detect the maximum number of so far undetected faults.

During the seed determination process an adaptive X-filling process is first employed to generate a set of candidate patterns for pattern embedding.

The process then derives a seed solution that can embed multiple candidate patterns at one time so as to minimize the number of seeds.

Abstract

To shorten the test sequence,the pattern embedding process begins with a small initial set of pseudo-random patterns and will incrementally add more patterns only when necessary.

Experimental results show that compared with the previous test-per-clock techniques based on the LFSR- and twisted-ring-counter-reseeding methods,our method can reduce the test sequence length by over 60%with generally smaller numbers of storage bits.

When compared with the mapping-logic-based BIST methods, our method can reduce the test sequence length by over 50% with a comparable area overhead.

Abstract

Preliminaries

Note that the first state of the LFSR is regarded as the seed. All the required seeds for reseeding can be stored in To embed a partially-specified test cube Pi into the j-th LFSR state LSj, the compatibility of the pattern pair (Pi, LSj) must be checked to see if a feasible solution to the corresponding set of linear equations can be identified.

For example, to embed a test cube P1 (10x0x) to the fourth state LS4,

the compatibility of P1 to LS4 is checked by solving the following linear equations.

Preliminaries

Preliminaries

Since a solution {x1 = 0, x4 = 0 and x2(+) x3(+)x5 = 1} can be

identified, the pattern pair (P1, LS4) is said to be compatible,

meaning that P1 can be embedded to LS4. When P1 is indeed

embedded to LS4, all the LFSR states should be updated based

on the solution for the pair (P1, LS4). Fig. 1(c) shows the

results after the update, which can then be further checked to

see if more pattern can be embedded. If no solution to the

linear equations can be identified, the pattern pair (Pi, LSj) is

said to be incompatible.

Preliminaries

The main objective of our LFSR reseeding algorithm is to

determine an appropriate seed for which a short test sequence

can be generated to detect a large number of undetected faults.

The proposed reseeding algorithm is described next.

Preliminaries

Proposed Concurrent Multiple Pattern Embedding Procedure

Seed Determination Process

Seed Determination Process

Experimental Results

Experimental Results

Experimental Results

Experimental Results

Test-per-clock BIST methods have the great advantage of very short test time. In this paper we have developed an efficient LFSR reseeding algorithm for test-per-clock BIST to minimize the number of seeds and the test sequence length simultaneously.

Experimental results show that significant reductions on storage data volume and/or test application time are achieved when compared to related test-per-clock BIST methods that are based on LFSR reseeding, mapping logic and TRC reseeding.

In fact our method can detect all testable stuck-at faults in any ISCAS circuit in less than 5000 clock cycles.

CONCLUSION

[1] L.-T. Wang, C.-W. Wu, and X. Wen, VLSI Test Principles andArchitectures: Design for Testability, Morgan Kaufmann, 2006.

[2] B. Koenemann, “LFSR-coded test patterns for scan designs,” in Proc.Europe Test Conf. 1991, pp.237-242.

REFERENCES