Advanced monolithic pixel sensors using SOI technology

T. Miyoshi1, Y. Arai1, M. Asano2, Y. Fujita1, R. Hamasaki3, K. Hara2, S. Honda2,

Y. Ikegami1, I. Kurachi1, S. Mitsui4, R. Nishimura3, K. Tauchi1, N. Tobita2 ,

T. Tsuboyama1, M. Yamada1 and the SOIPIX collaboration1High Energy Accelerator Research Organization (KEK)2Univ. Of Tsukuba, 3SOKENDAI, 4Kanazawa Univ.

1

FRONTIER DETECTORS FOR FRONTIER PHYSICS

13th Pisa Meeting on Advanced Detectors

24-30 May 2015

- La Biodola, Isola d'Elba (Italy)

http://rd.kek.jp/project/soi/

http://rd.kek.jp/project/soi/

2

Outlines

SOI monolithic pixel sensors

KEK DAQ system and performance

Current issues and solutions

Sensor performance (Integration-type pixel sensors)

Future plan and summary

FPIXb

MX1711

(FY13-2)

MX1655

(FY13-1)

INTPIX7

(18 mm x 18 mm)

30

mm

24mm

6mm

SPRiT

(SOI Portable

Radiation imaging Terminal)

•No mechanical bump bonding. Fabricated with semiconductor process only

• Fully depleted (thick & thin) sensing region

with low sense node capacitance (~10 fF@17 mm pixel) high sensor gain

・SOI-CMOS; Analog and digital circuit can be closer smaller pixel size• Wide temperature range (1-570K)

• Low single event cross section

• Technology based on industry standards; cost benefit

3

The features of SOI monolithic pixel sensor

Insulator

(SiO2)

High R Si

Low R Si

SOI Monolithic pixel sensor

Targets

High-Energy Physics

X-ray astronomy

Material science

Non-destructive inspection

Medical application

SOI=Silicon on insulator2005-

Process

(Lapis

Semiconductor

Co. Ltd.)

0.2mm Low-Leakage Fully-Depleted (FD) SOI CMOS

1 Poly, 5 Metal layers (MIM Capacitor and DMOS option)

Core (I/O) voltage : 1.8 (3.3) V

SOI wafer

(200 mm f

=8 inch)

Top Si : Cz, ~18 -cm, p-type, ~40 nm thick

Buried Oxide: 200 nm thick

Handle wafer thickness: 725 mm thinned up to 300 mm (Lapis)

or ~50 mm (commercial process)

Handle wafer type: NCZ, NFZ, PCZ, PFZ, double SOI

Backside

process (2011~)

Mechanical Grind Chemical Etching Back side Implant

Laser Annealing Al plating

4

Process Summary

• KEK organizes MPW runs once/twice a year

• Mask is shared to reduce cost of a design

• Including pixel detector chip and SOI-CMOS circuit chip

25mm x 30mm

Sensor test and DAQ system

On package< 6mm-sq

On circuit board> 6mm-sq

5

User FPGA

SiTCPFPGA

100Mbps

1Gbps

ADC(16)DAC4)

SEABAS1

SEABAS218mm

6mm

Detector board DAQ board

6

DAQ software & GUI

ROOT on linux

Single thread scheme (2008-)

ROOT+QT+OpenCV(+picojson)+MSVC

Multi-thread scheme (2014-)

NFZ-INTPIX4(FY2009) @ 150V

17mm pixel size x 832x512

Pixel scan time 400 ns/pixel

65Hz, compressedtrimmer

Monochromatic

X-ray 33.3 keV

7

INTPIX4 still images with up-to-date system

INTPIX4+SEABAS2, 4ms x 2000fr, 150V, scan time 320ns/pixel

33.3keV monochromatic X-ray KEK Photon Factory BL-14C1

4ms x 2000fr

* INTPIX4 size ~14x9mm

Current issues

8

SiO2

Si

1. Additional pixel process

2. Improved SOI wafer

Solutions

Charge

Collection

Depends on layout

and circuit

Affecting electric field

Total Ionization

Dose (TID) effect

Matsumura, Hideaki, et al. "Improving Charge-Collection Efficiency of SOI Pixel Sensors for X-ray Astronomy." NIM A (2015).

Various Implantation Options in Sensor part and Double SOI

SOI process

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Shield the back-gate effect / optimize charge collection efficiency

Nested-well process (Increase crosstalk?)

p/n various doping density

Middle SOI:

Additional shield layer

STEM image

Top SOI: SOI-CMOS

Double SOI (DSOI)

Current issues and solutions

10

Buried P-Well (BPW)

another SOI layer

1. BPW process : effective to analog circuit in a pixel

2. Double SOI wafer : effective to digital circuit in a pixel

3. Additional process : improve charge collection efficiency

SiO2

Si

Compensate charge accumulation

Reduce coupling capacitance

1.0E-10

1.0E-09

1.0E-08

1.0E-07

1.0E-06

1.0E-05

1.0E-04

-200 -150 -100 -50 0

AB

S(V

DET

I)[A

]

VDET-VIO_BPW [V]

MX1786D-1J-DSOI INTPIX8

1.0E-12

1.0E-11

1.0E-10

1.0E-09

1.0E-08

1.0E-07

1.0E-06

1.0E-05

1.0E-04

-200 -150 -100 -50 0

I [A

]

VDET-VIO_BPW [V]

MX1655D-1J-DSOI INTPIX7 ID#24

RSTx=1.8V

1.0E-09

1.0E-08

1.0E-07

1.0E-06

1.0E-05

1.0E-04

1.0E-03

0 50 100 150 200

I[A

]

VDET-VIO_BPW [V]

MX1594-D1J-DSOI-3 INTPIXh2

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Breakdown voltage: double SOI sensor I-V measurement

1.E-09

1.E-08

1.E-07

1.E-06

1.E-05

1.E-04

-10 10 30 50 70

I[A

]

Vdet-Vio_bpw[V]

double SOI INTPIX3g (T=23deg)

Double SOI 1st trial Double SOI 2nd trial

Recover breakdown voltages: Similar to the single SOI case

60V 160V

Still incomplete

Process improvement110V

Almost the same as NCZ/NFZ cases

2015(up-to-date)2014

Treatment of edge of SOI chip is incomplete.

N-type sensor

P-type sensor

P-type sensor

N-type sensor

3rd&4th5th

Residual of Vth shifts of various FET types(FETs grouped into 3 in VSOI2 setting)

NMOS

Thre

sho

ld v

olt

age

●VSOI2= 0V●VSOI2=-1V●VSOI2=-2V

●VSOI2=-3V●VSOI2=-4V●VSOI2=-5V

●VSOI2=-10V●VSOI2=-15V●VSOI2=-20V

●VSOI2=-25V

NMOS- - - pre-irrad

2MGy

FET threshold shifts and compensation in DSOIIV curves of an NMOS (2MGy irradiated) withChanging VDSOI2

S. Honda et al., “Total Ionization Damage Compensations in Double Silicon-on-Insulator Pixel Sensors”, PoS (TIPP2014)039. K. Hara et al., ”Initial Characteristics and Radiation Damage Compensation of Double Silicon-on-Insulator Pixel Device,”, PoS(VERTEX2014)033.

12

)V (Sensor Bias

0 2 4 6 8 10 12 14 16 18 20

Ch

arg

e (

AD

C c

oun

t)

0

1000

2000

3000

4000

5000

6000

preirrad

100kGy VSOI2=-10V

V_RST(preirrad)=550mV

V_RST(100kGy)=950mVINT_TIME=120ns

Response to infrared laser of 1064 nm wavelength and 10 ns pulse duration.

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The pixel images after 100 kGy could not obtain but recovered with VSOI2=-10V.

The average ADC count as function of the square root of the bias voltage for sensor.Obtained similar linearity and sensitivity to pre-irradiation with VSOI2=-10 V .

Pre-irrad

VSOI2=0V VSOI2=-10V

S. Honda et al., TIPP12014, 2-6 June 2014, Amsterdam

PIXEL2014 presentation by M. Yamada

N-type Double SOI pixel sensor

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SOI Pixel sensor with N-type, P-type (and double SOI wafers)Spatial resolution study using NFZ-FPIXb

P-type sensor study using PFZ-INTPIX7 compared with NFZ-INTPIX7

X-ray target (Cu)

500mmIC1

IC2

absorber

slit2

slit1

INTPIX7

slit1 slit2sample

NFZ-FPIXb

Front illumination

NFZ/PFZ-INTPIX7

Front illumination

FPIXb

KEK-PF monochromatic X-ray 16 keV

Pixel size 8 um x 512 x 192 pixels Pixel size 12 um x 1408 x 1408 pixels

12m

m

8mm~10Tr.

4Tr.

Spatial resolution

• Cu 8keV、20kV、2mA、front illumination, bias 100V

• Ratio 16μm slit、

INTPIX4(17μm)：0.57、FPIXb(8μm)：0.83

15

0

50

100

150

200

250

300

0 50 100 150 200 250 300 350G

ray

scal

eNumber of pixel

0

20

40

60

80

100

120

140

0 30 60 90 120 150 180

Gra

y sc

ale

Number of pixel

25μm 20μm 16μm 25μm 20μm 16μm

NFZ-INTPIX4 17um pixel NFZ-FPIXb 8um pixel

INTPIX4 FPIXb

16μm zoom-in

Vis

ible

lin

e

Dar

k lin

e

X-ray test chart + X-ray tube

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Spatial resolution (2)

JIMA chart (RT RC-05)

Au thickness 1um (very thin!)

After clustering

before clustering

X-ray tube: Target Cu

NFZ-FPIXbCu 20kV 10maBackbias 100V1ms x 2000fr.

8um slit can be seen

Energy resolution

• X-ray spectra Am241 at room temperature

• Energy resolution (FWHM) @13.9keV

INTPIX4 CZN：1.87 keV (13.4%)、FPIXb FZN：0.80 keV (5.8%)

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2011 JPS A. Takeda et al.

13.9keV

20.8keV

17.8keV

13.9keV

20.8keV

17.8keVCu 8.0keV

Mo 17.5keV

INTPIX4 CZN 200V back illumination FPIXb FZN 100V front illumination

Cu+Mo+Am241Am241

18

1.E-08

1.E-07

1.E-06

1.E-05

1.E-04

1.E-03

0 100 200 300 400

I[A

]

VDET-VIOBPW[V]

I[A] NCZ

I[A] NFZ

I[A] PFZ

Leakage current ofNCZ/NFZ/PFZ-INTPIX7

P-type SOI sensor: PFZ-INTPIX7 vs. NFZ-INTPIX7

PFZ SOI sensor has high leakage current and low breakdown voltage

Modification of P-type wafer fabrication process is required.

16 keV Monochromatic X-ray at KEK Photon FactoryBeam spot size 0.4 mm x 0.4 mmFront illumination, Vbb 150V

Beam spot

~34 pixels (12x34~0.4mm)

NFZ

PFZ

ADU

ADU

Preliminary

Preliminary

16keV peak

16keV peak

PFZ-500um thick

NFZ-500um thick

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Summary and future plan

SOI pixel sensor development since 2005SOI pixel sensor system with Gbit Ethernet (SEABAS2) works fine

Current issues:The back-gate effect will be suppressed by BPW process or double SOIRadiation hardness can be improved with double SOI

Initial test of double SOI, N-type, P-type sensors was successfulAll wafers need to be improved, especially p-type wafer

Future plan:Crosstalk study must be done with counting-type pixel sensorsCharge collection issue must be solved using novel idea of p/n implantation

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Thank you for your attention!

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Supplement

SOI Wafer for monolithic sensor

Smart cutTM by Soitec

High Resistivity Silicon:

N-type Czochralski, NCZ, 0.7 kOhm-cm, 300 mm-thick

N-type Float Zone, NFZ, 2-7k Ohm-cm, 500 mm-thick

P-type Czochralski, PCZ, 1k Ohm-cm, 300 mm-thick

P-type Float Zone, PFZ, 2-40k Ohm-cm, 500 mm-thick

Initial silicon

Oxidation

Implantation

Splitting

High R

Low R

Cleaning and

bonding

SOI wafer

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circuit sensor

Double SOI (DSOI) pixel sensor

Initial silicon

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Middle SOI: Additional shield layer

STEM image

SOI wafer

Double SOI N-type sensor (2011-2013) MPW11(MX1501),12-1(MX1542),12-2(MX1594)

Double SOI P-type sensor (2014-) MPW13-1(MX1655), MPW13-2(MX1711),

MPW14(MX1786), MPW15-1(MX1850)

Top SOI: SOI-CMOS