advanced vlsi sopc design flowaccess.ee.ntu.edu.tw/.../course_outline/sopc1.pdf · pp. 2 outline...

ACCESS IC LAB

Graduate Institute of Electronics Engineering, NTU

Advanced VLSIAdvanced VLSISOPC design flowSOPC design flow

Advisor: 吳安宇Speaker: 沈文中

ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU

pp. 2

OutlineOutlineWhat’s SOC?IP classificationIP reusable & benefitSOPC solution on FPGASOPC design flow


pp. 3

OutlineOutlineWhat’s SOC?

Definition of SOCAdvantage of SOC

IP classificationIP reusable & benefitSOPC solution on FPGASOPC design flow


pp. 4

SystemSystem--onon--aa--ChipChip

1. Use standard bus, to transfer data among blocks.

2. For bus IO, block reusable is benefit.3. IO pad of chip is the limit of freq. But freq. in

the same chip can be higher.


pp. 5

Changes in the Nature of IC Changes in the Nature of IC DesignDesign


pp. 6

Ex: JPEG video systemEx: JPEG video system


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SOCSOC製製程演進階段程演進階段


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SystemSystem--level IC Developmentlevel IC Development


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OutlineOutlineWhat’s SOC?IP classification

Soft IPFirm IPHard IP

IP reusable & benefitSOPC solution on FPGASOPC design flow


pp. 10

Types of IPTypes of IP1. Soft IP: (“Code”)

1. Synthesizable HDL description at RTL level2. Flexible: can be changed to suit an application3. Technology independent: may be re-synthesized

across process4. Significant IP protection risk


pp. 11

Types of IPTypes of IP1. Firm IP: (“synthesizable netlist +

structure”)1. Gate-level netlist optimized

structurally and topologically for performance and size

2. Floorplanning or placement without routing


pp. 12

Types of IP (cont.)Types of IP (cont.)3. Hard IP: (“physical”)

1. Ready for “drop in”2. Include layout and timing information3. Optimized for performance, size,

and power4. IP is easily protected


pp. 13

Categorizing Reusable BlocksCategorizing Reusable Blocks


pp. 14

Tradeoffs among types of blocksTradeoffs among types of blocks


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pp. 16

Engineering Productivity GapEngineering Productivity Gap

1. Engineering productivity has not been keeping up with silicon gate capacity for several years.

2. Companies have been using larger design teams, making engineers work longer hours, etc., but clearly the limit is being reached.


pp. 17

Why must IP Reuse?Why must IP Reuse?


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pp. 19

What is SOPC?What is SOPC?

FPGAEmbeddedProcessor Memory

Logic

High-Performance

I/O

Processor

CompleteSOPC Solution(System-On-a-Programmable-Chip)


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Introduce to SOPC solutionIntroduce to SOPC solutionSoft embedded processor design & prototyping environment


pp. 21

Introduce to SOPC solutionIntroduce to SOPC solution

Hard embedded processor design & prototyping environment


pp. 22

Excalibur Excalibur NiosNios Device SupportDevice SupportPerformance

(MIPS) Future PLD Architectures

EmbeddedEmbeddedCoreCore

TMTM

Excalibur MIPSExcalibur ARM200

APEX™ Devices

ACEX™ Devices30

50

100Mercury™ Devices

FLEX™ 10K Devices

0


pp. 23

Low-CostEmbedded Processor

High-PerformanceCustom DSP

Multi-ProcessorSystem

Flexibility & ScalabilityFlexibility & Scalability

500K GatesAvailable

ESB

ESB

ESB

ESB

ESB

ESB

ESB

ESB

ESB

ESB

ESB

ESB

ESB

ESB

ESB

ESB

ESB

ESB

ESB

ESB

ESB

ESB

ESB

ESB

Excalibur ARM Stripe

150K GatesAvailable

DSPDSP75K Gates Available

ACEX™ EP1K100

APEX EP20K200E

Excalibur XA10


pp. 24

NiosNios Development KitDevelopment KitNios 32-Bit and 16-Bit RISC CPU PeripheralsDevelopment Board Development Tools


pp. 25

Timer

IRQ

PBM CPU

UART

FLASH

SRAM

SerialPort

Configurable Soft Core Processor32-Bit Pipelined RISC ArchitectureLarge Internal Register FileFully synchronous interfaceConfigurable Data Path30 to 80 MIPS PerformanceDynamic Bus Sizing 12% of

NiosNios Embedded Processor CoreEmbedded Processor Core

Your DesignHere

EP20K200EAltera PLD


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pp. 27

NiosNios System OverviewSystem OverviewA complete Nios system module contains a Nios embedded processor and its associated system peripherals.

The SOPC Builder helps you easily specify options for the Nios system module.

Nios system module contains hardware and software sections


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NiosNios System Overview(cont.)System Overview(cont.)Peripheral components

Memory InterfaceRAM, ROM

Serial I/OUART

PIO(parallel IO)Seven SegmentLED, LCDUser defined Interface

Timer


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NiosNios System Overview(cont.)System Overview(cont.)The SOPC builder let NIOS module easy specified by using wizard

Almost constraint can be changed to fit our own design, such as peripheral library.


pp. 30

NiosNios System Overview(cont.)System Overview(cont.)Hardware & Software generation

Nios system module contains:Hardware : (HDL code) describe the hardware module -download by QuartsII

Software : (header file) define c program library to develop your own program

-download by NIOS SDK


pp. 31

Tool Design FlowTool Design Flow

Processor Design

Simulation Test Bench

C Header files

Custom Library

Boot monitor

Synthesis Place & Route

Cygnus/Red HatGNUPro

AlteraPLD

JTAGSerial

User Design

Purchased IP

ExecutableCode

HardwareConfiguration

File

Configure Processor

Select Peripherals

GenerateHardware Software

Download& Debug

User Code

S/W Libraries

RTOS

Peripheral Library


pp. 32

StepsStepsCreate your design

Create project fileCreate *.BDF file

Add SOPC into your designConnect your own block & IO pad to Nios CPUCompile & Pin AssignmentSoftware developmentDownload your design


pp. 33

Create a new projectCreate a new projectSelect File => New Project Wizard

Working DirectoryProject nameTop-level design name

Create a new project in the path C:\AVLSI\<your id>\lab2

Click finish


pp. 34

Create a new schematicCreate a new schematicCreate a *.bdf file, for placing SOPC system, include NIOS CPU & other block

Block design file


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StepsStepsCreate your designAdd SOPC into your design

Create CPUAdd peripheralsGenerate hardware & software design

Connect your own block & IO pad to Nios CPUCompile & Pin AssignmentSoftware developmentDownload your design


pp. 36

Create NIOS32 CPUCreate NIOS32 CPUSelect symbol from tool menu bar, And click Mega Wizard Plug-In Manager


pp. 37

Create Create megafunctionmegafunctionSOPC is one block of megafunction

Create a new megafunction, to familiar with it’s content


pp. 38

Use SOPC BuilderUse SOPC BuilderSelect Altera Excalibur Nios

Choose VerilogHDL to perform the soft core CPU


pp. 39

Add CPUAdd CPU

Click “Next”

Choose 32 bit RISC CPU,then click “Finish”


pp. 40

Add ComponentsAdd ComponentsClick “Add Peripheral” for adding it into your design


pp. 41

Current List of PeripheralsCurrent List of PeripheralsUARTPIOTimerSPIPWMIDEKeyboardPS2 MouseVGA

EthernetPCISRAMSDRAMFlashCompact FlashOn-chip RAMOn-chip ROMUser-Defined


pp. 42

PIO PeripheralPIO Peripheral1 to 32-bit Parallel I/O Port

Input OnlyOutput OnlyBi-directional Port

Edge Detection on InputsInterrupt Generation

Mask-ableIRQ Source


pp. 43

AddonAddon ComponentComponentPeripheral components

Memory InterfaceRAM, ROM, flash

Serial I/OUART

PIO(parallel IO)Seven SegmentLED, LCDUser defined Interface

Timer

NiosCPU

Ava

lon

™B

us

UserI/FNios System

Module

ExternalDevice

I/O

I/O

I/O

I/O

Altera PLD


pp. 44

The demo boardThe demo board


pp. 45





pp. 46

Choose OnChoose On--chip Memorychip MemoryFor Add boot_rom

Choose GERMS Monitor


pp. 47

UART

GERMS MonitorGERMS Monitor

Monitor Program Runs from On-Chip ROMDebugger Runs on Host PC or UNIX PlatformBasic Development Facilities:

Download CodeBurn FlashExamine/Modify MemoryRun Programs

DebugMonitor


pp. 48

GERMSGERMSG – GoE – Erase FlashR – RelocateM – MemoryS – Motorola S record: – Intel Hex recordCR – show next 64 Bytes of memoryEscape – Restart GERMS monitor


pp. 49





pp. 50

System ConfigurationSystem ConfigurationMain Program Memory

Code ExecutionMain Data Memory

Variables & StackHost Communication

Monitor STDIODebug Communication

GDB PortBoot ID Message

Monitor Prints at Start-up


pp. 51

System ConfigurationSystem ConfigurationBoot Device

Boot_romInterrupt Vector Table

sramHighest Performance Bus

Standard busSynthesis Target Family

APEX 20K Devices


pp. 52

Generate System ModuleGenerate System ModuleSoftware Development Kit (SDK)Hardware DesignSynthesis


pp. 53

What happen after GenerateWhat happen after GenerateSoftware

nios.h :define the peripheral address:define the memory map

Hardware A NIOS CPU module constructed by verilog code


pp. 54

IO have their addr./*

* File: nios.h

*

* This file is a machine generated address map

* for a Nios cpu named cpu.

* f:/我的文件/avlsi/r91943088/lab2/nios32.ptf

* Generated: 2002.12.21 19:29:11

*/

// The Memory Map

#define na_uart_1_debug ((np_uart *) 0x00000420)

#define na_uart_1_debug_irq 17

#define na_timer_0 ((np_timer *) 0x00000440)

#define na_timer_0_irq 18

#define na_led_pio ((np_pio *) 0x00000460)

#define na_button_pio ((np_pio *) 0x00000470)

#define na_button_pio_irq 19

#define na_ext_ram ((void *) 0x00040000)

#define na_ext_ram_end ((void *) 0x00080000)

#define na_ext_ram_size ((void *) 0x00040000)

#define na_ext_flash ((void *) 0x00100000)

Software GenerationSoftware Generation


pp. 55

Hardware Hardware GenereationGenereationAfter generation, a NIOS module appears in Symbol


pp. 56

StepsStepsCreate your designAdd SOPC into your designConnect your own block & IO pad to Nios CPUCompile & Pin AssignmentSoftware developmentDownload your design


pp. 57

Add IO PadAdd IO PadUse add symbol to add IO pad to schematic.


pp. 58

StepsStepsCreate your designAdd SOPC into your designConnect your own block & IO pad to Nios CPUPin Assignment & CompileDownload your design


pp. 59

Assign PinsAssign PinsCompile first

Assign the IO pins to the I/O Interface on develop board

Compile then


pp. 60



pp. 61

Software DevelopSoftware DevelopCPU contains hardware part and software part

Hardware part was created above

Software part is written in c or c++ language, then compiled into assembly code

Take an example for writing c++ program to control CPU change light when press switch


pp. 62

Define memory map& peripheral addr.

0111

0: input1:output2:bidrection

button

led

How to write codeHow to write code


pp. 63

How to write code(cont.)How to write code(cont.)

Change led light

Get data

Write data


pp. 64



pp. 65

Memory UsageMemory Usage*.srec is downloaded into SRAM, can’t still exist after reset

Flash memory store the data executed automatically when boot

SRAM256Kb

Data

Address

1Mb Flash

APEX

ROMFactory Factory APEX ImageAPEX Image

UserAPEX Image

User User SoftwareSoftware

140000


pp. 66

NIOS SDKNIOS SDKUNIX like environment

Open from ”Start Menu/program files/Altera/Excalibur NIOS 2.0/NIOS SDK Shell”


pp. 67

NIOS CommandNIOS Commandnios-build: Compile, Assemble & Link

Transpose c program into <program>.srec

nios-run: Download Executable & Runburn flash with <project>.hexout(hardware) or <program>.flash(software)Download *.srec to SRAM

srec2flash: Create Flash-bootable CodeConvert <program>.srec to <program>.flash


pp. 68

NiosNios RoutinesRoutinesnios-build hello.c (nb hello.c)

Builds program including compile, link and convert to SRECnios-run hello.srec (nr hello.srec)

Downloads using com1 and enters terminal modenr –p com2 hello.srec

Downloads using com2nr –x hello.srec

Downloads without entering terminal modenr –t

Enters terminal mode without download (Ctrl + C to exit)


pp. 69

Download routineDownload routinenr <project>.hexout -download hardware

designnr <program>.srec -download software

design


pp. 70

LABLABNIOS Tutorial Have a C code to generate sine wave and display to 7-segment LED. Program should read data from DIP SW as a value of delay loop. ( pi / 10)


pp. 71

HomeworkHomeworkUse Mega Plug-In Manager to generate NIOS with DIP SW and necessary peripheral device.Use Mega Plug-In Manager to generate a 4 by 4 multiplier.Have a verilog code to decode 8 bit binary to 7-segment.Have a C code to read two 4-bit data from DIP SW and send data to 4 by 4 multiplier. The multiplier output should connect to decoder directly to display answer.Use LA to read answer-data to verify, too.

advanced vlsi sopc design flowaccess.ee.ntu.edu.tw/.../course_outline/sopc1.pdf · pp. 2 outline...

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