altiroc asic for hgtd atlas

ALTIROCASIC for HGTD ATLAS

N. Seguin-MoreauOMEGA microelectronics group

Ecole Polytechnique & CNRS IN2P3http://omega.in2p3.fr

Collaboration IFAE, LAL, OMEGA, SLAC, SMU

http://omega.in2p3.fr/

High Granular Timing Detector (HGTD) ATLAS Phase II

• Granularité plus fine (que celle du calo EM) pour aider à l’identification des

particules

• Mesure de temps plus fine pour rejeter les jets de pile up en temps

2

Sensor = Low Gain Avalanche Diode (LGAD)

n-on-p Si detector with extra highly doped

p-layer

HGTD - ALTIROC ASIC - VLSI May 2018

FE ASIC (ALTIROC): to readout LGAD sensors. Provides a time measurement of each hit of events selected by L0/L1 trigger with a

resolution smaller than 30 ps/MIP

HGTD electronics: General architecture

3

z

• 2 disks/EC, 2 double sided Layers of LGAD sensors & ASIC /disk, Rin/Rout = 120/640 mm

• 3 952 modules of 2 x 4 cm2 /End Cap => total of 15 810 ASIC (23 000 with yield)

2 double-sided layers of

Si sensors & ASICs, large eta vs

low eta modularity

On detector electronics

On detector electronics FlexPeripheral on detector electronics

Final ASIC: 2 x 2 cm2

225 channels to readout 225 pixels of 1.3 x 1.3 mm2

4

ASIC requirements

LGAD pixel size (thickness ~ 45 µm) 1.3 x 1.3 mm2

Detector capacitance 3.4 pF

Collected charge (1 MIP) at gain = 20 9.2 fC

Dynamic range 20 MIPs

Preamplifier-discri jitter at gain = 20 < 20 ps

Time walk contribution < 10 ps

TDC binning 20 ps (TOA) and 40 (or 80) ps (TOT)

TDC range 2.5 ns (TOA) and 20 ns (TOT)

Number of bits / hit 7 for TOA and 9 for TOT

FIFO latency 10 µs/ 35 µs latency for L0 (L1) trigger

Luminosity counters per ASIC 7 bits (sum) + 5 bits (outside window)

Number of channels/ASIC 225

elink driver bandwidth 320 Mb/s, 640 Mb/s and 1.28 Gb/s

Total power per area (ASIC) < 300 mW/cm2 (< 1.2 W)

TID and neutron fluence Inner region: 4.5 MGy, 4.5 x 10 15 n/cm2

Outer region: 2.1 MGy, 4.0 x 10 15 n/cm2

Electronics total contribution

<30ps

=> 5 mW/ch or 4 mA/pixel

=>TSMC 130nm


Time resolution: Time Walk, Jitter, TDC bin

5

Time Walk

Jitter

Vthout_PA (with noise)

out_discri<TOA> pk-pk = 100 ps

Jitter = rms of this dispersion

TOA

TOA

TOT

TOT- -

LGAD current

out_PATime walk: the voltage value Vo is

reached at different time for signal of

different amplitudes

Jitter: the noise is summed to

the signal, causing amplitude

variations

Due to physics signal duration and preamp speed

Mostly due to electronic noise

TDCTime to Digital Converter

---- TOA coded on 7 bits

---- TOT coded on 9 bits

𝝈𝒕𝑻𝑫𝑪 =

𝑻𝑫𝑪𝒃𝒊𝒏

𝟏𝟐

𝝈𝒕𝑻𝑾 =

𝒕𝒓𝒊𝒔𝒆𝑽𝒕𝒉𝑺

𝑹𝑴𝑺

𝝈𝒕𝑱=

𝑵

𝒅𝑽𝒅𝒕

=𝒕𝒓𝒊𝒔𝒆𝑺/𝑵

Total Time resolution : 𝝈𝒕𝟐 =

𝒕𝒓𝒊𝒔𝒆𝑽𝒕𝒉

𝑺 𝑹𝑴𝑺

𝟐

+𝒕𝒓𝒊𝒔𝒆

𝑺/𝑵

𝟐+

𝑻𝑫𝑪𝒃𝒊𝒏

𝟏𝟐

𝟐

Time Walk correction

• Can be corrected using Time Over Threshold technique

• TOA position vs TOT value: polynomial fit , 700 ps variation corrected to better than 10 ps

6

Variation of 700 ps for ΔQinj = 20 MIP

𝝈𝒕𝑻𝑾 =

𝒕𝒓𝒊𝒔𝒆𝑽𝒕𝒉𝑺

𝑹𝑴𝑺

TO

A (

ns)

Qinj (MIP)

TOT (ns)

TO

A (

ns)


Jitter

7

• Jitter is given by :

• Optimum value: t10-90_PA= td (current duration)

• Gives ps/fC as scales with 1/Qin

• Electronics noise en given by the input transistor

transconductance gm:

PA

dPA

in

dn

in

dPAd

PA

nJ

tt

tt

Q

Ce

Q

ttC

t

e

dtdV

N

_9010

22

_9010

22

_9010

_901022/

d

in

dnJ

t tQ

Ce

Dominated by sensor

Electronics only gives

the spectral density of

the input transistor en

Dm

nqI

kT

g

kTe

22

Cd: detector capacitance

t 10_10_PA : rise time of the PA

td= drift time of the detector

e n preamp noise density

0,000

0,500

1,000

1,500

2,000

2,500

0 1 2 3 4

e_n (

nV

/sqrt

Hz)

Id (mA)

noise spectral density

LGAD signal


ALTIROC: Front-End Channel/pixel

8

Each FE channel made of

A preamplifier followed by a discriminator: Time walk correction made with a Time over Threshold (TOT)

architecture

Two TDC (Time to Digital Converter): Time of Arrival (TOA) + Time Over Threshold (TOT) measurement

TOA: range of 2.5 ns and a bin of 20 ps (7 bits)

TOT: range of 20 ns and a bin of 40 ps (9 bits)

One Local memory (FIFO): to store the 17 bits of the time measurement until L0/L1 trigger

Data transmitted/pixel: 17 bits + 8 bits for channel number = 25 bits @0.8MHz or 1MHz + discri output for

the luminosity measurement


• First prototype, which integrates only the analog part submitted in Dec 2016

• 8 channels:• 4 channels for 1x1 mm2 sensors (2pF)

• 4 channels for 3x3 mm2 sensors (20 pF): NOT USED

• 2 pF Preamp: Common source configuration (Voltage PA = VPA)

− Power < 500 µW: Id (M1) = 300 µA, I (M2)= 60 µA

− Normal VT trans except for the PMOS follower

− Low input capacitance: ~ 300 fF,

− Low noise: 1.2 nV/√Hz

− BW tuneable with Cp: 1 GHz down to 200 MHz

− R2=25K: for DC bias, Rin ~ 1.6 KΩ, Fall time= 2.2 RinCd

− I leakage sensor: absorbed by R2

− Can be disabled by Slow Control

9

ALTIROC0

POST LAYOUT SIMULATIONS (LGAD) Cd = 2 pF Cd = 4 pF Cd = 10 pF

Preamplifier Bandwidth (MHz) 550 560 500

Noise (mV) 0.54 0.57 0.57

S/N 93 54 30

Jitter (ps) with LGAD gain of 20 10 16 32

PA BW tuned with Cp, tr_pa (δ) = td/2

d

min

dJ

t tg

kT

Q

C 2


ALTIROC0 measurements

10

• Submitted mid December 2016, received in March 2017

• Area = 3.4 x 3.4 mm2, thickness=300µm: large chip to fit 1 x 1 mm2 sensors

(for testbeam)

• 8 channels: Four 2pF-channels and four 20 pF-channels– Characterization of 2 pF-channels only

– Characterization of the TOT architecture only. CFD architecture also tested but tunings quite tricky

and performance similar to the TOA/TOT architecture

– Scope measurements, injection through internal Ctest

• Identical test boards for testbench and test beam measurements:

– Testbench: ASIC alone, wire bonded on the board

– Testbeam: ASIC bump bonded on the sensor (1 x 1 mm2 sensor, 42 µm

thickness => C sensor ~ 2.5 pF)

Discri ouputs

Discriminator

output –ch0

TO

A

TO

E


ASIC and testboard parasitic capacitance measurement

11

As the jitter is proportional to Cd, it is Important to extract the parasitic capacitance (Testboard, ASIC ..)

Cparasitic extracted from the fit of 1/Vout_pa versus Cdetector:

– Vout_pa measured (Scurves) for various Cd (soldered on the testboard) and Qinj=5 fC, 10 fC , 20 fC (Injection of 50 mV, 100 mV or 200 mV through internal Ctest = 100 fF)

1

𝑉𝑜𝑢𝑡_𝑝𝑎=

𝐶𝑑𝐺𝑝𝑎 ∗ 𝑄𝑖𝑛𝑗

+𝐶𝑝𝑎𝑟𝑎𝑠𝑖𝑡𝑖𝑐

𝐺𝑝𝑎 ∗ 𝑄𝑖𝑛𝑗Gpa : Gain of the preamp

• Measurement on a testboard on which the ASIC inputs are wire bonded on the PCB

=> C parasitic ASIC + C parasitic testboard= 2.8 pF

• Slope obtained with measurement and with simulations are in good agreement : measured preamp gain= 0.85 * simulated

preamp gain

ASIC and testboard parasitic capacitance (1)

12

1

𝑉𝑜𝑢𝑡_𝑝𝑎=

𝐶𝑑𝐺𝑝𝑎 ∗ 𝑄𝑖𝑛𝑗

+𝐶𝑝𝑎𝑟𝑎𝑠𝑖𝑡𝑖𝑐

𝐺𝑝𝑎 ∗ 𝑄𝑖𝑛𝑗Measurement

Post layout simulations


Test bench measurements

13

800 ps

Soldered Cd = 2 pF => Ctot = 4.8 pF



@Christina Agapopoulou, LAL

TO

A (

ns)

TO

A (

ns)

Qinj (fC)

Qinj (fC)

TO

A (

ps)

TOT (ps)HGTD - ALTIROC ASIC - VLSI May 2018

Test bench measurements with ASIC + sensor

14

• 1x1 mm² sensors fabricated by CNM/IFAE Barcelona, expected C

sensor ~ 2.5 pF

• Bump-bonded to ALTIROC0 at Barcelona

• Sensor biased at - 80 V and – 130 V

• Test pulse injection through internal Ctest=0.1 pF

• After reworking on the grouding, ASIC+Sensor jitter measurement

gives = 30 ps @ 10 fC and ~ 25 mV (for HV= 80 or 130V)

=> C sensor = 5.4 pF – 0.7 pF = 4.7 pF

42 ps @10fC

reduced down to 30 ps

after working on grounding

Jitter meas. ASIC+Sensor vs Qinj

Testbeam measurements with ASIC + sensor

15

• 1x1 mm² sensors fabricated by CNM/IFAE Barcelona

• Bump-bonded to ALTIROC0 at Barcelona

• Sensor biased at - 80 V

• Test pulse injection through internal Ctest=0.1 pF

• Testbeam measurement ASIC+Sensor (LGAD signal)= 48 ps

Test beam at CERN 8-12 Sept 2017

Testbeam jitter (ASIC+Sensor)

Time resolution measurement:

σfit of tASIC – tSiPM distribution

Time resolution: 48 ps


ALTIROC1 prototype (Mid-June 2018 submission)

16

ALTIROC1 = Second ALTIROC ASIC prototype with 25 complete FE channels to readout 5 x 5 sensor cells of 1.3 mm x 1.3 mm

(6.5 mm x 6.5 mm) + Phase shifter

3 Labs involved: OMEGA (analog Part), SLAC (Digital part: TDC and FIFO), SMU (Phase shifter)

ASIC size: 7,5 x 7 mm² taking into account the pads on the right side of the ASIC (7.5 mm) and also pads (for bias, probes ...)

on the top side for debug (top pads only for this prototype version)


ALTIROC1 Input stage: Voltage PA or TZ PA

17

25 channels: 15 channels with Voltage preamp (VPA) + 10 Channels with a Transimpedence Preamplifier (similar to the

amplifier designed by Univ Santa Cruz with discrete components and used for sensor characterization)

Fall time given by 2.2* Rin_pa * Cd

Rin_TZ pa =150 Ω whereas Rin_Voltage PA ~ 1.5 KΩ

=> TOT_TZ (few ns) very different from TOT_VPA


VPA, TZ PA and discriminator simulations

18

Cd= 3.5 pF

LGAD signal

Jitter similar for TZ and VPA architectures but

TOA vs TOT sensitivity very different between these

2 architectures

=> TDC for TOT meas. different for VPA and TZ_PA

Jitte

r(p

s)

Input (MIP) Input (MIP)

TOT

TO

T (

ns)

TO

A (

ns)

Voltage PA

TZ preamp

V PA

TZ

V PATZ

VPA• Resolution: 40 ps• Range: 18 ns• 9 bits

TZ• Resolution: 20 ps• Range: 3 ns• 8 bits


TDC: one for TOA and one for TOT measurement

19

TOT VPA• Resolution: 40ps• Range: 18ns• 9 bits

TOT TZ• Resolution: 20ps• Range: 3ns• 8 bits

TOA (VPA or TZ)• Resolution: 20ps• Range: 2.5 ns• 7 bits

TOT: coarse delay line + TOA TDC

@ Bojan Markovic, SLAC

TOA TDC Architecture (Simplified): Vernier Delay Line

20

1 2 3 4 128F1 F2 F3 F4 F128

120ps 120ps 120ps 120ps 120ps

1 2 3 4 128S1 S2 S3 S4 S128

140ps 140ps 140ps 140ps 140ps

Q1 Q2 Q3 Q4 Q128

Bin2

Q2Q1

Bin3

Q3Q2

Bin4

Q4Q3

Bin128

Q128Q128

Bin1

Q10

Time-to-Digital Converter (TDC)

START

STOP

Simplified Block Diagram:

STOP signal propagatesin the Fast Delay Line(Delay of one cell = 120 ps)

START signal propagatesin the Slow Delay Line(Delay of one cell = 140 ps)

• The START pulse comes first and initializes the TDC operation.• The STOP pulse follows the START with a delay that represents the time interval to be digitalized.• At each tap of the Delay Line the STOP signal catches up to the START signal by the deference of the propagation delays of cells in Slow and Fast branches of

the delay line: i.e. 140ps – 120ps = 20ps that represents the LSB of time measurement.• The number of cells necessary for STOP signal to surpass the START signal represents the result of TDC conversion.• TDC range is equal to 128*20ps = 2.56ns

2.5ns

Clock

STOP

Event

Detection

2.5ns Measurement Window

START

ToA

Differential shunt capacitor voltage-controlled delay cells

Local FIFO 19x400 (SRAM)

21

SRAM Cell (10T configuration):

Standard 6T cell Configuration

Additional buffers in order to allow for simultaneous Read/Write operation within the same clock period.

Dimensions:6.57um x 2.18um = 14.3226um^2

Layout (provisional):

+ + ++

SRAM word length: 19bits• 1 HIT bit• 7 TOA bits• 9 TOT bits• 2 extra debugging bits:

• TOA overflow bit• 1 extra Vernier TDC bit for

TOT measurement

SRAM depth: 400 (10µs data)

ALTIROC1

22

~ 7 mm

~ 8

mm

Altiroc1 layout

22

S

R

A

M

TO

T T

DC

TOA TDC

Probes and SC

Analog Part

1.3 mmOne pixel layout

1.3

mm

Submission : 13 June 2018


Clock tree

• Clock tree (pulser command , clocks): 4x4 channels

• Delay : 700 ps

• tr10-90 = 130 ps

23

VPA

VPA

VPA

VPA

VPA

VPA

VPA

VPA

VPA

VPA

VPA

VPA

VPA

VPA

VPA

TZ

TZ

TZ

TZ

TZ

TZ

TZ

TZ

TZ

TZ

VPA: Voltage preamp

TZ: Transimpedance preamp


SUMMARY

24

• Performance quite good on testbench but

discrepancy between measurements and

simulations to be understood– ~ 25 ps jitter obtained on test bench at Q = 10 fC with test pulse

and Ctot = 2 pF + 2.8 pF

• ASIC+sensor: Testbench and testbeam measurements

give a larger detector capacitance than expected

– 30 ps jitter obtained on test bench at Qinj = 10 fC with testpulse

and sensor connected

– 48 ps in testbeam

• ALTIROC1: 25 channels (PA+discri+TDC+FIFO)

– Submission mid June 2018

– Radiation tests in 2018 -2019

• Final ASIC: 225 channels with all the readout partHGTD - ALTIROC ASIC - VLSI May 2018

BACKUP

25HGTD - ALTIROC ASIC - VLSI May 2018

Arming discriminator

measurements

Discriminator

output –ch0

TO

A

TO

E

Test bench setup

26

− Scope measurements of TOA and TOT and Trigger efficiency

meeasurement (Scurves)

− On testbench we can’t inject LGAD currents

=> Injection of a Voltage step through the integrated Ctest = 100 fF to

simulate the input charge:

− Qinj=100 mV x 100 fF=10 fC

− Waveform of the Input current is then a dirac (δ) current with a drift time td equal

to the rise time of the voltage pulse

500 ps 700 ps

1.2 ns

𝐼𝑖𝑛 =𝑑𝑄𝑖𝑛𝑗

𝑑𝑡𝑎𝑛𝑑 𝑄𝑖𝑛𝑗 = 𝑉𝑖𝑛. 𝐶𝑡𝑒𝑠𝑡

Discri ouputs

TOT


Internal pulser

27

• To calibrate t0 and TOT

External clocks needed by the TDC must exhibit a good phase stability

(Phase jitter and drift between clocks between different ASIC must be

< 5 ps)

Calibration of the absolute value of the phase:

Measurement of t0 of each ASIC and channel thanks to an internal

pulser

• Principle:

Programmable current (DAC 6 bits) that flows in a resistor R and that

is interrupted by an external cmd pulse => Voltage step (=-R*IDAC that

is sent to the internal Ctest capacitor of each channel)

Dynamic range: 7,7 mV (LSB) to 500 mV or 1,5 fC up to 100 fC

1 MIP (10 fC)

Using internal pulser

Using external picosecond generatorVstep

Out_pa


28

ALTIROC0: Preamp post layout simulations (LGAD signal)

d

min

dJ

t tg

kT

Q

C 2

POST LAYOUT SIMULATIONS (LGAD) Cd = 2 pF Cd = 4 pF Cd = 10 pF

Preamplifier Bandwidth (MHz) 550 560 500

Noise (mV) 0.54 0.57 0.57

S/N 93 54 30

Jitter (ps) with LGAD gain of 20 10 16 32

PA BW tuned with Cp, tr_pa (δ) = td/2

Simulation Cd= 2 pF

Vout_pa @ 10 fC

With LGAD input signal, tr_pa = 680 ps

With Ctest input, tr_pa = 355 ps

LGAD input signal


• To extract the parasitic capacitance of the ASIC alone, we measured 1/Vout_pa on a testboard on which the ASIC inputs were

not wire bonded on the PCB => C parasitic ASIC alone = 0.7 pF (in good agreement with simulations – due to prot diode, C input

trans)

ASIC and testboard parasitic capacitance (2)

29

C parasitic ASIC + C parasitic testboard= 2.8 pF => C parasitic testboard = 2.1 pF, which is larger than expected (= 1 pF)


Testbench: jitter measurements/Simulations vs Ctot

30

• Measurements with testboard on which the ASIC inputs are wire bonded

• Ctot is then equal to Cd (soldered) + Cparasitic (Testboard +ASIC) = Cd (soldered) + 2.8 pF

Jitter measurement

10fC through Ctest

C para = 2.8 pF

Jitter simulation (post layout)

10fC through Ctest

Cpara = 0.7 pF

20 ps

Ctest inj. 10 fC

td = 100 ps

Test bench measurement quite good:

20 ps @ Ct=4.2 pF but

discrepancy Measurement / Simulation:


Attempt to understand discrepancy measured jitter and simulated jitter

31

tr measurement

10 fC through Ctest

tr simulation (post layout)

10 fC through Ctest

Rise time (tr_pa)

Out_pa measurement

Out_pa sim (post layout)

• tr_pa: 30 - 40 % difference between simulation (~ 600 - 700ps) and measurement (~ 750 ps- 850 ps)

Preamp too slow (in simul and measurement): tr should be 300 ps for a dirac current input.

(Problem identified: position of the switch in serie with Cp used to tune the BW)

• S = out_pa: small difference, about 10-15 % difference between measurement and simulation

• N = Noise: constant with Cd, simulation: 600 µV, Measurement 700 µV

Out_pa (10 fC injected through Ctest)

jitter = tr_pa / (S/N)


Power Consumption Summary

32

Time-to-Digital Converters

TOA TDC (10% occupancy) TOT TDC (10% occupancy)

Vernier DL TDC Coarse + Vernier DL TDCCoarse + Vernier DL TDC TZ PA

Coarse + Vernier DL TDC Voltage PA

405 µW 350 µW 360 µW 500 µW

SRAM 19x400

Read simultaneous with Write operation Read disables the Write operation

Write @ 40MHz(10% occupancy)

Write & Read @ 40MHz(10% occupancy)

Write @ 40MHz(10% occupancy)

Read @ 40MHz

125 µW 460 µW 125 µW 180 µW


altiroc asic for hgtd atlas

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