am26c32 クワッド差動ライン・レシーバ datasheet (rev. l)over operating free-air...

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英語版のTI製品についての情報を翻訳したこの資料は、製品の概要を確認する目的で便宜的に提供しているものです。該当する正式な英語版の最新情報は、www.ti.comで閲覧でき、その内容が常に優先されます。TIでは翻訳の正確性および妥当性につきましては一切保証いたしません。実際の設計などの前には、必ず最新版の英語版をご参照くださいますようお願いいたします。

English Data Sheet: SLLS104

AM26C32JAJSGF8L –DECEMBER 1990–REVISED OCTOBER 2018

参参考考資資料料

AM26C32 ククワワッッドド差差動動ラライインン・・レレシシーーババ

1

1 特特長長1• ANSI TIA/EIA-422-B、TIA/EIA-423-B、ITU勧告

V.10およびV.11の要件を満たす、または超える仕様

• 低消費電力、ICC = 10mA（標準値）• ±200mVの感度で±7Vの同相範囲• 入力ヒステリシス：60mV（標準値）• tpd：17ns（標準値）• 5V単一電源で動作• 3ステート出力• 入力フェイルセーフ回路• AM26LS32デバイスの改良版• 車載対応Q-Tempで利用可能

2 アアププリリケケーーシショョンン• 高信頼性車載機器• ファクトリ・オートメーション• ATM/キャッシュ・カウンタ• スマート・グリッド• AC/サーボ・モータ・ドライブ

3 概概要要AM26C32デバイスは、平衡または不平衡デジタル・データ伝送用クワッド差動ライン・レシーバです。イ

ネーブル機能は4つのレシーバすべてに共通で、アクティブHIGHまたはアクティブLOWの入力を選択できます。3ステート出力により、バス構成システムに直接接続できます。フェイルセーフ設計により、入力が

オープンの場合、出力は常にHIGHであることが規定されています。AM26C32デバイスは、バイポーラとCMOSトランジスタを組み合わせたBiCMOSプロセスで製造されています。このプロセスは、バイポーラの

高電圧および大電流にCMOSの低消費電力を組み合わせることで、ACおよびDC性能を維持しながら消費電力を通常のAM26LS32の1/5に削減します。

製製品品情情報報(1)型型番番パパッッケケーージジ本本体体ササイイズズ（（公公称称））

AM26C32N PDIP (16) 19.30mm×6.35mmAM26C32NS SO (16) 10.20mm×5.30mmAM26C32D SOIC (16) 9.90mm×3.90mmAM26C32PW TSSOP (16) 5.00mm×4.40mmAM26C32J CDIP (16) 21.34mm×6.92mmAM26C32W CFP (16) 10.16mm×6.73mmAM26C32FK LCCC (20) 8.90mm×8.90mm

(1) 提供されているすべてのパッケージについては、巻末の注文情報を参照してください。

概概略略回回路路図図

http://www-s.ti.com/sc/techlit/SLLS104.pdfhttp://www.tij.co.jp/product/jp/am26c32?qgpn=am26c32http://www.tij.co.jp/product/jp/AM26C32?dcmp=dsproject&hqs=pfhttp://www.tij.co.jp/product/jp/AM26C32?dcmp=dsproject&hqs=sandbuysamplebuyhttp://www.tij.co.jp/product/jp/AM26C32?dcmp=dsproject&hqs=tddoctype2http://www.tij.co.jp/product/jp/AM26C32?dcmp=dsproject&hqs=swdesKithttp://www.tij.co.jp/product/jp/AM26C32?dcmp=dsproject&hqs=supportcommunity

2

AM26C32JAJSGF8L –DECEMBER 1990–REVISED OCTOBER 2018 www.ti.com

Copyright © 1990–2018, Texas Instruments Incorporated

目目次次1 特特長長.......................................................................... 12 アアププリリケケーーシショョンン ......................................................... 13 概概要要.......................................................................... 14 改改訂訂履履歴歴................................................................... 25 Pin Configuration and Functions ......................... 36 Specifications......................................................... 4

6.1 Absolute Maximum Ratings ...................................... 46.2 ESD Ratings.............................................................. 46.3 Recommended Operating Conditions....................... 46.4 Thermal Information ................................................. 46.5 Electrical Characteristics........................................... 56.6 Switching Characteristics .......................................... 56.7 Typical Characteristics .............................................. 6

7 Parameter Measurement Information .................. 78 Detailed Description .............................................. 8

8.1 Overview ................................................................... 88.2 Functional Block Diagram ......................................... 8

8.3 Feature Description................................................... 88.4 Device Functional Modes.......................................... 9

9 Application and Implementation ........................ 109.1 Application Information............................................ 109.2 Typical Application ................................................. 10

10 Power Supply Recommendations ..................... 1211 Layout................................................................... 12

11.1 Layout Guidelines ................................................. 1211.2 Layout Example .................................................... 12

12 デデババイイススおおよよびびドドキキュュメメンントトののササポポーートト ....................... 1312.1 ドキュメントの更新通知を受け取る方法..................... 1312.2 コミュニティ・リソース ................................................ 1312.3 商標 ....................................................................... 1312.4 静電気放電に関する注意事項 ................................ 1312.5 Glossary ................................................................ 13

13 メメカカニニカカルル、、パパッッケケーージジ、、おおよよびび注注文文情情報報 ................. 13

4 改改訂訂履履歴歴

Revision K (June 2015) かからら Revision L にに変変更更 Page

• Changed II unit value From: µA To: mA in the Electrical Characteristics table...................................................................... 5

Revision J (February 2014) かからら Revision K にに変変更更 Page

• 「ピン構成および機能」セクション、「ESD定格」表、「機能説明」セクション、「デバイスの機能モード」セクション、「アプリケーションと実装」セクション、「電源に関する推奨事項」セクション、「レイアウト」セクション、「デバイスおよびドキュメントのサポート」セクション、「メカニカル、パッケージ、および注文情報」セクションを追加...................................................................................... 1

Revision I (September 2004) かからら Revision J にに変変更更 Page

• ドキュメントを新しいTIデータシート形式に更新 - 仕様変更なし ................................................................................................... 1• 「注文情報」表を削除 ................................................................................................................................................................ 1• 「特長」を更新........................................................................................................................................................................... 1• Added ESD Warning .............................................................................................................................................................. 3

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AM26C32www.ti.com JAJSGF8L –DECEMBER 1990–REVISED OCTOBER 2018


5 Pin Configuration and Functions

D, N, NS, PW, J or W Package16-Pin SOIC, PDIP, SO, TSSOP, CDIP, or CFP

Top ViewFK Package20-Pin LCCC

Top View

(1) NC – no internal connection.

Pin FunctionsPIN

I/O DESCRIPTIONNAME LCCC SOIC, PDIP, SO,TSSOP, CFP, or CDIP1A 3 2 I RS422/RS485 differential input (noninverting)1B 2 1 I RS422/RS485 differential input (inverting)1Y 4 3 O Logic level output2A 8 6 I RS422/RS485 differential input (noninverting)2B 9 7 I RS422/RS485 differential input (inverting)2Y 7 5 O Logic level output3A 13 10 I RS422/RS485 differential input (noninverting)3B 12 9 I RS422/RS485 differential input (inverting)3Y 14 11 O Logic level output4A 18 14 I RS422/RS485 differential input (noninverting)4B 19 15 I RS422/RS485 differential input (inverting)4Y 17 13 O Logic level outputG 5 4 I Active-high selectG 15 12 I Active-low selectGND 10 8 — Ground

NC (1)

1

— — Do not connect61116

VCC 20 16 — Power Supply


4



(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratingsonly, which do not imply functional operation of the device at these or any other conditions beyond those indicated under RecommendedOperating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) All voltage values, except differential voltages, are with respect to the network ground terminal.

6 Specifications

6.1 Absolute Maximum Ratingsover operating free-air temperature range (unless otherwise noted) (1)

MIN MAX UNITVCC Supply voltage (2) 7 V

VI Input voltageA or B inputs –11 14

VG or G inputs –0.5 VCC + 0.5

VID Differential input voltage –14 14 VVO Output voltage –0.5 VCC + 0.5 VIO Output current ±25 mATstg Storage temperature -65 150 °C

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.2 ESD RatingsVALUE UNIT

V(ESD) Electrostatic dischargeHuman body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1) ±3000

VCharged-device model (CDM), per JEDEC specification JESD22-C101 (2) ±2000

6.3 Recommended Operating Conditionsover operating free-air temperature range (unless otherwise noted)

MIN NOM MAX UNITVCC Supply voltage 4.5 5 5.5 VVIH High-level input voltage 2 Vcc VVIL Low-level input voltage 0 0.8 VVIC Common-mode input voltage -7 +7 VIOH High-level output current –6 mAIOL Low-level output current 6 mA

TA Operating free-air temperature

AM26C32C 0 70

°CAM26C32I –40 85AM26C32Q –40 125AM26C32M –55 125

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics applicationreport, SPRA953.

6.4 Thermal Information

THERMAL METRIC (1)AM26C32

UNITD (SOIC) N (PDIP) NS (SO) PW (TSSOP)16 PINS 16 PINS 16 PINS 16 PINS

RθJA Junction-to-ambient thermal resistance 73 67 64 108 °C/W

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(1) All typical values are at VCC = 5 V, VIC = 0, and TA = 25°C.(2) The algebraic convention, in which the less positive (more negative) limit is designated minimum, is used in this data sheet for common-

mode input voltage.

6.5 Electrical Characteristicsover operating free-air temperature range (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP (1) MAX UNIT

VIT+Differential input high-thresholdvoltage

VO = VOH(min), IOH = –440µA

VIC = –7 V to 7 V 0.2 VVIC = 0 V to 5.5 V 0.1

VIT–Differential input low-thresholdvoltage VO = 0.45 V, IOL = 8 mA

VIC = –7 V to 7 V –0.2 (2) VVIC = 0 V to 5.5 V –0.1 (2)

Vhys Hysteresis voltage (VIT+ – VIT−) 60 mVVIK Enable input clamp voltage VCC = 4.5 V, II = –18 mA –1.5 VVOH High-level output voltage VID = 200 mV, IOH = –6 mA 3.8 VVOL Low-level output voltage VID = –200 mV, IOL = 6 mA 0.2 0.3 V

IOZOFF-state (high-impedance state)output current VO = VCC or GND ±0.5 ±5 µA

II Line input currentVI = 10 V, Other input at 0 V 1.5 mAVI = –10 V, Other input at 0 V –2.5 mA

IIH High-level enable current VI = 2.7 V 20 μAIIL Low-level enable current VI = 0.4 V –100 μAri Input resistance One input to ground 12 17 kΩICC Quiescent supply current VCC = 5.5 V 10 15 mA

(1) All typical values are at VCC = 5 V, TA = 25°C.

6.6 Switching Characteristicsover operating free-air temperature range, CL = 50 pF (unless otherwise noted)

PARAMETER TEST CONDITIONSAM26C32CAM26C32I

AM26C32QAM26C32M UNIT

MIN TYP (1) MAX MIN TYP (1) MAXtPLH Propagation delay time,

low- to high-leveloutput

See Figure 2

9 17 27 9 17 27 ns

tPHL Propagation delay time,high- to low-leveloutput

9 17 27 9 17 27 ns

tTLH Output transition time,low- to high-leveloutput

See Figure 2

4 9 4 10 ns

tTHL Output transition time,high- to low-leveloutput

4 9 4 9 ns

tPZH Output enable time tohigh-level

See Figure 3

13 22 13 22 ns

tPZL Output enable time tolow-level

13 22 13 22 ns

tPHZ Output disable timefrom high-level

See Figure 3

13 22 13 26 ns

tPLZ Output disable timefrom low-level

13 22 13 25 ns


±1

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put

Vol

tage

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Logic Input Current - mA

HIGHLOW

C001

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6.7 Typical Characteristics

Figure 1. Output Voltage vs Input Current


TEST CIRCUIT

Device

Under

Test

G Input

G Input

VCCS1

RL = 1 kΩ

CL = 50 pF

(see Note A)

VID = ±2.5 V

VOLTAGE WAVEFORMS

tPZL, tPLZ Measurement: S1 to VCC

tPZH, tPHZ Measurement: S1 to GND

1.3 VG

G

(see Note B)

Output

(with VID = 2.5 V)

Output

(with VID = −2.5 V)

tPZH tPHZ tPZH tPHZ

tPZL tPLZ tPZL tPLZ

VOH −0.5 V

VOL + 0.5 V

VOH −0.5 V

VOL + 0.5 V

3 V

0 V

3 V

0 V

VOH

VOL

VOH

VOL

1.3 V

50%

50%

A Input

B Input

TEST CIRCUIT VOLTAGE WAVEFORMS

0 V

Output

VOH

VOL10%

90%90%

10%

tTLH tTHL

tPLHtPHL

2.5 V

−2.5 V

50%

Input

Device

Under

Test

A

B

VCC

CL = 50 pF

(see Note A)Input

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7 Parameter Measurement Information

A. CL includes probe and jig capacitance.

Figure 2. Switching Test Circuit and Voltage Waveforms

A. CL includes probe and jig capacitance.B. The input pulse is supplied by a generator having the following characteristics: PRR = 1 MHz, duty cycle ≤ 50%, tr = tf

= 6 ns.

Figure 3. Enable/Disable Time Test Circuit and Output Voltage Waveforms


Input

VCC

EQUIVALENT OF A OR B INPUT TYPICAL OF ALL OUTPUTS

Output

VCCVCC

1.7 kΩ

NOM

GND GND

1.7 kΩ

NOM17 kΩ

NOM

288 kΩ

NOM

VCC (A inputs)

or

GND (B inputs)

Input

GND

EQUIVALENT OF G OR G INPUT

8



8 Detailed Description

8.1 OverviewThe AM26C32 is a quadruple differential line receiver that meets the necessary requirements for NSI TIA/EIA-422-B, TIA/EIA-423-B, and ITU Recommendation V.10 and V.11. This device allows a low power or low voltageMCU to interface with heavy machinery, subsystems and other devices through long wires of up to 1000m, givingany design a reliable and easy to use connection. As any RS422 interface, the AM26C32 works in a differentialvoltage range, which enables very good signal integrity.

8.2 Functional Block Diagram

8.3 Feature Description

8.3.1 ±7-V Common-Mode Range With ±200-mV SensitivityFor a common-mode voltage varying from -7V to 7V, the input voltage is acceptable in low ranges greater than200 mV as a standard.

8.3.2 Input Fail-Safe CircuitryRS-485 specifies that the receiver output state should be logic high for differential input voltages of VAB ≥ +200mV and logic low for VAB ≤ –200 mV. For input voltages in between these limits, a receiver’s output state is notdefined and can randomly assume high or low. Removing the uncertainty of random output states, moderntransceiver designs include internal biasing circuits that put the receiver output into a defined state (typically high)in the absence of a valid input signal.

A loss of input signal can be caused by an pen circuit caused by a wire break or the unintentional disconnectionof a transceiver from the bus. The AM26C32 has an internal circuit that ensures functionality during an idle bus.

8.3.3 Active-High and Active-LowThe device can be configure using the G and G logic inputs to select receiver output. The high voltage or logic 1on the G pin, allows the device to operate on an active-high and having a low voltage or logic 0 on the G enablesactive low operation. These are simply a way to configure the logic to match that of the receiving or transmittingcontroller or microprocessor.

8.3.4 Operates from a Single 5-V SupplyBoth the logic and receivers operate from a single 5-V rail, making designs much more simple. The line driversand receivers can operate off the same rail as the host controller or a similar low voltage supply, thus simplifyingpower structure.


9



8.4 Device Functional Modes

8.4.1 Enable and DisableThe receivers implemented in these RS422 devices can be configured using the G and G pins to be enabled ordisabled. This allows users to ignore or filter out transmissions as desired.

Table 1. Function Table (Each Receiver)DIFFERENTIA

L INPUT ENABLES OUTPUT

A/B G G Y

VID ≥ VIT+H X HX L H

VIT < VID <VIT+

H X ?X L ?

VID ≤ VIT-H X LX L L

X L H Z


DIND

AM26C31

(One Driver)

D

RT

AM26C32

(One Receiver)

ROUT

10



9 Application and Implementation

NOTEInformation in the following applications sections is not part of the TI componentspecification, and TI does not warrant its accuracy or completeness. TI’s customers areresponsible for determining suitability of components for their purposes. Customers shouldvalidate and test their design implementation to confirm system functionality.

9.1 Application InformationWhen designing a system that uses drivers, receivers, and transceivers that comply with RS-422 or RS-485,proper cable termination is essential for highly reliable applications with reduced reflections in the transmissionline. Because RS-422 allows only one driver on the bus, if termination is used, it is placed only at the end of thecable near the last receiver. In general, RS-485 requires termination at both ends of the cable. Factors toconsider when determining the type of termination usually are performance requirements of the application andthe ever-present factor, cost. The different types of termination techniques discussed are unterminated lines,parallel termination, AC termination, and multipoint termination. Laboratory waveforms for each terminationtechnique (except multipoint termination) illustrate the usefulness and robustness of RS-422 (and, indirectly, RS-485). Similar results can be obtained if 485-compliant devices and termination techniques are used. Forlaboratory experiments, 100 feet of 100-Ω, 24-AWG, twisted-pair cable (Bertek) was used. A single driver andreceiver, TI AM26C31C and AM26C32C, respectively, were tested at room temperature with a 5-V supplyvoltage. Two plots per termination technique are shown. In each plot, the top waveform is the driver input and thebottom waveform is the receiver output. To show voltage waveforms related to transmission-line reflections, thefirst plot shows output waveforms from the driver at the start of the cable; the second plot shows input waveformsto the receiver at the far end of the cable.

9.2 Typical Application

Figure 4. Differential Terminated Configuration

9.2.1 Design RequirementsResistor and capacitor (if used) termination values are shown for each laboratory experiment, but vary fromsystem to system. For example, the termination resistor, RT, must be within 20% of the characteristic impedance,Zo , of the cable and can vary from about 80 Ω to 120 Ω.

9.2.2 Detailed Design ProcedureFigure 4 shows a configuration with no termination. Although reflections are present at the receiver inputs at adata signaling rate of 200 kbps with no termination, the RS-422-compliant receiver reads only the inputdifferential voltage and produces a clean signal at the output.


±3

±2

±1

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3

4

5

0 0.1 0.2 0.3 0.4 0.5

Vol

tage

(V

)

Time (�s)

Y A/B

C001

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Typical Application (continued)9.2.3 Application Curve

Figure 5. Differential 120-Ω Terminated Output Waveforms (Cat 5E Cable)


AM26C32

1

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VCC

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4A

4Y

G

3Y

3A

3B

0.1µF

VDD

Termination Resistor

Reduce logic signal trace

when possible

12

AM26C32JAJSGF8L –DECEMBER 1990–REVISED OCTOBER 2018 www.tij.co.jp


10 Power Supply RecommendationsPlace 0.1-μF bypass capacitors close to the power-supply pins to reduce errors coupling in from noisy or highimpedance power supplies.

11 Layout

11.1 Layout GuidelinesFor best operational performance of the device, use good PCB layout practices, including:• Noise can propagate into analog circuitry through the power pins of the circuit as a whole, as well as the

operational amplifier. Bypass capacitors are used to reduce the coupled noise by providing low impedancepower sources local to the analog circuitry.– Connect low-ESR, 0.1-μF ceramic bypass capacitors between each supply pin and ground, placed as

close to the device as possible. A single bypass capacitor from V+ to ground is applicable for singlesupply applications.

• Separate grounding for analog and digital portions of circuitry is one of the simplest and most-effectivemethods of noise suppression. One or more layers on multilayer PCBs are usually devoted to ground planes.A ground plane helps distribute heat and reduces EMI noise pickup. Make sure to physically separate digitaland analog grounds, paying attention to the flow of the ground current.

• To reduce parasitic coupling, run the input traces as far away from the supply or output traces as possible. Ifit is not possible to keep them separate, it is much better to cross the sensitive trace perpendicular asopposed to in parallel with the noisy trace.

• Place the external components as close to the device as possible. Keeping RF and RG close to the invertinginput minimizes parasitic capacitance.

• Keep the length of input traces as short as possible. Always remember that the input traces are the mostsensitive part of the circuit.

• Consider a driven, low-impedance guard ring around the critical traces. A guard ring can significantly reduceleakage currents from nearby traces that are at different potentials.

11.2 Layout Example

Figure 6. Trace Layout on PCB and Recommendations

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13

AM26C32www.tij.co.jp JAJSGF8L –DECEMBER 1990–REVISED OCTOBER 2018


12 デデババイイススおおよよびびドドキキュュメメンントトののササポポーートト

12.1 ドドキキュュメメンントトのの更更新新通通知知をを受受けけ取取るる方方法法ドキュメントの更新についての通知を受け取るには、ti.comのデバイス製品フォルダを開いてください。右上の隅にある「通知を受け取る」をクリックして登録すると、変更されたすべての製品情報に関するダイジェストを毎週受け取れます。変更の詳細については、修正されたドキュメントに含まれている改訂履歴をご覧ください。

12.2 ココミミュュニニテティィ・・リリソソーーススThe following links connect to TI community resources. Linked contents are provided "AS IS" by the respectivecontributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms ofUse.

TI E2E™オオンンラライインン・・ココミミュュニニテティィ TIののE2E（（Engineer-to-Engineer））ココミミュュニニテティィ。。エンジニア間の共同作業を促進するために開設されたものです。e2e.ti.comでは、他のエンジニアに質問し、知識を共有し、アイディアを検討して、問題解決に役立てることができます。

設設計計ササポポーートト TIのの設設計計ササポポーートト役に立つE2Eフォーラムや、設計サポート・ツールをすばやく見つけることができます。技術サポート用の連絡先情報も参照できます。

12.3 商商標標E2E is a trademark of Texas Instruments.All other trademarks are the property of their respective owners.

12.4 静静電電気気放放電電にに関関すするる注注意意事事項項これらのデバイスは、限定的なESD（静電破壊）保護機能を内蔵しています。保存時または取り扱い時は、MOSゲートに対する静電破壊を防止するために、リード線同士をショートさせておくか、デバイスを導電フォームに入れる必要があります。

12.5 GlossarySLYZ022 — TI Glossary.

This glossary lists and explains terms, acronyms, and definitions.

13 メメカカニニカカルル、、パパッッケケーージジ、、おおよよびび注注文文情情報報以降のページには、メカニカル、パッケージ、および注文に関する情報が記載されています。この情報は、そのデバイスについて利用可能な最新のデータです。このデータは予告なく変更されることがあり、ドキュメントが改訂される場合もあります。本データシートのブラウザ版を使用されている場合は、画面左側の説明をご覧ください。

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重重要要ななおお知知ららせせとと免免責責事事項項

TI は、技術データと信頼性データ（データシートを含みます）、設計リソース（リファレンス・デザインを含みます）、アプリケーションや設計に関する各種アドバイス、Web ツール、安全性情報、その他のリソースを、欠陥が存在する可能性のある「現状のまま」提供しており、商品性および特定目的に対する適合性の黙示保証、第三者の知的財産権の非侵害保証を含むいかなる保証も、明示的または黙示的にかかわらず拒否します。

これらのリソースは、TI 製品を使用する設計の経験を積んだ開発者への提供を意図したものです。(1) お客様のアプリケーションに適した TI 製品の選定、(2) お客様のアプリケーションの設計、検証、試験、(3) お客様のアプリケーションが適用される各種規格や、その他のあらゆる安全性、セキュリティ、またはその他の要件を満たしていることを確実にする責任を、お客様のみが単独で負うものとします。上記の各種リソースは、予告なく変更される可能性があります。これらのリソースは、リソースで説明されている TI 製品を使用するアプリケーションの開発の目的でのみ、TI はその使用をお客様に許諾します。これらのリソースに関して、他の目的で複製することや掲載することは禁止されています。TI や第三者の知的財産権のライセンスが付与されている訳ではありません。お客様は、これらのリソースを自身で使用した結果発生するあらゆる申し立て、損害、費用、損失、責任について、TI およびその代理人を完全に補償するものとし、TI は一切の責任を拒否します。TI の製品は、TI の販売条件（www.tij.co.jp/ja-jp/legal/termsofsale.html）、または ti.com やかかる TI 製品の関連資料などのいずれかを通じて提供する適用可能な条項の下で提供されています。TI がこれらのリソースを提供することは、適用されるTI の保証または他の保証の放棄の拡大や変更を意味するものではありません。IMPORTANT NOTICE

Copyright © 2018, Texas Instruments Incorporated日本語版日本テキサス・インスツルメンツ株式会社

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PACKAGE OPTION ADDENDUM

www.ti.com 9-Mar-2021

Addendum-Page 1

PACKAGING INFORMATION

Orderable Device Status(1)

Package Type PackageDrawing

Pins PackageQty

Eco Plan(2)

Lead finish/Ball material

(6)

MSL Peak Temp(3)

Op Temp (°C) Device Marking(4/5)

Samples

5962-9164001Q2A ACTIVE LCCC FK 20 1 Non-RoHS& Green

SNPB N / A for Pkg Type -55 to 125 5962-9164001Q2AAM26C32MFKB

5962-9164001QEA ACTIVE CDIP J 16 1 Non-RoHS& Green

SNPB N / A for Pkg Type -55 to 125 5962-9164001QEAAM26C32MJB

5962-9164001QFA ACTIVE CFP W 16 1 Non-RoHS& Green

SNPB N / A for Pkg Type -55 to 125 5962-9164001QFAAM26C32MWB

AM26C32CD ACTIVE SOIC D 16 40 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 AM26C32C

AM26C32CDBR ACTIVE SSOP DB 16 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM 26C32

AM26C32CDE4 ACTIVE SOIC D 16 40 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 AM26C32C

AM26C32CDR ACTIVE SOIC D 16 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 AM26C32C

AM26C32CDRE4 ACTIVE SOIC D 16 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 AM26C32C

AM26C32CN ACTIVE PDIP N 16 25 RoHS & Green NIPDAU N / A for Pkg Type 0 to 70 AM26C32CN

AM26C32CNE4 ACTIVE PDIP N 16 25 RoHS & Green NIPDAU N / A for Pkg Type 0 to 70 AM26C32CN

AM26C32CNSR ACTIVE SO NS 16 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 26C32

AM26C32CNSRG4 ACTIVE SO NS 16 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 26C32

AM26C32ID ACTIVE SOIC D 16 40 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 AM26C32I

AM26C32IDE4 ACTIVE SOIC D 16 40 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 AM26C32I

AM26C32IDG4 ACTIVE SOIC D 16 40 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 AM26C32I

AM26C32IDR ACTIVE SOIC D 16 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 AM26C32I

AM26C32IDRE4 ACTIVE SOIC D 16 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 AM26C32I

http://www.ti.com/product/AM26C32M?CMP=conv-poasamples#samplebuyhttp://www.ti.com/product/AM26C32M?CMP=conv-poasamples#samplebuyhttp://www.ti.com/product/AM26C32M?CMP=conv-poasamples#samplebuyhttp://www.ti.com/product/AM26C32?CMP=conv-poasamples#samplebuyhttp://www.ti.com/product/AM26C32C?CMP=conv-poasamples#samplebuyhttp://www.ti.com/product/AM26C32?CMP=conv-poasamples#samplebuyhttp://www.ti.com/product/AM26C32?CMP=conv-poasamples#samplebuyhttp://www.ti.com/product/AM26C32?CMP=conv-poasamples#samplebuyhttp://www.ti.com/product/AM26C32?CMP=conv-poasamples#samplebuyhttp://www.ti.com/product/AM26C32?CMP=conv-poasamples#samplebuyhttp://www.ti.com/product/AM26C32?CMP=conv-poasamples#samplebuyhttp://www.ti.com/product/AM26C32?CMP=conv-poasamples#samplebuyhttp://www.ti.com/product/AM26C32?CMP=conv-poasamples#samplebuyhttp://www.ti.com/product/AM26C32?CMP=conv-poasamples#samplebuyhttp://www.ti.com/product/AM26C32?CMP=conv-poasamples#samplebuyhttp://www.ti.com/product/AM26C32?CMP=conv-poasamples#samplebuyhttp://www.ti.com/product/AM26C32?CMP=conv-poasamples#samplebuy



Addendum-Page 2

Orderable Device Status(1)

Package Type PackageDrawing

Pins PackageQty

Eco Plan(2)

Lead finish/Ball material

(6)

MSL Peak Temp(3)

Op Temp (°C) Device Marking(4/5)

Samples

AM26C32IDRG4 ACTIVE SOIC D 16 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 AM26C32I

AM26C32IN ACTIVE PDIP N 16 25 RoHS & Green NIPDAU N / A for Pkg Type -40 to 85 AM26C32IN

AM26C32INSR ACTIVE SO NS 16 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 26C32I

AM26C32IPW ACTIVE TSSOP PW 16 90 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 26C32I

AM26C32IPWG4 ACTIVE TSSOP PW 16 90 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 26C32I

AM26C32IPWR ACTIVE TSSOP PW 16 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 26C32I

AM26C32IPWRG4 ACTIVE TSSOP PW 16 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 26C32I

AM26C32MFKB ACTIVE LCCC FK 20 1 Non-RoHS& Green

SNPB N / A for Pkg Type -55 to 125 5962-9164001Q2AAM26C32MFKB

AM26C32MJB ACTIVE CDIP J 16 1 Non-RoHS& Green

SNPB N / A for Pkg Type -55 to 125 5962-9164001QEAAM26C32MJB

AM26C32MWB ACTIVE CFP W 16 1 Non-RoHS& Green

SNPB N / A for Pkg Type -55 to 125 5962-9164001QFAAM26C32MWB

AM26C32QD ACTIVE SOIC D 16 40 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 AM26C32Q

AM26C32QDG4 ACTIVE SOIC D 16 40 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 26C32Q

AM26C32QDR ACTIVE SOIC D 16 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 AM26C32Q

(1) The marketing status values are defined as follows:ACTIVE: Product device recommended for new designs.LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.PREVIEW: Device has been announced but is not in production. Samples may or may not be available.OBSOLETE: TI has discontinued the production of the device.

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Addendum-Page 3

(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substancedo not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI mayreference these types of products as "Pb-Free".RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device PackageType

PackageDrawing

Pins SPQ ReelDiameter

(mm)

ReelWidth

W1 (mm)

A0(mm)

B0(mm)

K0(mm)

P1(mm)

W(mm)

Pin1Quadrant

AM26C32CDR SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1

AM26C32CNSR SO NS 16 2000 330.0 16.4 8.2 10.5 2.5 12.0 16.0 Q1

AM26C32IDR SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1

AM26C32INSR SO NS 16 2000 330.0 16.4 8.2 10.5 2.5 12.0 16.0 Q1

AM26C32IPWR TSSOP PW 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1

AM26C32QDR SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1

PACKAGE MATERIALS INFORMATION

www.ti.com 17-Dec-2020

Pack Materials-Page 1

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)

AM26C32CDR SOIC D 16 2500 333.2 345.9 28.6

AM26C32CNSR SO NS 16 2000 853.0 449.0 35.0

AM26C32IDR SOIC D 16 2500 333.2 345.9 28.6

AM26C32INSR SO NS 16 2000 367.0 367.0 38.0

AM26C32IPWR TSSOP PW 16 2000 367.0 367.0 35.0

AM26C32QDR SOIC D 16 2500 350.0 350.0 43.0

PACKAGE MATERIALS INFORMATION

www.ti.com 17-Dec-2020

Pack Materials-Page 2

www.ti.com

PACKAGE OUTLINE

C

14X 0.65

2X4.55

16X 0.300.19

TYP6.66.2

1.2 MAX

0.150.05

0.25GAGE PLANE

-80

BNOTE 4

4.54.3

A

NOTE 3

5.14.9

0.750.50

(0.15) TYP

TSSOP - 1.2 mm max heightPW0016ASMALL OUTLINE PACKAGE

4220204/A 02/2017

1

89

16

0.1 C A B

PIN 1 INDEX AREA

SEE DETAIL A

0.1 C

NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.5. Reference JEDEC registration MO-153.

SEATINGPLANE

A 20DETAIL ATYPICAL

SCALE 2.500

www.ti.com

EXAMPLE BOARD LAYOUT

0.05 MAXALL AROUND

0.05 MINALL AROUND

16X (1.5)

16X (0.45)

14X (0.65)

(5.8)

(R0.05) TYP


4220204/A 02/2017

NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

LAND PATTERN EXAMPLEEXPOSED METAL SHOWN

SCALE: 10X

SYMM

SYMM

1

8 9

16

15.000

METALSOLDER MASKOPENINGMETAL UNDERSOLDER MASK

SOLDER MASKOPENING

EXPOSED METALEXPOSED METAL

SOLDER MASK DETAILS

NON-SOLDER MASKDEFINED

(PREFERRED)

SOLDER MASKDEFINED

www.ti.com

EXAMPLE STENCIL DESIGN

16X (1.5)

16X (0.45)

14X (0.65)

(5.8)

(R0.05) TYP


4220204/A 02/2017

NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design.

SOLDER PASTE EXAMPLEBASED ON 0.125 mm THICK STENCIL

SCALE: 10X

SYMM

SYMM

1

8 9

16

MECHANICAL DATA

MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE

4040065 /E 12/01

28 PINS SHOWN

Gage Plane

8,207,40

0,550,95

0,25

38

12,90

12,30

28

10,50

24

8,50

Seating Plane

9,907,90

30

10,50

9,90

0,38

5,605,00

15

0,22

14

A

28

1

2016

6,506,50

14

0,05 MIN

5,905,90

DIM

A MAX

A MIN

PINS **

2,00 MAX

6,90

7,50

0,65 M0,15

0°–�8°

0,10

0,090,25

NOTES: A. All linear dimensions are in millimeters.B. This drawing is subject to change without notice.C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.D. Falls within JEDEC MO-150

重要なお知らせと免責事項TI は、技術データと信頼性データ (データシートを含みます)、設計リソース (リファレンス・デザインを含みます)、アプリケーションや設計に関する各種アドバイス、Web ツール、安全性情報、その他のリソースを、欠陥が存在する可能性のある「現状のまま」提供しており、商品性および特定目的に対する適合性の黙示保証、第三者の知的財産権の非侵害保証を含むいかなる保証も、明示的または黙示的にかかわらず拒否します。これらのリソースは、TI 製品を使用する設計の経験を積んだ開発者への提供を意図したものです。(1) お客様のアプリケーションに適したTI 製品の選定、(2) お客様のアプリケーションの設計、検証、試験、(3) お客様のアプリケーションが適用される各種規格や、その他のあらゆる安全性、セキュリティ、またはその他の要件を満たしていることを確実にする責任を、お客様のみが単独で負うものとします。上記の各種リソースは、予告なく変更される可能性があります。これらのリソースは、リソースで説明されている TI 製品を使用するアプリケーションの開発の目的でのみ、TI はその使用をお客様に許諾します。これらのリソースに関して、他の目的で複製することや掲載することは禁止されています。TI や第三者の知的財産権のライセンスが付与されている訳ではありません。お客様は、これらのリソースを自身で使用した結果発生するあらゆる申し立て、損害、費用、損失、責任について、TI およびその代理人を完全に補償するものとし、TI は一切の責任を拒否します。TI の製品は、TI の販売約款 (https://www.tij.co.jp/ja-jp/legal/terms-of-sale.html)、または ti.com やかかる TI 製品の関連資料などのいずれかを通じて提供する適用可能な条項の下で提供されています。TI がこれらのリソースを提供することは、適用される TI の保証または他の保証の放棄の拡大や変更を意味するものではありません。IMPORTANT NOTICE

日本語版日本テキサス・インスツルメンツ合同会社Copyright © 2021, Texas Instruments Incorporated

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1 特長2 アプリケーション3 概要目次4 改訂履歴5 Pin Configuration and Functions6 Specifications6.1 Absolute Maximum Ratings6.2 ESD Ratings6.3 Recommended Operating Conditions6.4 Thermal Information6.5 Electrical Characteristics6.6 Switching Characteristics6.7 Typical Characteristics

7 Parameter Measurement Information8 Detailed Description8.1 Overview8.2 Functional Block Diagram8.3 Feature Description8.3.1 ±7-V Common-Mode Range With ±200-mV Sensitivity8.3.2 Input Fail-Safe Circuitry8.3.3 Active-High and Active-Low8.3.4 Operates from a Single 5-V Supply

8.4 Device Functional Modes8.4.1 Enable and Disable

9 Application and Implementation9.1 Application Information9.2 Typical Application9.2.1 Design Requirements9.2.2 Detailed Design Procedure9.2.3 Application Curve

10 Power Supply Recommendations11 Layout11.1 Layout Guidelines11.2 Layout Example

12 デバイスおよびドキュメントのサポート12.1 ドキュメントの更新通知を受け取る方法12.2 コミュニティ・リソース12.3 商標12.4 静電気放電に関する注意事項12.5 Glossary

13 メカニカル、パッケージ、および注文情報