amkor’s next generation of packaging solutions … … confidential i sep-15 1 amkor’s next...

21
Amkor Confidential I Sep-15 1 Amkor’s Next Generation of Packaging Solutions … the future is now!

Upload: hoangkien

Post on 21-Mar-2018

217 views

Category:

Documents


3 download

TRANSCRIPT

Amkor Confidential I Sep-15 1

Amkor’s Next Generation of Packaging Solutions … the future is now!

Amkor Confidential I Sep-15 2

Agenda

Strategic Technology Roadmap

Differentiating SLIM & SWIFT

Development Overview

Conclusions

簡報者
簡報註解

Amkor Confidential I Sep-15 3 3 Amkor Confidential I Sep-15

Semiconductor Packaging Evolution

Reduce cost Improve performance

Improve board space floor plan

Higher bandwidth Lower power

Desire to integrate multiple chips on a single package platform

Reduce floor space of package platform (thin & small)

Avoid cost of expensive silicon nodes below 14nm

Keep package size pin out the same while reducing chip size

Amkor Confidential I Sep-15 4 4 Amkor Confidential I Sep-15

Semiconductor Packaging Interconnect Evolution

100µm 10µm 1µm 10nm

PCB Design Rule Wafer Design Rule

Organic Substrate

GAP!

BEOL

~8 < 1µm

Highest Cost

Lowest Cost

Bump

Substrate

OSAT

Foundry

Evolving

Amkor Confidential I Sep-15 5 5 Amkor Confidential I Sep-15

Amkor’s Package Technology Integration Roadmap

Thin Film on Subst

Adv Subst Process

High Perform Products

(dual substrate)

FCBGA

Si Interposer

2um

10um

SWIFT™ (Single die / Multi die)

Mobile Products

Substrate Level

Wafer Level

Foundry Level

fcCSP

(Bump Line RDL)

(BEOL RDL)

HVM LVM Proto Develop

SLIM™ SLIM™

(On Board RDL)

WLCSP

• SWIFT: Silicon Wafer Integrated Fan-out Tech • SLIM : Silicon-less Integrated Module

5um

rtMLF

Amkor Confidential I Sep-15 6 6 Amkor Confidential I Sep-15

TSV Transition To SLIM / SWIFT Efficient way to connect die to die and die to board at lower cost

Typical 2.5D cross section SLIM package for the same TV

Amkor Confidential I Sep-15 7 7 Amkor Confidential I Sep-15

Flip Chip CSP and SiP Migration to SWIFT Mainly to reduce form factor and profile

SWIFT: Passive integration at wafer level and multi die packaging

Amkor Confidential I Sep-15 8 8 Amkor Confidential I Sep-15

SLIM & SWIFT Package Definition

EMC Solder ball

Solder

ball

UF

Top die 2 Top die 1

RDL

EMC Solder

ball

UF

Top die 2 Top die 1

PBO

Solder ball

Passivation3

Passivation1

Passivation2

2nd

RDL 1st RDL

3rd

RDL

SLIMTM SWIFTTM

Silicon-Less Integrated Module Silicon Wafer Integrated Fan-out Technology

Top die

U-bump solder joint Fab. BEOL layer

RDL layer

BGA

Top die

U-bump solder joint

RDL layer

BGA

Amkor Confidential I Sep-15 9 9 Amkor Confidential I Sep-15

SLIM / SWIFT Package Options Wafer Level Package Format Flip Chip Package Format

Thinner package profile TSV-less interposer size = package size

Thicker than WLCSP type TSV-less interposer size < package size

SLIM Size e.g. 11mm

15mm 15mm

Amkor Confidential I Sep-15 10 10 Amkor Confidential I Sep-15

SLIM / SWIFT Package Variants

SLIM / SWIFT on Substrate – CSP 2D or 3D POP Compatible

W-SLIM / SWIFT, FIPOP/3D

W-SLIM / SWIFT, TMV/3D

SLIM / SWIFT on Substrate – 2D

Wafer Level Flip Chip Package

W-SLIM / SWIFT, 2D

Amkor Confidential I Sep-15 11 11 Amkor Confidential I Sep-15

Amkor’s Advanced WLP Positioning

Multi dies, SoC partition, 3D compatible < 2um L/S by foundry interposer BEOL High performance (CPU/GPU), mobile AP, BB

Single/Multi die, SoC partition, 3D 2~10um L/S interconnect by bumping RDL Mobile AP / BB, mid-range CPU/GPU

Single die RDL > 10um L/S RF, WLAN, Power etc.

W-SLIM

SWIFT

WLCSP

Performance

Products : RF and Analog to Advanced Processors

Amkor Confidential I Sep-15 12 12 Amkor Confidential I Sep-15

Amkor’s Advanced Flip Chip Product Positioning Multi die, SoC partition, HBM, 3D compatible RDL ≤ 2um L/S by foundry BEOL interposer Ultra Thin Lower cost ; SLIM ˂ 2.1D / 2.5D

Multi die, SoC partition, HBM, 3D compatible RDL ≤ 2um L/S by foundry BEOL interp. + TSV

HBM integration RDL 2~10um L/S by substrate

Single or multi die RDL > 10um L/S by subtrate 3D compatible

S-SLIM

Advanced fcCSP / FCBGA

Performance

2.5D

2.1D

Products : AP, BB, CPU, GPU and Networking

Amkor Confidential I Sep-15 13 13 Amkor Confidential I Sep-15

Process Differentiation

Leverage high yield process

Fab. BEOL process RDL fabrication first Chip attach and mold last Flip chip attach

High accuracy die placement

Self alignment by solder joint High UPH chip placement No die shift / rotation issue

Flexibility

Different package form possible Die thickness / Mold interface etc.

Die face down

Amkor Confidential I Sep-15 14 14 Amkor Confidential I Sep-15

1. RDL wafer

Simplified Process Flow

EMC Solder

ball UF

Top die 1

PBO Solder

ball

Passivation3

Passivation1 Passivation2 2nd

RDL 1st RDL

3rd RDL

Cycle time

Cycle time

2. CoW

3. BGA or C4 + Substrate

1. Re-con.

2. RDL 3. BGA

Amkor – Die Last Competitors – Die First

Amkor Confidential I Sep-15 15 15 Amkor Confidential I Sep-15

Key Process Capability Wafer processing (Bumping and MEOL) at K4 and Assembly at K1

Bumping

• Fine pitch u-bump • NiAu pad • Multi-layer RDL • Low temp. cure

PSPI • Tall Cu post

MEOL

• Carrier bond-debond

• Si grinding • Si etch • Oxide etch

Assembly

• CoW chip attach • Wafer underfill

and mold • CSP or FCBGA w/

lid

Amkor Confidential I Sep-15 16 16 Amkor Confidential I Sep-15

Key Module Development Summary Molded 12inch CoW wafer processing - Available

Fine L/S multi RDL - 5/5um available - 3L RDL demonstrated

Backside pattern reveal and carrier attach - Available

Fine pitch u-bump interconnection - CoW chip attach with mass reflow - 40/45um available - 30um demonstrated

Tall Cu pillar for memory interface - 180um tall Cu demonstrated

Amkor Confidential I Sep-15 17 17 Amkor Confidential I Sep-15

Package Level Reliability Customer TV data

Test item Pre-con Condition Result (O/S daisy chain test)

TC B L3/260 55C/125C – 1000cycle

Pass

HAST L3/260 130C/85%RH – 96hrs

Pass

HTS NA 150’C – 1000 hours

pass

Amkor Confidential I Sep-15 18 18 Amkor Confidential I Sep-15

Board Level Reliability

Leg TC (- 40 ~ 125℃, 1CPH)

Drop (1500G, 0.5 ms duration)

Board UF SS 1st fail Mean life 63.2% life SS 1st fail Mean life 63.2% life

w/o UF 30 199 285 303 30 57 288 320

UF 30 N/A N/A N/A 30 N/A N/A N/A

TV cross section: 10mm x 10mm package body SLIM

40um pitch u-bump 529 I/O, 0.25mm ball on 0.4mm pitch

• JESD22-B111 compliant board • 15 units per board • 8L PCB, 1mm thickness

Amkor Confidential I Sep-15 19 19 Amkor Confidential I Sep-15

Key Milestones

Q1 2015 Q2 2015 Q3 2015 Q4 2015 Q1 2016 Q2 2016 Q3 2016 Q4 2016

Key Gates

1. Feasibility

2. Validation

3. Intern Qual

4. Corner Eval

5. Cust. Qual

6. Production

Complete

SLIM

SWIFT

Amkor Confidential I Sep-15 20 20 Amkor Confidential I Sep-15

Conclusions SLIM / SWIFT bridges the gap between TSV and traditional substrate

and wafer fan-out packaging

SLIM / SWIFT technology is designed to provide increased I/O and circuit density within a reduced footprint and profile for single & and multi-die applications

Finally, SLIM / SWIFT technology enables the creation of advanced 3D structures that address the need for increased IC integration in emerging mobile and networking applications

Amkor Confidential I Sep-15 21

Thank You!