79826979 fujitsu siemens esprimo v6535.pdf
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A A
B B
C C
D D
E E
44
33
22
11
Title
Siz
eD
ocum
ent
Num
ber
Rev
Date
:S
heet
of
Wis
tro
n C
orp
ora
tio
n21F
, 88,
Sec.1
, H
sin
Tai W
u R
d.,
Hsic
hih
,T
aip
ei H
sie
n 2
21,
Taiw
an,
R.O
.C.
D45/D
46
PD
BL
OC
K D
IAG
RA
M
A3
14
7F
riday,
Marc
h 1
4,
2008
Title
Siz
eD
ocum
ent
Num
ber
Rev
Date
:S
heet
of
Wis
tro
n C
orp
ora
tio
n21F
, 88,
Sec.1
, H
sin
Tai W
u R
d.,
Hsic
hih
,T
aip
ei H
sie
n 2
21,
Taiw
an,
R.O
.C.
D45/D
46
PD
BL
OC
K D
IAG
RA
M
A3
14
7F
riday,
Marc
h 1
4,
2008
Title
Siz
eD
ocum
ent
Num
ber
Rev
Date
:S
heet
of
Wis
tro
n C
orp
ora
tio
n21F
, 88,
Sec.1
, H
sin
Tai W
u R
d.,
Hsic
hih
,T
aip
ei H
sie
n 2
21,
Taiw
an,
R.O
.C.
D45/D
46
PD
BL
OC
K D
IAG
RA
M
A3
14
7F
riday,
Marc
h 1
4,
2008
DCBATOUT
KBC
28
WPC773
Winbond
INT.
KB
Touch
Pad
27
27
SYSTEM DC/DC
X4 DMI
HOST BUS
DDR2 socket
CLK GEN.
667/800/1066MHz@1.05V
400MHz
3
4,
5
6,7
,8,9
,10,1
1
12,1
3
16,1
7,1
8,1
9
Cantiga
ICH9M
Mobile CPU
D4
5/D
46
Blo
ck
Dia
gra
m
Codec
ALC269
Headphone Out
MIC In
Penryn
INPUTS
SYSTEM DC/DC
TPS51125 5V_S5(5A)3
4
OUTPUTS
RTM875T-606-VD-GRT
RT9026
DDR_VREF_S0
(1.5A)
6 P
CIe
port
s
a/b/g/n
SATA
HD
D21
CD
RO
M
LPC BUS
3D3V_S5(5A)
Mini Card
DDR2 socket
12,1
3
AG
TL
+ C
PU
I/F
LV
DS
, C
RT
I/F
INT
EG
RA
TE
D G
RA
HP
ICS
DD
R M
emory
I/F
Hig
h D
efin
itio
n A
udio
AC
PI
1.1
PC
I/P
CI
BR
IDG
E
21
25
C-Link0
DEBUG
CONN.
LPC
27
1D8V_S3(10A)36
DCBATOUT
1D05V_M(11A)
INPUTS
OUTPUTS
Project code: 91.4J001.001--D45
91.4K001.001--D46
PCB P/N : 07248
REVISION : SA
4 S
AT
A
LP
C I
/F
TOP
VCC S S
GND
BOTTOMPCB STACKUP
Kedron
MDC Card
AZALIA
MODEM
29 INT.SPKR
RJ11
71.I
CH
9M
.00U
71.C
NT
IG.0
0U
TPS51124
SATA
G7921 20
800/667MHz
DDR_VREF_S3
G9131
3D3V_S0
2D5V_S0
(300mA)
TRL8111C
24
23
LAN
24
TXFM
RJ45
1D8V_S3
35
38
33
VCC_CORE_S0
0~1.3V 47A
OUTPUTS
CPU DC/DC
INPUTS
DCBATOUT
CHARGER
OUTPUTS
INPUTS
CHG_PWR
DCBATOUT
UP+5V
5V 100mA
18V 4.0A
BQ24745
ISL6266A
Ser
ial
Per
iph
eral
I/F
22
29
29
USB
Blu
eT
oo
th
US
B3 P
ort
CA
ME
RA
4M byte
BIOS
28
PCI-E
MS/MS Pro/
MMC/SD
26
4 in 1
SPI I/F
eS
AT
A
/US
B22
SATA
37
NB DC/DC OUTPUTS
INPUTS
DCBATOUTISL6263A
35
USB0
GFX_CORE
35
APL5912
1D5V_S0
1D8V_S3
12 U
SB
800/667MHz
INT.MIC
PCI-E
Mini Card
25
UMTS(3G)
PCI-E /USB 2.0
PCI-E /USB 2.0
S-V
ideo
ATI
M82M
VRAMx4
256MB
41~
47
PCI-EG
LV
DS
WX
GA
/SX
GA
+
15"
LC
D1
4
RG
B C
RT
CR
T1
3
S-V
ideo 1
3
PCI-E/USB 2.0New card
25
25
G577
USB Cardreader 2
6JMICRO380
22
14
22
ICS9LPRS365YGLFT-GP
1394
-
A A
B B
C C
D D
E E
44
33
22
11
Title
Siz
eD
ocum
ent
Num
ber
Rev
Date
:S
heet
of
Wis
tro
n C
orp
ora
tio
n21F
, 88,
Sec.1
, H
sin
Tai W
u R
d.,
Hsic
hih
,T
aip
ei H
sie
n 2
21,
Taiw
an,
R.O
.C.
Refe
ren
ce
24
7F
riday,
Marc
h 1
4,
2008
D45/D
46
PD
UM
A
Title
Siz
eD
ocum
ent
Num
ber
Rev
Date
:S
heet
of
Wis
tro
n C
orp
ora
tio
n21F
, 88,
Sec.1
, H
sin
Tai W
u R
d.,
Hsic
hih
,T
aip
ei H
sie
n 2
21,
Taiw
an,
R.O
.C.
Refe
ren
ce
24
7F
riday,
Marc
h 1
4,
2008
D45/D
46
PD
UM
A
Title
Siz
eD
ocum
ent
Num
ber
Rev
Date
:S
heet
of
Wis
tro
n C
orp
ora
tio
n21F
, 88,
Sec.1
, H
sin
Tai W
u R
d.,
Hsic
hih
,T
aip
ei H
sie
n 2
21,
Taiw
an,
R.O
.C.
Refe
ren
ce
24
7F
riday,
Marc
h 1
4,
2008
D45/D
46
PD
UM
A
1 = TLS cipher suite with
confidentiality (default)
0 = Transport Layer Security (TLS) cipher
suite with no confidentiality
Cantiga chipset and ICH9M I/O controller
Hub strapping configuration
page 218
Intel Management
engine Crypto strap
CFG6
Reserved
This signal should not be pulled high.
GPIO49
SPI_MOSI
GPIO33/
HDA_DOCK
_EN#
SATALED#
SPKR
TP3
CFG9
00 = Reserve
(Default)
CFG16
0 = LFP Disabled (Default)
Local Flat Panel
(LFP) Present
CFG19
CFG20
SDVO_CTRLDATA
11 = Disabled (default)
1 = Dynamic ODT Enabled
0 = Dynamic ODT Disabled
1= LFP Card Present; PCIE disabled
L_DDC_DATA
FSB Dynamic ODT
DMI Lane Reversal
NOTE:
PCIE config2 bit2,
Rising Edge of PWROK.
GNT2#/
GPIO53
Sets bit0 of RPC.PC(Config Registers:Offset 224h)
Top-Block
Swap Override.
Rising Edge of PWROK.
GNT0#:
SPI_CS1#/
GPIO58
0 = Reverse Lanes,15->0,14->1 ect..
Boot BIOS Destination
Selection 0:1.
Rising Edge of PWROK.
ESI compatible mode is for server platforms only.
This signal should not be pulled low for desttop
and mobile.
HDA_SDOUT
HDA_SYNC
GNT3#/
GPIO55
Signal
Sampled low:Top-Block Swap mode(inverts A16 for
all cycles targeting FWH BIOS space).
Note: Software will not be able to clear the
Top-Swap bit until the system is rebooted
without GNT3# being pulled down.
This signal has a weak internal pull-up.
XOR Chain Entrance/
PCIE Port Config1 bit1,
Rising Edge of PWROK
1= Normal operation(Default):Lane
Numbered in order
Allows entrance to XOR Chain testing when TP3
pulled low.When TP3 not pulled low at rising edge
of PWROK,sets bit1 of RPC.PC(Config Registers:
offset 224h). This signal has weak internal pull-down
PCIE config1 bit0,
Rising Edge of PWROK.
GPIO20
Usage/When Sampled
ESI Strap (Server Only)
Rising Edge of PWROK
Comment
CFG[13:12]
0 = Only Digital Display Port
or PCIE is operational (Default)
1 =Digital display Port and PCIe are
operting simulataneously via the PEG port
0 =No SDVO Card Present (Default)
1 = SDVO Card Present
page 17
DMI Termination Voltage,
Rising Edge of PWROK.
The signal is required to be low for desktop
applications and required to be high for
mobile applications.
Signal has weak internal pull-up. Sets bit 27
of MPC.LR(Device 28:Function 0:Offset D8)
CFG[2:0]
CFG[4:3]
CFG8
CFG[15:14]
CFG[18:17]
CFG5
Pin Name
011 = FSB667
FSB Frequency
Select
0 = DMI x2
others = Reserved
Reserved
(Default)
1 = DMI x4
Strap Description
DMI x2 Select
iTPM Host
Interface
Configuration
Sets bit2 of RPC.PC2(Config Registers:Offset 0224h)
This signal has a weak internal pull-down.
GNT1#/
GPIO51
Integrated TPM Enable,
Rising Edge of CLPWROK
Sample low: the Integrated TPM will be disabled.
Sample high: the MCH TPM enable strap is sampled
low and the TPM Disable bit is clear, the
Integrated TPM will be enable.
Flash Descriptor
Security Override Strap
Rising Edge of PWROK
PCI Express Lane
Reversal. Rising Edge
of PWROK.
No Reboot.
Rising Edge of PWROK.
XOR Chain Entrance.
Rising Edge of PWROK.
This signal should not be pull low unless using
XOR Chain testing.
If sampled high, the system is strapped to the
"No Reboot" mode(ICH9 will disable the TCO Timer
system reboot feature). The status is readable
via the NO REBOOT bit.
ICH9M Functional Strap Definitions
Controllable via Boot BIOS Destination bit
(Config Registers:Offset 3410h:bit 11:10).
GNT0# is MSB, 01-SPI, 10-PCI, 11-LPC.
page 92
PCI Routing
Sampled low:the Flash Descriptor Security will be
overridden. If high,the security measures will be
in effect.This should only be enabled in manufacturing
environments using an external pull-up resister.
SDVO PresentMontevina Platform Design guide 22339 0.5
USB Table
00
AD22
TI7412
INT
REQ
G:CARDBUS
B:1394
F:Flash Media
G:SD Host
GNT
IDSEL
LANE2
MiniCard WLAN
PCIE Routing
010 = FSB800
000 = FSB1067
LANE3
NewCard WLAN
ICH9 EDS 642879 Rev.1.5
USB3
USB2
FT
Combo(ESATA/USB)
NC
Pair
4
BLUETOOTH
USB
USB4
50 2 31
Device
WEBCAM
6 7 8 9NEW1
MINICARD
ICH9M
BATTERY
KBC
Thermal
MXM
SMBC_G792
BAT_SCL
SMB_CLK
LAN
SMBC_ICH
CK505
DDR
CFG7
SMBus
ICH9 EDS 642879 Rev.1.5
ICH9M Integrated Pull-up
and Pull-down Resistors
SIGNAL
Resistor Type/Value
HDA_BIT_CLK
HDA_RST#
HDA_SDIN[3:0]
HDA_SDOUT
HDA_SYNC
GNT[3:0]#/GPIO[55,53,51]
GPIO[20]
LDA[3:0]#/FHW[3:0]#
LDRQ[0]
PME#
PWRBTN#
SATALED#
LAN_RXD[2:0]
LDRQ[1]/GPIO23
TP[3]
SPKR
GLAN_DOCK#
SPI_CS1#/GPIO58/CLGPIO6
USB[11:0][P,N]
CL_RST0#
SPI_MOSI
SPI_MISO
TACH_[3:0]
PULL-DOWN 20K
PULL-DOWN 20K
PULL-DOWN 15K
The pull-up or pull-down active when configured for native
GLAN_DOCK# functionality and determined by LAN controller
PULL-UP 20K
PULL-UP 20K
PULL-UP 20K
PULL-UP 20K
PULL-UP 20K
PULL-UP 20K
PULL-UP 20K
PULL-UP 15K
PULL-UP 20K
PULL-UP 20K
PULL-UP 20K
PULL-UP 20K
PULL-UP 20K
PULL-UP 20K
PULL-DOWN 20K
PULL-DOWN 20K
PULL-DOWN 20K
PULL-DOWN 20K
PULL-DOWN 20K
PULL-DOWN 20K
GPIO[49]
HDA_DOCK_EN#/GPIO33
CL_DATA[1:0]
CL_CLK[1:0]
DPRSLPVR/GPIO16
ENERGY_DETECT
PULL-DOWN 20K
PULL-UP 20K
PULL-UP 20K
PULL-UP 20K
PULL-UP 20K
0= The iTPM Host Interface is enabled(Note2)
1=The iTPM Host Interface is disalbed(default)
PCIE Graphics Lane
CFG10
PCIE Loopback enable
0 = Enable (Note 3)
1= Disabled (default)
XOR/ALL
1 = Reverse Lanes
DMI x4 mode[MCH -> ICH]:(3->0,2->1,1->2and0->3)
DMI x2 mode[MCH -> ICH]:(3->0,2->1)
0 = Normal operation(Default):
Lane Numbered in Order
Digital Display Port
(SDVO/DP/iHDMI)
Concurrent with PCIe
1. All strap signals are sampled with respect to the leading edge of
the (G)MCH Power OK (PWROK) signal.
2. iTPM can be disabled by a 'Soft-Strap' option in the
Flash-decriptor section of the Firmware. This 'Soft-Strap' is
activated only after enabling iTPM via CFG6.
Only one of the CFG10/CFG/12/CFG13 straps can be enabled at any time.
10 = XOR mode Enabled
01 = ALLZ mode Enabled (Note 3)
-
A A
B B
C C
D D
E E
44
33
22
11
3D
3V
_C
LK
GE
N_
S0
3D
3V
_48M
PW
R_
S0
3D
3V
_C
LK
PLL_
S0
PC
LK
CLK
5
PC
LK
CLK
2
PC
LK
CLK
4P
CLK
CLK
3
CP
U_
SE
L2_
R
PC
LK
CLK
3
CLK
_P
CIE
_S
AT
A_
1
CLK
_C
PU
_B
CLK
_1
CLK
_P
CIE
_M
INI_
12#
3D
3V
_C
LK
PLL_
S0
CLK
_M
CH
_3G
PLL_
1#
CLK
_M
CH
_3G
PLL_
1
DR
EF
SS
CLK
#_
1D
RE
FS
SC
LK
_1
CLK
48
DR
EF
CLK
_1
DR
EF
CLK
#_
1
PC
LK
CLK
1
CLK
_M
CH
_B
CLK
_1
CLK
_C
PU
_B
CLK
_1#
CLK
_M
CH
_B
CLK
_1#
PC
LK
CLK
5
PC
LK
CLK
4C
LK
_P
CIE
_IC
H_
1#
CLK
_P
CIE
_IC
H_
1
CLK
_C
PU
_X
DP
#_
RC
LK
_C
PU
_X
DP
_R
CLK
_P
CIE
_P
EG
_1
CLK
_P
CIE
_P
EG
_1#
CLK
_P
CIE
_M
INI_
12
PC
LK
CLK
0
CP
U_
SE
L2_
RG
EN
_X
TA
L_
OU
T_
R
GE
N_
XT
AL_
OU
T
3D
3V
_C
LK
GE
N_
S0
GE
N_
XT
AL_
IN
CLK
_P
CIE
_S
AT
A_
1#
3D
3V
_48M
PW
R_
S0
PC
LK
CLK
2
CLK
_P
CIE
_C
AR
D#_
R
CLK
_P
CIE
_N
EW
#_
RC
LK
_P
CIE
_N
EW
_R
CLK
_P
CIE
_LA
N#_
RC
LK
_P
CIE
_LA
N_
R
PC
LK
_F
WH
CLK
_IC
H14
CLK
48_
ICH
PC
LK
_IC
HP
CLK
_K
BC
DR
EF
SS
CLK
_1
DR
EF
SS
CLK
#_
1O
SC
_S
PR
EA
D
VG
A_
XIN
1
CLK
_P
CIE
_C
AR
D_
R
CLK
_P
CIE
_M
INI2
CLK
_P
CIE
_M
INI2
#
3D
3V
_S
0
3D
3V
_S
03D
3V
_S
0
3D
3V
_S
0
3D
3V
_S
0
CLK
_P
CIE
_P
EG
41
CLK
_P
CIE
_P
EG
#41
CP
U_
SE
L1
4,7
CP
U_
SE
L2
4,7
PM
_S
TP
CP
U#
17
CLK
48_
ICH
17
CLK
_C
PU
_B
CLK
4C
LK
_C
PU
_B
CLK
#4
CLK
_M
CH
_B
CLK
6C
LK
_M
CH
_B
CLK
#6
CLK
_P
CIE
_S
AT
A16
CLK
_P
CIE
_S
AT
A#
16
CLK
_P
CIE
_IC
H17
CLK
_P
CIE
_IC
H#
17
CLK
_P
CIE
_M
INI1
25
CLK
_P
CIE
_M
INI1
#25
CLK
_IC
H14
17
PM
_S
TP
PC
I#17
SM
BD
_IC
H12,1
9S
MB
C_
ICH
12,1
9
CLK
_P
WR
GD
17
PC
LK
_IC
H17
CP
U_
SE
L0
4,7
PC
LK
_F
WH
27
PC
LK
_K
BC
28
CLK
_M
CH
_3G
PLL
7C
LK
_M
CH
_3G
PLL#
7
CLK
_P
CIE
_M
INI2
#25
CLK
_P
CIE
_M
INI2
25
DR
EF
CLK
7D
RE
FC
LK
#7
CLK
_P
CIE
_N
EW
25
CLK
_P
CIE
_N
EW
#25
DR
EF
SS
CLK
#7
DR
EF
SS
CLK
7
CLK
_M
CH
_O
E#
7
CLK
_P
CIE
_LA
N23
CLK
_P
CIE
_LA
N#
23
OS
C_
SP
RE
AD
42
VG
A_
XIN
142
CLK
_P
CIE
_C
AR
D26
CLK
_P
CIE
_C
AR
D#
26
Title
Siz
eD
ocum
ent
Num
ber
Rev
Date
:S
heet
of
Wis
tro
n C
orp
ora
tio
n21F
, 88,
Sec.1
, H
sin
Tai W
u R
d.,
Hsic
hih
,T
aip
ei H
sie
n 2
21,
Taiw
an,
R.O
.C.
Clo
ck G
en
era
tor
34
7T
uesday,
Marc
h 1
8,
2008
D45/D
46
PD
UM
A
Title
Siz
eD
ocum
ent
Num
ber
Rev
Date
:S
heet
of
Wis
tro
n C
orp
ora
tio
n21F
, 88,
Sec.1
, H
sin
Tai W
u R
d.,
Hsic
hih
,T
aip
ei H
sie
n 2
21,
Taiw
an,
R.O
.C.
Clo
ck G
en
era
tor
34
7T
uesday,
Marc
h 1
8,
2008
D45/D
46
PD
UM
A
Title
Siz
eD
ocum
ent
Num
ber
Rev
Date
:S
heet
of
Wis
tro
n C
orp
ora
tio
n21F
, 88,
Sec.1
, H
sin
Tai W
u R
d.,
Hsic
hih
,T
aip
ei H
sie
n 2
21,
Taiw
an,
R.O
.C.
Clo
ck G
en
era
tor
34
7T
uesday,
Marc
h 1
8,
2008
D45/D
46
PD
UM
A
SEL1
FSB
SEL0
FSA
133M
100M
166M
800M
01
01X
667M
200M
01
CPU
SEL2
FSC
FSB
01
01 0
1
PIN NAME
DESCRIPTION
Byte 5, bit 7
0 = PCI0 enabled (default)
1= CR#_A enabled. Byte 5, bit 6 controls whether CR#_A controls SRC0 or SRC2 pair
Byte 5, bit 6
0 = CR#_A controls SRC0 pair (default),
1= CR#_A controls SRC2 pair
Byte 5, bit 5
0 = PCI1 enabled (default)
1= CR#_B enabled. Byte 5, bit 6 controls whether CR#_B controls SRC1 or SRC4 pair
Byte 5, bit 4
0 = CR#_B controls SRC1 pair (default)
1= CR#_B controls SRC4 pair
PCI1/CR#_B
0 = Overclocking of CPU and SRC Allowed
1 = Overclocking of CPU and SRC NOT allowed
PCI2/TME
0 = Pin17 as SRC-1, Pin18 as SRC-1#, Pin13 as DOT96, Pin14 as DOT96#
1 = Pin17 as 27MHz, Pin 18 as 27MHz_SS, Pin13 as SRC-0, Pin14 as SRC-0#
PCI4/27M_SEL
ICS9LPRS365YGLFT setting table
0 =SRC8/SRC8#
1 = ITP/ITP#
PCI_F5/ITP_EN
PCI3
PCI0/CR#_A
CL=20pF0.2pF
PIN NAME
DESCRIPTION
Byte 5, bit 3
0 = SRC3 enabled (default)
1= CR#_C enabled. Byte 5, bit 2 controls whether CR#_C controls SRC0 or SRC2 pair
Byte 5, bit 2
0 = CR#_C controls SRC0 pair (default),
1= CR#_C controls SRC2 pair
Byte 5, bit 1
0 = SRC3 enabled (default)
1= CR#_D enabled. Byte 5, bit 0 controls whether CR#_D controls SRC1 or SRC4 pair
Byte 5, bit 0
0 = CR#_D controls SRC1 pair (default)
1= CR#_D controls SRC4 pair
SRCC3/CR#_D
SRCC11/CR#_G
SRCT11/CR#_H
SRCT3/CR#_C
Byte 6, bit 7
0 = SRC7# enabled (default)
1= CR#_F controls SRC6
Byte 6, bit 6
0 = SRC7 enabled (default)
1= CR#_F controls SRC8
Byte 6, bit 4
0 = SRC11 enabled (default)
1= CR#_H controls SRC10
Byte 6, bit 5
0 = SRC11# enabled (default)
1= CR#_G controls SRC9
SRCC7/CR#_E
SRCT7/CR#_F
533M
1067M
266M
00
0
SB
SB
PD
PD
PD
12
R581
33R
2J-2
-GP
VG
A_
27M
R581
33R
2J-2
-GP
VG
A_
27M
12
R274
33R
2J-2
-GP
R274
33R
2J-2
-GP
1 234
RN
32
SR
N0J-6
-GP
RN
32
SR
N0J-6
-GP
1 2
C393
SC
4D
7U
10V
5Z
Y-3
GP
C393
SC
4D
7U
10V
5Z
Y-3
GP
1 2
EC
54 SC15P50V2JN-2-GP
EC
54 SC15P50V2JN-2-GP
1 2C723
SCD1U16V2ZY-2GP
C723
SCD1U16V2ZY-2GP
1 2
X4
X-1
4D
31818M
-35G
P
X4
X-1
4D
31818M
-35G
P
12
R582
0R
0603-P
AD
R582
0R
0603-P
AD
12
R267
0R
0402-P
AD
R267
0R
0402-P
AD
12
R289
10K
R2J-3
-GP
R289
10K
R2J-3
-GP
1 234
RN
33
SR
N0J-6
-GP
RN
33
SR
N0J-6
-GP
12
R283
475R
2F
-L1-G
PD
YR
283
475R
2F
-L1-G
PD
Y
1 2C724
SCD1U16V2ZY-2GP
C724
SCD1U16V2ZY-2GP
123 4
RN
44
SR
N0J-6
-GP
RN
44
SR
N0J-6
-GP
1 2
EC
52 SC15P50V2JN-2-GP
EC
52 SC15P50V2JN-2-GP
12
R287
10K
R2J-3
-GP
DY
R287
10K
R2J-3
-GP
DY
1 2C397
SCD1U16V2ZY-2GP
C397
SCD1U16V2ZY-2GP
12
C382
SC
27P
50V
2JN
-2-G
PC
382
SC
27P
50V
2JN
-2-G
P
TP
68
TP
68
1 2C719
SCD1U16V2ZY-2GP
C719
SCD1U16V2ZY-2GP
1 2C721
SC1U16V3ZY-GP
C721
SC1U16V3ZY-GP
12
R293
22R
2J-2
-GP
R293
22R
2J-2
-GP
12
R296
10K
R2J-3
-GP
DY
R296
10K
R2J-3
-GP
DY
1 234
RN
34
SR
N0J-6
-GP
RN
34
SR
N0J-6
-GP
123 4
RN
36
SR
N0J-6
-GP
VG
AR
N36
SR
N0J-6
-GP
VG
A
12
R268
10M
R2J-L
-GP
DY
R268
10M
R2J-L
-GP
DY
12
R298
33R
2J-2
-GP
R298
33R
2J-2
-GP
1 2C703
SCD1U16V2ZY-2GP
C703
SCD1U16V2ZY-2GP
1 2
C372
SC15P50V2JN-2-GP
DY
C372
SC15P50V2JN-2-GP
DY
123 4
RN
43
SR
N0J-6
-GP
RN
43
SR
N0J-6
-GP
12
R288
10K
R2J-3
-GP
UM
A
R288
10K
R2J-3
-GP
UM
A
1 234
RN
39
SR
N0J-6
-GP
UM
A
RN
39
SR
N0J-6
-GP
UM
A
1 2
EC
49 SC15P50V2JN-2-GP
EC
49 SC15P50V2JN-2-GP
12
R270
10K
R2J-3
-GP
DY
R270
10K
R2J-3
-GP
DY
1 2
C400
SC
4D
7U
10V
5Z
Y-3
GP
C400
SC
4D
7U
10V
5Z
Y-3
GP
12
R2790
R0603-P
AD
R2790
R0603-P
AD
12
R295
22R
2J-2
-GP
R295
22R
2J-2
-GP
1 2EC
110
SCD1U16V2ZY-2GP
DYE
C110
SCD1U16V2ZY-2GP
DY 12
R284
10K
R2J-3
-GP
DY
R284
10K
R2J-3
-GP
DY
123 4
RN
40
SR
N0J-6
-GP
UM
AR
N40
SR
N0J-6
-GP
UM
A
123 4
RN
41
SR
N0J-6
-GP
RN
41
SR
N0J-6
-GP
12
R291
22R
2J-2
-GP
R291
22R
2J-2
-GP
1 2
EC
51 SC15P50V2JN-2-GP
EC
51 SC15P50V2JN-2-GP
1 2
EC
53 SC15P50V2JN-2-GP
EC
53 SC15P50V2JN-2-GP
1 2C399
SCD1U16V2ZY-2GP
C399
SCD1U16V2ZY-2GP
12
R273
10K
R2J-3
-GP
R273
10K
R2J-3
-GP
1 234
RN
35
SR
N0J-6
-GP
RN
35
SR
N0J-6
-GP
TP
127
TP
127
12
R294
10K
R2J-3
-GP
VG
A_
27M
_P
HR
294
10K
R2J-3
-GP
VG
A_
27M
_P
H
1 2
C375
SC15P50V2JN-2-GP
DY
C375
SC15P50V2JN-2-GP
DY
12
R286
10K
R2J-3
-GP
R286
10K
R2J-3
-GP
1 2C704
SCD1U16V2ZY-2GP
C704
SCD1U16V2ZY-2GP
VD
DP
CI
2
VD
D48
9
VD
DP
LL3
16
VD
DR
EF
61
VD
DS
RC
39
VD
DC
PU
55
VD
D96_
IO12
VD
DP
LL3_
IO20
VD
DS
RC
_IO
26
VD
DS
RC
_IO
36
VD
DS
RC
_IO
45
VD
DC
PU
_IO
49
PC
I0/C
R#_A
1
PC
I1/C
R#_
B3
PC
I2/T
ME
4
PC
I35
PC
I4/2
7_
SE
LE
CT
6
PC
I_F
5/I
TP
_E
N7
X2
59
X1
60
US
B_
48M
HZ
/FS
LA
10
FS
LB
/TE
ST
_M
OD
E57
RE
F0/F
SLC
/TE
ST
_S
EL
62
GN
DP
CI
8
GN
D48
11
GN
D15
GN
D19
GN
DS
RC
23
GN
DS
RC
42
GN
DC
PU
52
GN
DR
EF
58
GN
DS
RC
29
SD
AT
A63
SC
LK
64
SR
CC
10
35
SR
CT
10
34
SR
CT
11/C
R#_
H33
SR
CC
11/C
R#_
G32
SR
CC
931
SR
CT
930
NC
#48
48
CK
_P
WR
GD
/PD
#56
CP
UC
053
CP
UT
054
CP
UC
1_
F50
CP
UT
1_
F51
CP
UC
2_
ITP
/SR
CC
846
CP
UT
2_
ITP
/SR
CT
847
SR
CC
7/C
R#_
E43
SR
CT
7/C
R#_
F44
SR
CC
640
SR
CT
641
CP
U_
ST
OP
#37
PC
I_S
TO
P#
38
SR
CC
428
SR
CT
427
SR
CC
3/C
R#_
D25
SR
CT
3/C
R#_
C24
SR
CC
2/S
AT
AC
22
SR
CT
2/S
AT
AT
21
27M
HZ
_S
S/S
RC
C1/S
E2
18
27M
HZ
_N
ON
SS
/SR
CT
1/S
E1
17
SR
CC
0/D
OT
C_
96
14
SR
CT
0/D
OT
T_
96
13
U18
ICS
9LP
RS
365Y
GLF
T-G
P71.0
9365.0
0W
U18
ICS
9LP
RS
365Y
GLF
T-G
P71.0
9365.0
0W
1 2C722
SCD1U16V2ZY-2GP
C722
SCD1U16V2ZY-2GP
123 4
RN
38
SR
N0J-6
-GP
RN
38
SR
N0J-6
-GP
1 2C718
SCD1U16V2ZY-2GP
C718
SCD1U16V2ZY-2GP
1 2C701
SCD1U16V2ZY-2GP
C701
SCD1U16V2ZY-2GP
12
R580
33R
2J-2
-GP
VG
A_
27M
SS
R580
33R
2J-2
-GP
VG
A_
27M
SS
1 2
C730
SC4D7U6D3V3KX-GP
DY
C730
SC4D7U6D3V3KX-GP
DY
12
C381
SC
27P
50V
2JN
-2-G
P
C381
SC
27P
50V
2JN
-2-G
P
1 234
RN
60
SR
N0J-6
-GP
RN
60
SR
N0J-6
-GP
12
R2820
R0603-P
AD
R2820
R0603-P
AD
12
R292
10K
R2J-3
-GP
DY
R292
10K
R2J-3
-GP
DY
12
R299
2K
2R
2J-2
-GP
R299
2K
2R
2J-2
-GP
123 4
RN
42
SR
N0J-6
-GP
RN
42
SR
N0J-6
-GP
1 2C702
SCD1U16V2ZY-2GP
C702
SCD1U16V2ZY-2GP
-
A A
B B
C C
D D
E E
44
33
22
11
H_A
#18
H_A
#20
H_A
#21
H_A
#22
H_A
#17
H_A
#19
H_A
#23
H_A
#24
H_A
#25
H_A
#26
H_A
#27
H_A
#28
H_A
#29
H_A
#30
H_A
#31
H_A
#3
H_A
#4
H_A
#5
H_A
#6
H_A
#7
H_A
#8
H_A
#9
H_A
#10
H_A
#11
H_A
#12
H_A
#13
H_A
#14
H_A
#15
H_A
#16
H_
RE
Q#0
H_
RE
Q#1
H_
RE
Q#2
H_
RE
Q#3
H_
RE
Q#4
H_A
#[3
5..
3]
H_
RS
#1
H_
RS
#0
H_
RS
#2
H_
IER
R#
XD
P_
BP
M#0
XD
P_
BP
M#1
XD
P_
BP
M#2
XD
P_
BP
M#3
XD
P_
BP
M#4
XD
P_
TC
KX
DP
_T
DI
XD
P_
TM
SX
DP
_T
RS
T#
XD
P_
TD
O
XD
P_
DB
RE
SE
T#
XD
P_
BP
M#5
H_
D#32
H_
D#33
H_
D#34
H_
D#35
H_
D#36
H_
D#37
H_
D#38
H_
D#39
H_
D#41
H_
D#40
H_
D#42
H_
D#43
H_
D#[6
3..
0]
H_
D#44
H_
D#45
H_
D#46
H_
D#47
H_
D#0
H_
D#1
H_
D#2
H_
D#3
H_
D#4
H_
D#5
H_
D#6
H_
D#7
H_
D#8
H_
D#9
H_
D#10
H_
D#11
H_
D#12
H_
D#13
H_
D#14
H_
D#15
H_
D#16
H_
D#17
H_
D#18
H_
D#19
H_
D#20
H_
D#21
H_
D#22
H_
D#23
H_
D#24
H_
D#25
H_
D#26
H_
D#27
H_
D#28
H_
D#29
H_
D#30
H_
D#31
H_
D#48
H_
D#49
H_
D#51
H_
D#50
H_
D#52
H_
D#53
H_
D#54
H_
D#55
H_
D#57
H_
D#56
H_
D#58
H_
D#59
H_
D#60
H_
D#61
H_
D#63
H_
D#62
CO
MP
0C
OM
P1
CO
MP
2C
OM
P3
TE
ST
1
TE
ST
2
H_
DS
TB
N#[3
..0]
H_
DS
TB
P#[3
..0]
H_
DIN
V#[3
..0]
RS
VD
_C
PU
_12
RS
VD
_C
PU
_13
RS
VD
_C
PU
_14
RS
VD
_C
PU
_4
RS
VD
_C
PU
_1
RS
VD
_C
PU
_8
RS
VD
_C
PU
_5
RS
VD
_C
PU
_6
RS
VD
_C
PU
_7
RS
VD
_C
PU
_2
RS
VD
_C
PU
_3
RS
VD
_C
PU
_10
RS
VD
_C
PU
_11
XD
P_
TD
I
XD
P_
TM
S
XD
P_
TR
ST
#
XD
P_
TD
O
H_
CP
UR
ST
#
XD
P_
DB
RE
SE
T#
XD
P_
TC
K
H_
TH
ER
MD
C
H_
TH
ER
MD
A
CP
U_
GT
LR
EF
0
RS
VD
_C
PU
_9
CP
U_
PR
OC
HO
T#_
R
TE
ST
4
TE
ST
1T
ES
T2
TE
ST
4
H_A
#32
H_A
#33
H_A
#34
H_A
#35
XD
P_
BP
M#5
H_
ST
PC
LK
#_
R
1D
05V
_S
0
1D
05V
_S
0
1D
05V
_S
0
3D
3V
_S
0
1D
05V
_S
0
H_A
DS
#6
H_
BN
R#
6
H_
DR
DY
#6
H_
DB
SY
#6
H_
BR
EQ
#0
6
H_
HIT
#6
H_
HIT
M#
6
H_
LO
CK
#6
H_
DS
TB
N#2
6H
_D
ST
BP
#2
6H
_D
INV
#2
6
H_
D#[6
3..
0]
6
H_
DS
TB
N#3
6H
_D
ST
BP
#3
6H
_D
INV
#3
6
H_A
DS
TB
#1
6
H_A
#[3
5..
3]
6
H_A
DS
TB
#0
6H
_R
EQ
#[4
..0]
6
H_
DS
TB
N#0
6H
_D
ST
BP
#0
6H
_D
INV
#0
6
H_
DS
TB
N#1
6H
_D
ST
BP
#1
6H
_D
INV
#1
6
H_
BP
RI#
6
H_
DE
FE
R#
6
H_
INIT
#16,2
7
H_
CP
UR
ST
#6
H_
RS
#[2
..0]
6
H_
TR
DY
#6
H_
TH
ER
MD
A20
CLK
_C
PU
_B
CLK
3C
LK
_C
PU
_B
CLK
#3
H_
DP
RS
TP
#7,1
6,3
2H
_D
PS
LP
#16
H_
DP
WR
#6
H_
PW
RG
D16
H_
CP
US
LP
#6
H_
FE
RR
#16
H_
TH
ER
MD
C20
PM
_T
HR
MT
RIP
-A#
7,1
6
H_
INT
R16
H_
NM
I16
H_
SM
I#16
H_
IGN
NE
#16
H_A
20M
#16
H_
DIN
V#[3
..0]
6
H_
DS
TB
N#[3
..0]
6
H_
DS
TB
P#[3
..0]
6
CP
U_
SE
L2
3,7
CP
U_
SE
L0
3,7
CP
U_
SE
L1
3,7
H_
ST
PC
LK
#16
PS
I#32
CP
U_
PR
OC
HO
T#_
R32
Title
Siz
eD
ocum
ent
Num
ber
Rev
Date
:S
heet
of
Wis
tro
n C
orp
ora
tio
n21F
, 88,
Sec.1
, H
sin
Tai W
u R
d.,
Hsic
hih
,T
aip
ei H
sie
n 2
21,
Taiw
an,
R.O
.C.
CP
U (
1 o
f 2)
44
7F
riday,
Marc
h 1
4,
2008
D45/D
46
PD
ZZ
ZZ
Title
Siz
eD
ocum
ent
Num
ber
Rev
Date
:S
heet
of
Wis
tro
n C
orp
ora
tio
n21F
, 88,
Sec.1
, H
sin
Tai W
u R
d.,
Hsic
hih
,T
aip
ei H
sie
n 2
21,
Taiw
an,
R.O
.C.
CP
U (
1 o
f 2)
44
7F
riday,
Marc
h 1
4,
2008
D45/D
46
PD
ZZ
ZZ
Title
Siz
eD
ocum
ent
Num
ber
Rev
Date
:S
heet
of
Wis
tro
n C
orp
ora
tio
n21F
, 88,
Sec.1
, H
sin
Tai W
u R
d.,
Hsic
hih
,T
aip
ei H
sie
n 2
21,
Taiw
an,
R.O
.C.
CP
U (
1 o
f 2)
44
7F
riday,
Marc
h 1
4,
2008
D45/D
46
PD
ZZ
ZZ
H_IERR# with a GND
0.1" away
Place testpoint on
Layout Note:
Comp0, 2 connect with Zo=27.4 ohm, make
Comp1, 3 connect with Zo=55 ohm, make
trace length shorter than 0.5" .
trace length shorter than 0.5" .
Layout Note:
"CPU_GTLREF0"
0.5" max length.
( No stub)
should connect to
PM_THRMTRIP#
without T-ing
ICH9 and MCH
All place within 2" to CPU
Net "TEST4" as short as possible,
make sure "TEST4" routing is
reference to GND and away other
noisy signals
SB use 62.10053.401
12
R74
54D
9R
2F
-L1-G
PR
74
54D
9R
2F
-L1-G
P
D16#
N22
D17#
K25
D18#
P26
D19#
R23
D20#
L23
D21#
M24
D22#
L22
D23#
M23
D24#
P25
D25#
P23
D26#
P22
D27#
T24
D28#
R24
D29#
L25
D30#
T25
D31#
N25
DIN
V0#
H25
DIN
V1#
N24
DS
TB
N0#
J26
DS
TB
N1#
L26
DS
TB
P0#
H26
DS
TB
P1#
M26
D0#
E22
D1#
F24
D2#
E26
D3#
G22
D4#
F23
D5#
G25
D6#
E25
D7#
E23
D8#
K24
D9#
G24
D10#
J24
D11#
J23
D12#
H22
D13#
F26
D14#
K22
D15#
H23
D53#
AC
26
D60#
AC
22
D63#
AC
23
GT
LR
EF
AD
26
TE
ST
2D
25
BS
EL0
B22
BS
EL1
B23
BS
EL2
C21
DIN
V2#
U22
D32#
Y22
D33#
AB
24
D34#
V24
D35#
V26
D36#
V23
D38#
U25
D39#
U23
D40#
Y25
D41#
W22
D42#
Y23
D43#
W24
D44#
W25
D45#
AA
23
D46#
AA
24
D47#
AB
25
DS
TB
P2#
AA
26
DS
TB
N2#
Y26
D48#
AE
24
D49#
AD
24
D52#
AB
21
D54#
AD
20
D55#
AE
22
D56#
AF
23
D57#
AC
25
D58#
AE
21
D59#
AD
21
D61#
AD
23
DIN
V3#
AC
20
DS
TB
N3#
AE
25
D51#
AB
22
D50#
AA
21
D62#
AF
22
CO
MP
0R
26
CO
MP
1U
26
DP
RS
TP
#E
5
DP
SLP
#B
5
DP
WR
#D
24
PW
RG
OO
DD
6
SLP
#D
7
PS
I#A
E6
TE
ST
1C
23
TE
ST
6A
26
TE
ST
3C
24
TE
ST
5A
F1
TE
ST
4A
F26
D37#
T22
DS
TB
P3#
AF
24
CO
MP
2A
A1
CO
MP
3Y
1
2 OF 4
DATA GRP0 DATA GRP1
DATA GRP2 DATA GRP3
MISC
U35B
BG
A479-S
KT
6-G
PU
3
2 OF 4
DATA GRP0 DATA GRP1
DATA GRP2 DATA GRP3
MISC
U35B
BG
A479-S
KT
6-G
PU
3
TP
8T
P8
TP
24
TP
24
12
R404
27D
4R
2F
-L1-G
PR
404
27D
4R
2F
-L1-G
P
12
R75
54D
9R
2F
-L1-G
PR
75
54D
9R
2F
-L1-G
P
12
R72
54D
9R
2F
-L1-G
PD
YR
72
54D
9R
2F
-L1-G
PD
Y
12
R98
0R
0402-P
AD
R98
0R
0402-P
AD
TP
7T
P7
12
R60
54D
9R
2F
-L1-G
PR
60
54D
9R
2F
-L1-G
P
TP
30
TP
30
TP
16
TP
16
TP
25
TP
25
12
R99
1K
R2J-1
-GP
DY
R99
1K
R2J-1
-GP
DY
12
R95
0R
2J-2
-GP
R95
0R
2J-2
-GP
12
R80
54D
9R
2F
-L1-G
PR
80
54D
9R
2F
-L1-G
P1
2R
79
27D
4R
2F
-L1-G
PR
79
27D
4R
2F
-L1-G
P
TP
2T
P2
1 2
R93
56R
2J-4
-GP
R93
56R
2J-4
-GP
TP
17
TP
17
12
R411
1K
R2J-1
-GP
DY
R411
1K
R2J-1
-GP
DY
TP
27
TP
27
TP
32
TP
32
TP
6T
P6
TP
26
TP
26
TP
12
TP
12
12
R67
54D
9R
2F
-L1-G
PR
67
54D
9R
2F
-L1-G
P
TP
20
TP
20
TP
11
TP
11
TP
86
TP
86
12
R403
54D
9R
2F
-L1-G
PR
403
54D
9R
2F
-L1-G
P
TP
9T
P9
12
R64
54D
9R
2F
-L1-G
PR
64
54D
9R
2F
-L1-G
P
1 2
R387
2KR2F-3-GPR387
2KR2F-3-GP
12
R386
1K
R2F
-3-G
PR
386
1K
R2F
-3-G
P
A3#
J4
A4#
L5
A5#
L4
A6#
K5
A7#
M3
A8#
N2
A9#
J1
A10#
N3
A11#
P5
A12#
P2
A13#
L2
A14#
P4
A15#
P1
A16#
R1
A20M
#A
6
AD
S#
H1
AD
ST
B0#
M1
RE
Q0#
K3
RE
Q1#
H2
RE
Q2#
K2
RE
Q3#
J3
RE
Q4#
L1
A17#
Y2
A18#
U5
A19#
R3
A20#
W6
A21#
U4
A22#
Y5
A30#
U2
A24#
R4
A25#
T5
A26#
T3
A32#
W3
A28#
W5
A29#
Y4
A27#
W2
A31#
V4
A33#
AA
4
A34#
AB
2
A35#
AA
3
FE
RR
#A
5
IGN
NE
#C
4
RS
VD
#M
4M
4
RS
VD
#N
5N
5
RS
VD
#T
2T
2
RS
VD
#V
3V
3
RS
VD
#B
2B
2
RS
VD
#C
3C
3
BN
R#
E2
BP
RI#
G5
DE
FE
R#
H5
DB
SY
#E
1D
RD
Y#
F21
BR
0#
F1
IER
R#
D20
INIT
#B
3
LO
CK
#H
4
RS
0#
F3
RS
1#
F4
RS
2#
G3
TR
DY
#G
2
HIT
#G
6
HIT
M#
E4
BP
M0#
AD
4
BP
M1#
AD
3
BP
M2#
AD
1
BP
M3#
AC
4
PR
DY
#A
C2
PR
EQ
#A
C1
TC
KA
C5
TD
IA
A6
TD
OA
B3
TM
SA
B5
TR
ST
#A
B6
DB
R#
C20
PR
OC
HO
T#
D21
TH
RM
DA
A24
TH
ER
MT
RIP
#C
7
BC
LK
0A
22
BC
LK
1A
21
RS
VD
#D
2D
2
RS
VD
#F
6F
6R
SV
D#D
3D
3R
SV
D#D
22
D22
ST
PC
LK
#D
5
LIN
T0
C6
LIN
T1
B4
SM
I#A
3
A23#
U1
AD
ST
B1#
V1
RE
SE
T#
C1
KE
Y_
NC
B1
TH
RM
DC
B25
1 OF 4
RESERVED
HCLK
THERMAL
ADDR GROUP 1
XDP/ITP SIGNALSCONTROL
ADDR GROUP 0 ICH
U35A
BG
A479-S
KT
6-G
PU
3
62.1
0079.0
01
1 OF 4
RESERVED
HCLK
THERMAL
ADDR GROUP 1
XDP/ITP SIGNALSCONTROL
ADDR GROUP 0 ICH
U35A
BG
A479-S
KT
6-G
PU
3
62.1
0079.0
01
TP
5T
P5
12
R92
68R
2-G
PR
92
68R
2-G
P
12
C471
SC
D1U
10V
2K
X-4
GP
DY
C471
SC
D1U
10V
2K
X-4
GP
DY
1 2
C113
SC
2200P
50V
2K
X-2
GP
DY
C113
SC
2200P
50V
2K
X-2
GP
DY
TP
78
TP
78
TP
18
TP
18
TP
31
TP
31
TP
13
TP
13
12
R97
54D
9R
2F
-L1-G
PD
YR
97
54D
9R
2F
-L1-G
PD
Y1 2
C475
SC1KP50V2KX-1GP
DY
C475
SC1KP50V2KX-1GP
DY
TP
4T
P4
TP
29
TP
29
12
R96
150R
2F
-1-G
PD
YR
96
150R
2F
-1-G
PD
Y
TP
3T
P3
TP
22
TP
22
TP
10
TP
10
TP
28
TP
28
-
A A
B B
C C
D D
E E
44
33
22
11
H_
VID
0H
_V
ID1
H_
VID
2H
_V
ID3
H_
VID
4H
_V
ID5
H_
VID
6
CP
U_
V6
CP
U_
G21
VC
C_
CO
RE
VC
C_
CO
RE
1D
5V
_S
0
1D
05V
_S
0
1D
5V
_V
CC
A_
S0
1D
05V
_S
0
VC
C_
CO
RE
VC
C_
CO
RE
VC
C_
CO
RE
VC
C_
SE
NS
E32
VS
S_
SE
NS
E32
H_
VID
[6..
0]
32
Title
Siz
eD
ocum
ent
Num
ber
Rev
Date
:S
heet
of
Wis
tro
n C
orp
ora
tio
n21F
, 88,
Sec.1
, H
sin
Tai W
u R
d.,
Hsic
hih
,T
aip
ei H
sie
n 2
21,
Taiw
an,
R.O
.C.
CP
U (
2 o
f 2)
54
7F
riday,
Marc
h 1
4,
2008
D45/D
46
PD
Title
Siz
eD
ocum
ent
Num
ber
Rev
Date
:S
heet
of
Wis
tro
n C
orp
ora
tio
n21F
, 88,
Sec.1
, H
sin
Tai W
u R
d.,
Hsic
hih
,T
aip
ei H
sie
n 2
21,
Taiw
an,
R.O
.C.
CP
U (
2 o
f 2)
54
7F
riday,
Marc
h 1
4,
2008
D45/D
46
PD
Title
Siz
eD
ocum
ent
Num
ber
Rev
Date
:S
heet
of
Wis
tro
n C
orp
ora
tio
n21F
, 88,
Sec.1
, H
sin
Tai W
u R
d.,
Hsic
hih
,T
aip
ei H
sie
n 2
21,
Taiw
an,
R.O
.C.
CP
U (
2 o
f 2)
54
7F
riday,
Marc
h 1
4,
2008
D45/D
46
PD
Layout Note:
should be of equal length.
VCCSENSE and VSSSENSE lines
Layout Note:
Provide a test point (with
no stub) to connect a
differential probe
between VCCSENSE and
VSSSENSE at the location
where the two 54.9ohm
resistors terminate the
55 ohm transmission line.
layout note: "1D5V_VCCA_S0"
as short as possible
1 2
C67 SCD1U10V2KX-4GP
C67 SCD1U10V2KX-4GP
1 2
R58
100R
2F
-L1-G
P-U
R58
100R
2F
-L1-G
P-U
1 2
C78 SCD1U10V2KX-4GP
C78 SCD1U10V2KX-4GP
VS
SA
F2
VS
SA
4
VS
SA
8
VS
SA
11
VS
SA
14
VS
SA
16
VS
SA
19
VS
SA
23
VS
SB
6
VS
SB
8
VS
SB
11
VS
SB
13
VS
SB
16
VS
SB
19
VS
SB
21
VS
SB
24
VS
SC
5
VS
SC
8
VS
SC
11
VS
SC
14
VS
SC
16
VS
SC
19
VS
SC
2
VS
SC
22
VS
SC
25
VS
SD
1
VS
SD
4
VS
SD
8
VS
SD
11
VS
SD
13
VS
SD
16
VS
SD
19
VS
SD
23
VS
SD
26
VS
SE
3
VS
SE
6
VS
SE
8
VS
SE
11
VS
SE
14
VS
SE
16
VS
SE
19
VS
SE
21
VS
SE
24
VS
SF
5
VS
SF
8
VS
SF
11
VS
SF
13
VS
SF
16
VS
SF
19
VS
SF
2
VS
SF
22
VS
SF
25
VS
SG
4
VS
SG
1
VS
SG
23
VS
SG
26
VS
SH
3
VS
SH
6
VS
SH
21
VS
SH
24
VS
SJ2
VS
SJ5
VS
SJ22
VS
SJ25
VS
SK
1
VS
SK
4
VS
SK
23
VS
SK
26
VS
SL3
VS
SL6
VS
SL21
VS
SL24
VS
SM
2
VS
SM
5
VS
SM
22
VS
SM
25
VS
SN
1
VS
SN
4
VS
SN
23
VS
SN
26
VS
SP
3
VS
SP
6
VS
SP
21
VS
SP
24
VS
SR
2
VS
SR
5
VS
SR
22
VS
SR
25
VS
ST
1
VS
ST
4
VS
ST
23
VS
ST
26
VS
SU
3
VS
SU
6
VS
SU
21
VS
SU
24
VS
SV
2
VS
SV
5
VS
SV
22
VS
SV
25
VS
SW
1
VS
SW
4
VS
SW
23
VS
SW
26
VS
SY
3
VS
SY
6
VS
SY
21
VS
SY
24
VS
SA
A2
VS
SA
A5
VS
SA
A8
VS
SA
A11
VS
SA
A14
VS
SA
A16
VS
SA
A19
VS
SA
A22
VS
SA
A25
VS
SA
B1
VS
SA
B4
VS
SA
B8
VS
SA
B11
VS
SA
B13
VS
SA
B16
VS
SA
B19
VS
SA
B23
VS
SA
B26
VS
SA
C3
VS
SA
C6
VS
SA
C8
VS
SA
C11
VS
SA
C14
VS
SA
C16
VS
SA
C19
VS
SA
C21
VS
SA
C24
VS
SA
D2
VS
SA
D5
VS
SA
D8
VS
SA
D11
VS
SA
D13
VS
SA
D16
VS
SA
D19
VS
SA
D22
VS
SA
D25
VS
SA
E1
VS
SA
E4
VS
SA
E8
VS
SA
E11
VS
SA
E14
VS
SA
E16
VS
SA
E19
VS
SA
E23
VS
SA
E26
VS
SA
2
VS
SA
F6
VS
SA
F8
VS
SA
F11
VS
SA
F13
VS
SA
F16
VS
SA
F19
VS
SA
F21
VS
SA
25
VS
SA
F25
4 OF 4
U35D
BG
A479-S
KT
6-G
PU
3
4 OF 4
U35D
BG
A479-S
KT
6-G
PU
3
1 2
TC
16
ST
220U
6D
3V
DM
-15G
PT
C16
ST
220U
6D
3V
DM
-15G
P
1 2
C69 SCD1U10V2KX-4GP
C69 SCD1U10V2KX-4GP
12
R94
0R
0402-P
AD
R94
0R
0402-P
AD
1 2
C501
SC
10U
6D
3V
5M
X-3
GP
C501
SC
10U
6D
3V
5M
X-3
GP
1 2
C105 SCD1U10V2KX-4GP
DYC
105 SCD1U10V2KX-4GP
DY
TP
79
TP
79
1 2
C487 SC22U6D3V5MX-L2GP
DY
C487 SC22U6D3V5MX-L2GP
DY
1 2C500 SCD01U16V2KX-3GP
C500 SCD01U16V2KX-3GP
1 2
C100 SC22U6D3V5MX-L2GP
DY
C100 SC22U6D3V5MX-L2GP
DY
1 2
C84 SCD1U10V2KX-4GP
C84 SCD1U10V2KX-4GP
1 2
C486 SC22U6D3V5MX-L2GP
DY
C486 SC22U6D3V5MX-L2GP
DY
1 2
C94 SC4D7U6D3V3KX-GP
C94 SC4D7U6D3V3KX-GP
1 2
C490 SC22U6D3V5MX-L2GP
C490 SC22U6D3V5MX-L2GP
VC
CA
7
VC
CA
9
VC
CA
C10
VC
CA
10
VC
CA
12
VC
CA
13
VC
CA
15
VC
CA
17
VC
CA
18
VC
CA
20
VC
CB
7
VC
CB
9
VC
CB
10
VC
CB
12
VC
CB
14
VC
CB
15
VC
CB
17
VC
CB
18
VC
CB
20
VC
CC
9
VC
CC
10
VC
CC
12
VC
CC
13
VC
CC
15
VC
CC
17
VC
CC
18
VC
CD
9
VC
CD
10
VC
CD
12
VC
CD
14
VC
CD
15
VC
CD
17
VC
CD
18
VC
CE
7
VC
CE
9
VC
CE
10
VC
CE
12
VC
CE
13
VC
CE
15
VC
CA
A7
VC
CA
A9
VC
CA
A10
VC
CA
A12
VC
CA
A13
VC
CA
A15
VC
CA
A17
VC
CA
A18
VC
CA
A20
VC
CA
B9
VC
CA
B12
VC
CA
B14
VC
CA
B15
VC
CA
B17
VC
CA
B18
VC
CE
17
VC
CE
18
VC
CE
20
VC
CF
7
VC
CF
9
VC
CF
10
VC
CF
12
VC
CF
14
VC
CF
15
VC
CF
17
VC
CF
18
VC
CF
20
VC
CA
B20
VC
CA
B7
VC
CA
C7
VC
CA
C9
VC
CA
C12
VC
CA
C13
VC
CA
C15
VC
CA
C17
VC
CA
C18
VC
CA
D7
VC
CA
D9
VC
CA
D10
VC
CA
D12
VC
CA
D14
VC
CA
D15
VC
CA
D17
VC
CA
D18
VC
CA
E9
VC
CA
E10
VC
CA
E12
VC
CA
E13
VC
CA
E15
VC
CA
E17
VC
CA
E18
VC
CA
E20
VC
CA
F9
VC
CA
F10
VC
CA
F12
VC
CA
F14
VC
CA
F15
VC
CA
F17
VC
CA
F18
VC
CA
F20
VC
CP
G21
VC
CP
J6
VC
CP
J21
VC
CP
K6
VC
CP
K21
VC
CP
M6
VC
CP
M21
VC
CP
N6
VC
CP
N21
VC
CP
R6
VC
CP
R21
VC
CP
T6
VC
CP
T21
VC
CP
V6
VC
CP
V21
VC
CP
W21
VC
CA
B26
VC
CA
C26
VID
0A
D6
VID
6A
E2
VID
4A
E3
VID
2A
E5
VID
5A
F3
VID
3A
F4
VID
1A
F5
VS
SS
EN
SE
AE
7
VC
CS
EN
SE
AF
7
VC
CA
B10
3 OF 4
U35C
BG
A479-S
KT
6-G
PU
3
3 OF 4
U35C
BG
A479-S
KT
6-G
PU
3
12
L21
HC
B1608K
F121T
30-G
P
L21
HC
B1608K
F121T
30-G
P
1 2
C104
SCD1U10V2KX-4GPC104
SCD1U10V2KX-4GP
1 2
C99 SC4D7U6D3V3KX-GP
C99 SC4D7U6D3V3KX-GP
TP
87
TP
87
1 2
C55 SCD1U10V2KX-4GP
C55 SCD1U10V2KX-4GP
1 2
C91 SC22U6D3V5MX-L2GP
C91 SC22U6D3V5MX-L2GP
1 2
C106 SCD1U10V2KX-4GP
C106 SCD1U10V2KX-4GP
1 2
C80 SC22U6D3V5MX-L2GP
C80 SC22U6D3V5MX-L2GP
1 2
C54 SCD1U10V2KX-4GP
C54 SCD1U10V2KX-4GP
1 2
C97 SC22U6D3V5MX-L2GP
C97 SC22U6D3V5MX-L2GP
TP
33
TP
33
1 2
C491 SC22U6D3V5MX-L2GP
C491 SC22U6D3V5MX-L2GP
1 2
C102 SCD1U10V2KX-4GP
C102 SCD1U10V2KX-4GP
1 2
C82 SCD1U10V2KX-4GP
C82 SCD1U10V2KX-4GP
12
R81
0R
0402-P
AD
R81
0R
0402-P
AD
1 2
C77 SCD1U10V2KX-4GP
C77 SCD1U10V2KX-4GP
TP
77
TP
77
1 2
R65
100R
2F
-L1-G
P-U
R65
100R
2F
-L1-G
P-U
1 2
C81 SC22U6D3V5MX-L2GP
C81 SC22U6D3V5MX-L2GP
-
5 5
4 4
3 3
2 2
1 1
DD
CC
BB
AA
H_
D#[6
3..
0]
H_
D#0
H_
D#1
H_
D#2
H_
D#3
H_
D#4
H_
D#5
H_
D#6
H_
D#7
H_
D#8
H_
D#9
H_
D#10
H_
D#11
H_
D#12
H_
D#13
H_
D#14
H_
D#15
H_
D#16
H_
D#17
H_
D#18
H_
D#19
H_
D#20
H_
D#21
H_
D#22
H_
D#23
H_
D#24
H_
D#25
H_
D#26
H_
D#27
H_
D#28
H_
D#29
H_
D#30
H_
D#31
H_
D#32
H_
D#33
H_
D#34
H_
D#35
H_
D#36
H_
D#37
H_
D#38
H_
D#39
H_
D#40
H_
D#41
H_
D#42
H_
D#43
H_
D#44
H_
D#45
H_
D#46
H_
D#47
H_
D#48
H_
D#49
H_
D#50
H_
D#51
H_
D#52
H_
D#53
H_
D#54
H_
D#55
H_
D#56
H_
D#57
H_
D#58
H_
D#59
H_
D#60
H_
D#61
H_
D#62
H_
D#63
H_
SW
ING
H_
RC
OM
P
H_
DV
RE
F
H_A
#35
H_A
#29
H_A
#30
H_A
#31
H_A
#26
H_A
#27
H_A
#28
H_A
#23
H_A
#24
H_A
#25
H_A
#20
H_A
#21
H_A
#22
H_A
#17
H_A
#18
H_A
#19
H_A
#14
H_A
#15
H_A
#16
H_A
#11
H_A
#12
H_A
#13
H_A
#8
H_A
#9
H_A
#10
H_A
#5
H_A
#6
H_A
#7
H_A
#3
H_A
#4
H_A
#[3
5..
3]
H_A
#33
H_A
#34
H_A
#32
H_
RS
#1
H_
RS
#2
H_
RS
#0
H_
RE
Q#1
H_
RE
Q#3
H_
RE
Q#2
H_
RE
Q#0
H_
RE
Q#4
H_
DS
TB
N#[3
..0]
H_
DS
TB
N#3
H_
DS
TB
N#2
H_
DS
TB
N#1
H_
DS
TB
N#0
H_
DS
TB
P#[3
..0]
H_
DS
TB
P#2
H_
DS
TB
P#0
H_
DS
TB
P#3
H_
DS
TB
P#1
H_
DIN
V#0
H_
DIN
V#1
H_
DIN
V#2
H_
DIN
V#3
H_
DIN
V#[3
..0]
H_
RC
OM
P
H_
SW
ING
H_A
VR
EF
1D
05V
_S
0
1D
05V
_S
0
H_
D#[6
3..
0]
4
H_
CP
UR
ST
#4
H_
CP
US
LP
#4
H_A
#[3
5..
3]
4
H_
BN
R#
4
H_
BR
EQ
#0
4
H_A
DS
#4
H_A
DS
TB
#0
4H
_A
DS
TB
#1
4
H_
DB
SY
#4
H_
DR
DY
#4
H_
HIT
#4
H_
HIT
M#
4
CLK
_M
CH
_B
CLK
3C
LK
_M
CH
_B
CLK
#3
H_
LO
CK
#4
H_
BP
RI#
4
H_
DE
FE
R#
4
H_
DP
WR
#4
H_
TR
DY
#4
H_
DIN
V#[3
..0]
4
H_
DS
TB
N#[3
..0]
4
H_
DS
TB
P#[3
..0]
4
H_
RE
Q#[4
..0]
4
H_
RS
#[2
..0]
4
Title
Siz
eD
ocum
ent
Num
ber
Rev
Date
:S
heet
of
Wis
tro
n C
orp
ora
tio
n21F
, 88,
Sec.1
, H
sin
Tai W
u R
d.,
Hsic
hih
,T
aip
ei H
sie
n 2
21,
Taiw
an,
R.O
.C.
Can
tig
a (
1 o
f 6) 6
47
Friday,
Marc
h 1
4,
2008
D45/D
46
PD
Title
Siz
eD
ocum
ent
Num
ber
Rev
Date
:S
heet
of
Wis
tro
n C
orp
ora
tio
n21F
, 88,
Sec.1
, H
sin
Tai W
u R
d.,
Hsic
hih
,T
aip
ei H
sie
n 2
21,
Taiw
an,
R.O
.C.
Can
tig
a (
1 o
f 6) 6
47
Friday,
Marc
h 1
4,
2008
D45/D
46
PD
Title
Siz
eD
ocum
ent
Num
ber
Rev
Date
:S
heet
of
Wis
tro
n C
orp
ora
tio
n21F
, 88,
Sec.1
, H
sin
Tai W
u R
d.,
Hsic
hih
,T
aip
ei H
sie
n 2
21,
Taiw
an,
R.O
.C.
Can
tig
a (
1 o
f 6) 6
47
Friday,
Marc
h 1
4,
2008
D45/D
46
PD
Pla
ce t
hem
near
to t
he c
hip
(
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