day4 順序控制的循序邏輯實現

DAY3DAY3

順序控制循序邏輯實現

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SR LatchSR Latch

RESETSET

Bistable → 雙穩態

SR Latch, SR Latch, 自保回路自保回路

SR LatchSR Latch

SR Latch with EnableSR Latch with Enable

LAB

D Latch: D Latch: 狀態儲存狀態儲存

D Filp Flop: Edge-Triggered LatchD Filp Flop: Edge-Triggered Latch

D Latch

D Flip Flopposedge

clock

D Flip FlopD Flip Flop

D Flip Flopnegedge clock

DFF: Enable, Preset, ClearDFF: Enable, Preset, Clear

JK Flip FlopJK Flip Flop

J & !QK & Q

T Flip FlopT Flip Flop

CounterCounter

000 – 001–010–011–100–101–110–111–000

Synchronous Counter(Synchronous Counter( 同步計數器同步計數器 ))

`

LAB

TimerTimer

one-shot

DebouncerDebouncer

LAB3

Timer DelayTimer Delay

LAB4

Verilog HDL RTL CodeVerilog HDL RTL Code

SR Latch HDL CodeSR Latch HDL Code

D Latch HDL CodeD Latch HDL Code

DFFDFF

always @(posedge clk) begin if (S) Q = 1'b1; else Q = D; end endmodule

always @(posedge clk) begin if (CE) Q = D; end

4-bit unsigned Up counter with 4-bit unsigned Up counter with asynchronous clearasynchronous clearmodule counter (C, CLR, Q);input C, CLR;output [3:0] Q;reg [3:0] Q; always @(posedge C or posedge CLR) begin if (CLR) Q = 4'b0000; else Q = Q + 1'b1; endendmodule

4-bit unsigned Down counter 4-bit unsigned Down counter with synchronous setwith synchronous setmodule counter (C, S, Q);input C, S;output [3:0] Q;reg [3:0] Q; always @(posedge C) begin if (S) Q = 4'b1111; else Q = Q - 1'b1; end endmodule

4-bit unsigned Up Counter with 4-bit unsigned Up Counter with asynchronous loadasynchronous loadmodule counter (C, ALOAD, D, Q);input C, ALOAD;input [3:0] D;output [3:0] Q;reg [3:0] Q; always @(posedge C or posedge ALOAD) begin if (ALOAD) Q = D; else Q = Q + 1'b1; endendmodule

4-bit unsigned Up counter with asyn4-bit unsigned Up counter with asyn--chronous clear and clock enablechronous clear and clock enable

module counter (C, CLR, CE, Q);input C, CLR, CE;output [3:0] Q;reg [3:0] Q; always @(posedge C or posedge CLR) begin if (CLR) Q = 4'b0000; else if (CE) Q = Q + 1'b1; endendmodule

8-bit shift-left register 8-bit shift-left register serial in serial out.serial in serial out.

module shift (C, SI, SO);input C,SI;output SO;reg [7:0] Q; always @(posedge C) begin Q <= Q << 1; // Q <= {Q[6:1], SI}; Q[0] <= SI; end assign SO = Q[7];endmodule