digital and logic designs presentation

Digital and logic designs

Topic: Binary Parallel Adder

Agenda of The Presentation

• Introduction

• Purpose

• Working

i. Serial Method

ii. Parallel Method

• Example

• Block diagram

• Carry Propagation

• Look-ahead Carry Technique

Introduction : Binary Parallel Adder

• A binary parallel adder is a circuit that produces sum of ‘n’ bit binary numbers in parallel.

• It consist of ‘n’ full adders connected in cascade.

• Output carry of one full adder is transferred as input carry to the next full adder.

PURPOSE OF PARALLEL ADDER

Purpose of parallel adder is to produce the sum of ‘n’ bit binary numbers by using n full adders.

Working

The sum of n bit of binary number can be done by two methods:

• Serial method

• Parallel method

Serial and Parallel method

• The serial method uses only one full adder circuit and storage device to hold the generated output carry.

• The parallel method uses ‘n’ full adders and all bits of binary number are applied simultaneously.

• The output carry from the one full adder is transferred as the input carry to the next full adder.

• Initially the input carry in is given as ‘0’.

Example

consider A = 1011 and B = 0011 then sum S = 1110

Subscript I 4 3 2 1

Input carry 0 1 1 0 Cin

Augend 1 0 1 1 Ai

Addend 0 0 1 1 Bi Sum 1 1 1 0 S

Output carry 0 0 1 1 Cout

Block Diagram

Q0 = S0 sum of first bit of A and B

Qn = Sn sum of second bit of A and B

Carry Propagation

• In binary parallel adder the carry must propagate through the each full adder to produce the correct output sum bit .

• The total propagation time is equal to the number of gate levels in the circuit.

• The propagation delay time in a parallel adders is the time, it takes the carry to propagate through the full adders.

Carry Propagation

• Each full adder contain two gate levels for the carry to propagate.• One OR gate

• One AND gate

So if there are four full adders used in parallel adder then there are 2 * 4 = 8 gate levels for the carry to propagate.

• For n- bit parallel adder , there are 2n bit gate level for the carry to propagate.

Carry Propagation

• The time consumed during the carry propagation in addition process is very critical.

• The carry propagation delay time can be reduced by using fast gates with reduced delays.

• Another method is to increase the equipment complexity.

• One of the technique is principle of look-ahead-carry.

• If we define two new variables :

Pi = Ai Bi

Gi = AiBi

Gi is called carry generate and it produces an output carry when both Ai and Bi are one .

Pi is called carry propagate because it is the term associated with the propagation of carry from Ci to Ci+1.

The output sum and carry can be expressed as :

S = Pi Ci

Ci+1 = Gi +PiCi

Look-ahead-carry

Look-ahead-carry Technique

• Circuit of full adder is shown below :

Look -a-head carry

• The Boolean function for the output carry for each stage are:

• C2 = G1 +P1C1

• C3 = G2 +P2C2 = G2 +P2(G1 + P1C1)= G2 +P2G1+P2P1C1

• C4 = G3 +P3C3 = G3 + P3(G2 +P2C2)= G3 + P3G2 + P3P2G1 + P3P2P1C1

Logic diagram of a look -a-head carry generator

4-bit full adder with look-ahead-carry