enhancement mode strained (1.3%) germanium quantum well ... · [1] iedm, 2010 [1] iedm, 2010 [3]...
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Enhancement Mode Strained (1.3%) Germanium Quantum Well FinFET
(Wfin=20nm) with High Mobility (μHole=700 cm2/Vs), Low EOT
(~0.7nm) on Bulk Silicon SubstrateA. Agrawal1, M. Barth1, G. B. Rayner Jr.2, V. T. Arun1,
C. Eichfeld1, G. Lavallee1, S-Y. Yu1, X. Sang3, S. Brookes3, N. Agrawal1, Y. Zheng1, Y-J. Lee4,
Y-R. Lin4, C-H. Wu4, C-H. Ko4, J. LeBeau3, R. Engel-Herbert1, S. E. Mohney1, Y-C. Yeo4 and S. Datta1
1The Pennsylvania State University 2Kurt J. Lesker Company
3North Carolina State University 4Taiwan Semiconductor Manufacturing Company
1
Outline• High Mobility Strained Germanium (s-Ge) QW
• Novel Tri-layer Dielectric Integration on Ge
• s-Ge QW on silicon Buffer Design and Growth
• s-Ge QW FinFET Fabrication and Characterization
• Benchmarking
2
Strain-Enhanced Mobility
1 10
100
1000
Strained SiRelaxed-Ge MOSFET
Mob
ility
[cm
2 /Vs]
Hole Density [x1012 /cm2]
1.3% strained-GeQWFET (TQW=15nm) 4x
Si Substrate
r-Ge
¾ 4x higher hole mobility for s-Ge QWFET compared to r-Ge MOSFET
SiGe Buffers-Ge QW
Si Substrate
Biaxial Compressive Strain
*R. Pillarisetty, Nature 2011
3
-2 -1 0 10.00.51.01.52.02.53.0
w/ Si cap
Cap
acita
nce
[PF/
cm2 ]
Gate Voltage [V]
f=1MHz
Planar
Si cap vs. GeOx IL
¾ Si cap passivation limits EOT scaling
Ge QW/10A Si cap/5A Al2O3/22A HfO2
4
Pd/AuPt/Ti/Au
Si Substrate
500 nm Si0.7Ge0.3 Buffer
Boron δ-doping 2x1018 /cm3
5 nm Si0.3Ge0.7 Spacer
10 nm Ge QW
20nm 5x1018 /cm3 PhosDoping
250 nm Si0.3Ge0.7 Buffer
9 10A Si� Limits EOT Scaling
Pt/Ti/Au Cap Layer
High-k
-2 -1 0 10.00.51.01.52.02.53.0
w/ Si cap
Cap
acita
nce
[PF/
cm2 ]
Gate Voltage [V]
f=1MHz
Planar
2.3X
GeOx IL
Si cap vs. GeOx IL
¾ GeOx IL passivation instead of Si cap realized¾ Low EOT of 0.83nm obtained on Ge QW
Ge QW/6A GeOx IL/5A Al2O3/22A HfO2
5
Pd/AuPt/Ti/Au
Si Substrate
500 nm Si0.7Ge0.3 Buffer
Boron δ-doping 2x1018 /cm3
5 nm Si0.3Ge0.7 Spacer
10 nm Ge QW
20nm 5x1018 /cm3 PhosDoping
250 nm Si0.3Ge0.7 Buffer
9 10A Si� Limits EOT Scaling9 6A GeOx� Low EOT, low DIT achieved
Pt/Ti/Au Cap Layer
High-k
Bulk FinFET vs. QW FinFET
Si Substrate
r-Ge
r-Ge
Gate Metal
Si Substrate
r-Ge
Cap layerHigh-k
s-Ge
SiGe Buffer
Gate Metal
Si Substrate
Cap LayerHigh-k
¾ Both Wfin and TQW determine strain in Ge QW
SiGe Buffers-Ge QW
Si Substrate
Biaxial Strain
WFin
TQW
6
S-Ge QW FinFET Highlights
s-Ge
SiGe BufferPhos Doping
Gate Metal
Si Substrate
SiGe Buffer Optimization� Retrograde Phos Doping; → Eliminate parallel channel
Channel Strain�Asymmetric Uniaxialstrain; → μHole Enhancement
Ge-Passivation� In-situ H-Plasma clean � Controlled sub-nm GeOx; → Low DIT Ultrathin EOT
Scaled FinFET� 20nm Fin Width; → E-Mode Operation
7
Tri-Layer High-κ Gate StackGOAL:
Sub-1 nm (EOT)
p-GeMetal
HfO2 Al2O3 GeOx
1.5eV
2.5eV
� Reduce DIT� Low temperatureprocess prevent Si-Ge interdiffusion
� PreventHfO2-GeOxintermixing
� Reduce gate leakage
EV
EC
EF
8
0 1 205
1015202530
GeO
x Thi
ckne
ss [A
]
Time [mins.]
Native GeOx
30 sec, 100W H-Plasma
T=250C0 2 4 60
2
4
6
5 10 15
Plasma-OFF
T=250C
GeO
x Thi
ckne
ss [A
]
Time [mins.]
O-Plasma 125W, 2 sec Pulse
Plasma-ON
Cycle #
¾ Removal of native GeOx with low power H-Plasma etch¾ High quality, uniform GeOx IL formed using low power O-Plasma pulse 9
Tri-Layer Process Flow
Tri-Layer Process Flow
0 2 4 6 8 100
2
4
6
T=250C
Al 2O
3 Thi
ckne
ss [A
]
Cycle #
Thermal ALDTMA Precursor + H2O
Nucleation delay
0 5 10 15 200
5
10
15
20
No Nucleationdelay
HfO
2 Thi
ckne
ss [A
]
Cycle #
Thermal ALDTDMAH Precursor + H2OT=250C
¾ Ultrathin Al2O3 cap layer and HfO2 high-κdeposited using Thermal ALD
10
Tri-Layer High-κ: In-situ GeOxPassivation
0 1 2 3 4 5 6 7 8
Cou
nt [a
.u.]
Depth [nm]
Ge Al O Hf
2nm
17A HfO2
Ge
6A GeOx/5A Al2O3
¾ In-situ plasma clean and GeOx IL realized for enhanced surface passivation¾ Low power plasma reduces surface roughness11
-2 -1 0 1 20
1
2
3
Thickness
HfO2/ 5A Al2O3/ 6A GeOx/p-Ge
T=300K
Cap
acita
nce
[PF/
cm2 ]
Gate Voltage [V]
75kHz to 2MHz
HfO2
30A
22A20A
17A HfO2/3A Al2O3/6A GeOx/p-Ge
¾ EOT of ~0.72nm achieved¾ Band-edge DIT from low 1012 to 1013 /cm2/eV in midgap observed
0.0 0.1 0.2 0.31012
1013
1014
17A 20A 22A 30A
DIT [/
cm2 /e
V]
Energy [E-EV]
EV
HfO2 Thickness
HfO2/5A Al2O3/6A GeOx/p-Ge
12
Tri-Layer High-κ/Ge C-V Characteristics
Gate Leakage Reduction
-1 0 110-7
10-5
10-3
10-1
101
J G [A
/cm
2 ]
Gate Voltage [V]
HfO2
[2] 22A HfO2/2A Al2O3/3A GeOx
103X
HfO2/5A Al2O3/6A GeOx/p-Ge
T=300KReducing
0.0 0.5 1.0 1.5 2.010-710-510-310-1101103105
HfO2/Al2O3/GeOx
[3]
J G [A
/cm
2 ] @ V
FB -1
V
EOT [nm]
[1] Poly Si/SiO2
[2] Al2O3/GeOx
[4] HfO2 (w/ IL)
[1] HfO2 (no IL)
4XThis work
HfO2/Al2O3/GeOx
¾ Low gate leakage of 10-2 A/cm2 (VG=VFB-1V) obtained at 0.72nm EOT with Tri-layer gate stack
[1] C. Choi et al., EDL 2004 [2] R. Zhang et al., IEDM 2011[3] R. Zhang et al., IEDM 2013 [4] R. Xie et al., IEDM 2008
13
-1 0 110-410-310-210-1100101102
Depth=250nm
Depth=150nm
I D [P
A/P
m]
Gate Voltage [V]
VDS=-0.5VLG=5Pm
No PhosPhos Doping Depth
Planarw/ Si cap
100mV/dec
¾ 103X IOFF reduction with deeper Phos doping in SiGe buffer with no degradation in ION
s-Ge QW on Silicon: SiGe Buffer Optimization
14
Si Substrate
500 nm Si0.7Ge0.3 Buffer
3nm Boron Modulation doping5 nm Si0.3Ge0.7 Spacer
10 nm Ge QWSi Cap
20nm 5x1018 /cm3 Phos Doping
Si0.3Ge0.7 Buffer
2 μm Si0.3Ge0.7 Buffer
Depth=150nm, 250nm
-1 0 110-5
10-3
10-1
101
103
96mV/dec
Planar
I D [P
A/P
m]
Gate Voltage [V]
VDS=-0.05V, -0.5VLG=5Pm
w/ GeOx IL
w/ Si cap
100mV/dec
-1.0 -0.5 0.00
100
200
300
-1.0 -0.5 0.00
50
100
150
Drain Voltage [V]
|VG-VT|=-1V to 1VVG,Step=0.1V
LG=5Pm w/ GeOx IL
Sour
ce C
urre
nt [P
A/P
m]
w/ Si Cap
¾2X higher ION (VDS=-0.5V) with 96 mV/decsubthreshold slope obtained with Tri-layer high-κ
Ge QW/Si Cap or GeOx IL/5A Al2O3/22A HfO2
QW MOSFET with Tri-layer High-k
15
5 10 15 20 250
200
400
600
800
[1] IEDM, 2010
[1] IEDM, 2010
[3] IEDM, 2005
Hol
e M
obili
ty [c
m2 /V
s]
EOT [A]
[2] VLSI, 2009
This workw/ Si cap
4X
Drift Mobility
1012 1013
100
1000
Hol
e M
obili
ty [c
m2 /V
s]
Hole Density [/cm2]
w/ GeOx IL w/ Si Cap
Si Universal
Unstrained Ge
This work
4X
¾4X higher hole mobility compared to r-Ge achieved
[1] R. Pillarisetty et al., IEDM 2010 [2] J. Mitard et al., VLSI 2009 [3] O. Weber et al., IEDM 2005
16
Ns=5x1012 /cm2
5 10 15 20 250
200
400
600
800
[1] IEDM, 2010
[1] IEDM, 2010
[3] IEDM, 2005
Hol
e M
obili
ty [c
m2 /V
s]
EOT [A]
[2] VLSI, 2009
This workw/ Si cap
This workw/ GeOx IL
4X
Drift Mobility
1012 1013
100
1000
Hol
e M
obili
ty [c
m2 /V
s]
Hole Density [/cm2]
w/ GeOx IL w/ Si Cap
Si Universal
Unstrained Ge
This work
4X
¾ Highest hole mobility at lowest EOT achieved with GeOx IL
[1] R. Pillarisetty et al., IEDM 2010 [2] J. Mitard et al., VLSI 2009 [3] O. Weber et al., IEDM 2005
17
Ns=5x1012 /cm2
Outline
Integrate s-Ge QW and Tri-layer high-κ in a FinFET
18
Asymmetric Strained FinFET
¾ Strain relaxation near sidewall results in net uniaxial strain along the channel direction 19
-10 0 10-1.5-1.0-0.50.0
Position Across Fin [nm]Tran
sver
seSt
rain
, HXX
[%]SiGe Buffer
s-Ge QW
Si Substrate
Biaxial Compressive Strain
Phos Doping
εXX [%]0.5
-2
Phos DopingSiGe Buffer
TransverseX
YZ
(100)
Si Substrate
20 40-2
-1
0
1
Stra
in, H
xx [%
]
Fin Width [nm]
Tran
sver
se
-2.5
-2.0
-1.5
Strain, HYY [%
]Longitudinal
Fin Mobility
¾ Mobility enhancement due to increasing uniaxialcompressive strain with reducing Wfin 20
0 -1 -2 -30
500
1000
150020nm (100)Ge
Hol
e M
obili
ty [c
m2 /V
s]
Uniaxial Strain [%]
(110)Ge
50nm
Wfin
* M. Chu et al., Annu. Rev. Mater. Res. 2009
Ns=1013 /cm2
FinFET Fabrication Flow
Si Substrate
500 nm Si0.7Ge0.3 Buffer
3nm Boron Modulation doping5 nm Si0.3Ge0.7 Spacer
10 nm Ge QW1 nm Si Cap
20nm 5E18 /cm3 Phos Doping
250 nm Si0.3Ge0.7 Buffer
2 μm Si0.3Ge0.7 Buffer
PRPR
Fin Pattern + Deposit Hardmask
10 nm Ge QW
Si0.3Ge0.7 Buffer
10nm Ge QW
Si Substrate
500 nm Si0.7Ge0.3 Buffer
20nm 5E18 /cm3 Phos Doping
Gate Metal
Si0.3Ge0.7 Buffer
B-doping
SiGe Buffer
Dry RIE Etch with Hardmask
Fin Pattern + Hardmask Deposition
Dry RIE Etch
Tri-Layer High-k +Gate Patterning 21
¾ FinFET fabrication using Sidewall Image Transfer (SIT)
FinFET Fabrication : SEM
¾ Wfin=20nm; Fin pitch = 80nm; Tri-layer high-κrealized on s-Ge QW with SIT process
Sour
ce
Dra
inGate Fin
Wfin=20nm
200 nm20 nm
Fin Pitch=80nm
Wfin=20nm
Ge Ge
Si0.3Ge0.7 Si0.3Ge0.7
22
FinFET Fabrication : TEM
¾ Vertical fin sidewall profile achieved for Wfin=20nm QW FinFET
Ge
Si0.3Ge0.7Buffer
Wfin=20nm
HfO2
Al2O3/GeOx
10nm
10nm Ge QW
Si Substrate
500 nm Si0.7Ge0.3 Buffer
20nm 5E18 /cm3 Phos Doping
Gate Metal
Si0.3Ge0.7 Buffer
B-doping
23
-2 -1 0 110-310-210-1100101102103
-0.5VLG=5Pm
I D [P
A/P
m]
Gate Voltage [V]
Planar 20nm
VDS=-0.05V
WFin
w/ GeOx IL
96mV/dec150mV/dec
Long Channel FinFETPerformance
-1.0 -0.5 0.00
100
200
300
Planar FinFET (WFin=20nm)
I D [P
A�P
m]
Drain Voltage [V]
|VG-VT|=-1V to 1VVG,Step=0.1V
LG=5Pm
¾ E-Mode (VT=-0.75V); ION/IOFF~104; SS=150mV/decfor Wfin=20nm FinFET with Tri-layer high-κ obtained24
E-Mode QW FinFET Operation
¾ E-Mode operation for Wfin=45nm and 20nm¾ Degradation in SS (36%) and peak Gm (60%) with reducing Wfin
Wfin=20nm; LG=5μm; 10 fins/μm
25
50 Planar-0.8-0.6-0.4-0.20.00.20.4 Depletion
Mode
V T,SA
T [V]
Fin Width [nm]
EnhancementMode
LG=5PmVDS=-0.5V
20 50 Planar90100110120130140150 VDS=-0.5V
SS [m
V/de
c]
Fin Width [nm]20 50 Planar
100
150
200
250
VDS=-0.5VPeak
Gm
[PS/Pm
]Fin Width [nm]20
1012 1013
100
1000
2.6X
Planar WFin=70nm WFin=45nm WFin=20nm
Hol
e M
obili
ty [c
m2 /V
s]
Hole Density [/cm2]
Si UniversalUnstrained Ge
2X
T=300K
¾ 2.6X higher μPeak obtained with s-Ge QW FinFET (Wfin=20nm) compared to unstrained-Ge
50 Planar700
800
900
1000
Peak
Mob
ility
[cm
2 /Vs]
Fin Width [nm]20
26
Fin Mobility
FinFET Hole Transport Highlights
Hol
e M
obili
ty [c
m2 /V
s]
Hole Density [/cm2]
PlanarFinFET
¾ Reducing sidewall DIT and sidewall roughness key to achieving higher fin mobility 27
1012 1013
100
1000
1012 1013
N-1S
N-1S
77K 150K 300K
Hol
e M
obili
ty [c
m2 /V
s]
Hole Density [/cm2]
NS
Planar
N-1S
FinFET (WFin=20nm)
N-2SNS
Transport Degradation
Scattering Mechanism Ns and T Dependence
Acoustic Phonon Ns-1/3 T
Sidewall Roughness Ns-2 T0
Remote Charge Scattering Ns3/2 T0
¾ Strong Ns dependence for FinFET at 77K indicates sidewall roughness scattering 28
100 200100
1000
T0
Planar WFin=70nm
Hol
e M
obili
ty [c
m2 /V
s]
Temperature [K]
WFin=45nm WFin=20nm
Ns=1013 /cm2
T-1
Transport Degradation
Scattering Mechanism Ns and T Dependence
Acoustic Phonon Ns-1/3 T
Sidewall Roughness Ns-2 T0
Remote Charge Scattering Ns3/2 T0
¾ Reduced temperature dependence of mobility for FinFET is indicative of sidewall roughness 29
Short Channel Ge QW FinFET
¾ Short channel FinFET with gate length of 100nm and Tri-layer high-κ fabricated using SIT
100nm
Sour
ce Drain
Gate Fin
30
20nmSi0.3Ge0.7 Buffer
10nm s-Ge QW
100nm LG
Al Gate
GeOx/Al2O3HfO2
Short Channel FinFET Performance
Wfin=20nm; LG=100nm; 10 fins/μm
-1.5 -1.0 -0.5 0.0 0.510-6
10-4
10-2
100
102
VDS=-0.05V
I D [P
A/P
m]
Gate Voltage [V]
VDS=-0.5V
130 mV/dec
Tri-Layer High-k/s-Ge QW FinFET -1.0 -0.5 0.00
50
100
150
200
I D [P
A�P
m]
Drain Voltage [V]
|VG-VT|=-1V to 1VVG,Step=0.1V
Tri-Layer High-k/s-Ge QW FinFET
¾ E-Mode LG=100nm QW FinFET (Wfin=20nm) with with ION=90μA/μm (VG-VT=-0.5V) and SS=130 mV/dec
31
-1.5 -1.0 -0.5 0.00
50
100
150
200
LG=100nm
Gm [P
S/Pm
]
Gate Voltage [V]
VDS=-0.5VWFin=20nm
Tri-Layer High-k/s-Ge QW FinFET
1.6X
LG=5Pm
Transconductance
0 1 2 3 4 50
1x1042x1043x1044x1045x1046x1047x104
RSD
-Lin
ear [:
�Pm
]
RExt = 6.4k:-PmLG=100nm
VG-VT=0V
VG-VT=-0.2V
VG-VT=-0.8V
FinFETWFin=20nm
Gate Length [Pm]
¾ Peak Gm enhancement of 1.6X observed for Lg=100nm QW FinFET¾ High Raccess=6.4kΩ-μm limits short channel performance 32
-1.5 -1.0 -0.5 0.010-6
10-4
10-2
100
102
104
I D [P
A/P
m]
VG-VT [V]
VDS=-0.5V
WFin=20nmLG=100nm
[1] Intel 22nmpMOS FinFET
Benchmarking
[1] C. Auth et al., VLSI 2012
¾ 3D simulation model calibration to experiment performed using self-consistent Poisson-Schrodinger solver for QW FinFET
33
-1.5 -1.0 -0.5 0.010-6
10-4
10-2
100
102
104
I D [P
A/P
m]
VG-VT [V]
VDS=-0.5V
WFin=20nmLG=100nm
20X
[1] Intel 22nmpMOS FinFET
¾ vinj estimated at 8x106 cm/s for s-Ge QW short channel FinFET at LG=100nm
0.0 0.1 0.2 0.3 0.40
5
10source
v eff [x
106 c
m/s
]
Channel Position [nm]
virtual
vinj=8x106 cm/s
LG=100nm
Intel 22nm pMOS FinFET
VGS=VDS=-0.5V
3x106 cm/s
Rext = 6.4 kΩ-μm -> 200 Ω-μm
Performance Projection
34[1] C. Auth et al., VLSI 2012
Conclusion¾ Asymmetric uniaxial strain along fin (1.8%) results in high hole mobility in s-Ge QW FinFET
¾ In-situ H-plasma clean and Tri-layer High-k gate stack developed: Low leakage (10-2 A/cm2), low DIT at ultrathin EOT (0.72nm) obtained
¾ Mobility of 770 cm2/Vs at 0.83nm EOT achieved with s-Ge QW MOSFETs
¾ E-Mode 1.3% s-Ge QW FinFET with Wfin=20nm and μHole=700 cm2/Vs (2.6X over r-Ge) achieved with Tri-layer high-k
¾ s-Ge QW FinFET shows 8x106 cm/s vinj (simulation) with lower Raccess
35
Acknowledgements
36
� TSMCo Exploratory Technology Development
� Kurt J. Lesker Co.� Penn State Nanofab� National Science Foundation
THANK YOU
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