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Full Custom Layout Design Flow

指導教授: 董蘭榮負責助教: 原祥富上課日期: 2013/11/13

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Outlines Schematic design with Composer Pre-simulation using Hspice Layout design with Virtuoso Layout verification with Calibre

Design Rule Check (DRC) Layout Versus Schematic (LVS) Layout Parasitic Extraction (PEX)

Post-simulation using Hspice

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Workstation: 140.113.146.24~27 & 34

Technology file: CIC 0.18um 1.8V/3.3V 1P6M Virtual Mixed Mode/RFCMOS Process

Tool Hspice - hspice_2012.06-SP2_linux CosmosScope - cosmos_scope_2010.03_linux Virtuoso - IC_51.41.151_linux Calibre - calibre_2012.2_26.20_linux32

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Announcements

Full Custom Layout Design Flow

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Pre-Simulationtool: Hspice

Specification

Circuit Designtool: Schematic

Layout Designtool: Virtuoso or Laker

Design Rule Check (DRC)tool: Calibre

Layout Versus Schematic (LVS)tool: Calibre

Tapeout

Layout Parasitic Extraction (PEX)tool: Calibre

Post-Simulationtool: Hspice

Technology Files

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Hspice cic018.l

Virtuoso display.drfcic18.tf

DRC rule.drcLVS Rule.lvs

PEXRule.rceRule_08KA.rcRule_20KA.rc

Prepare Files Type: “cp /usr2/ce21/student/u97/u9712525/.tcshrc . ” Type: “cp /usr2/ce21/student/u97/u9712525/.cdsinit . ” Type: “cp /usr2/ce21/student/u97/u9712525/calibre.cshrc . ” Type: “source .tcshrc ” Type: “source calibre.cshrc” Type:

“cp /usr2/ce21/student/u97/u9712525/test/CadenceVirtuoso . ” Type: “./CadenceVirtuoso”

( to create the symbolic link of the technology files )

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Cadence Virtuoso Command: icfb &

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Ignore this error

1.

2.

Create a New Library (1) Tools Library manager

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1.

2.

3.

1.

Create a New Library (2) File New Library

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2.

New a library name

The path of this new library

Press ok to build up

3.

Setup the Technology File Browse cic18.tf (CIC technology file)

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1. 2.

3.

Loaded Successfully You must place the “ cic18.tf ” in the same directory where you execute the

command “ icfb & ”, or the complete path must be given.

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Start to Schematic Work Library manager select the library name you just created,

ex “VLSI” in this example. File New Cell View

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1.

your library name

2.

3.

Type cell name

Composer-Schematic for design your ckt

Schematic Window

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Check and SaveSave

Add instance

Wire

Add Pin

Hot Key

Add Instance: NMOS

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1.

2.

3.

4.

Library: analogLibCell: nmos4View: symbol

Model name: n_18Width:Length:

Modify the parameter of the component:click and choose the component, and press Q to modify.

Add Instance: PMOS

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1.

2.

3. 4.

Library: analogLibCell: pmos4View: symbol

Model name: p_18Width:Length:

Add Instance: VCC

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1.

2.

3.

Add Instance: GND

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1.

2.

3.

Add Pin

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1.

2.Choose the type of the pin

Example: Inverter

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Remember to Check and Save

You need to make sure no error in the schematic.

Export the sp file File Export CDL

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1.

2.

3.

4.

Browse the schematic file

Type your sp ffile name

The sp file

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The path you save the (name).sp

File Modification for LVS

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Title

Add “*” berfore “.PARAM”

Modification: 1. MM1 M12. MM0 M03. PM p_184. NM n_18

LVS will burst out many errors if you don’t modify this file!!

The (name).sp file will be used later in LVS!!

Pre-Simulation

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Notice: 1. The technology file changes to “cic018.l”. 2. Model name for NMOS: n_183. Model name for PMOS: p_18

Example Code

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HSPICE Simulation Commands

hspice <-I path/input_file> <-o path/output_file>

-i path/input_fi:Name of the input netlistfile. If you do not enter an extension, HSPICEassumes .sp.-o path/output_file:Name of the output file. If you do not specify an extension, HSPICEassigns .lis.

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HSPICE Simulation Commands Examples

hspice -i demo.spdemo is the root input file name. Without the -o argument and without redirection, HSPICE does not generate an output listing file.

hspice -i demo.sp -o demodemo is the output file root name (designated with the -o option). Output files are named demo.lis, demo.tr0, demo.st0, and demo.ic0.

hspice demo.sp -n 7 > demo.outThis command redirects output to a file instead of stdout. demo.sp is the input netlist file. The .sp extension is optional. The -n 7 starts the output data file revision numbers at 7; for example: demo.tr7, demo.ac7, demo.sw7, and so forth. The > redirects the program output listing to file demo.out.

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CosmosScope

scope &

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Start to Layout Work

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Tools Library manager select the library name you just created, ex “VLSI” in this example.

File New Cell View1. 2.

Choose Virtuoso for layout cell view

Layout Work Windows LSW: Choose the material for your layout Layout plane: A design platform with P-substrate in default

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Hot Key for Layout Design

R Rectangle shift + Z Zoom inK Create ruler ctrl + Z Zoom outS Sketch shift + K Clear all rulersF Fit all Esc CancelC Copy Delete DeleteM Move ctrl + P Add pinsMouse left button to choose , right botton to zoom in

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Display Options

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Adjust the snap spacing to 0.01um, so that you can draw the minimum length

0.18um.

Inverter Layout

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Nwell

PIMP

NIMP

DIFF

PO1

ME1

M1_TEXT

CONT

PMOS

NMOS

in

vcc

gnd

out

Calibre – DRC (1) Calibre Run DRC

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DRC starts here!!

Calibre – DRC (2)

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Cancel

Calibre – DRC (3) Rule … select “rule.drc” ok

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1. 2.

3.

4.

Calibre – DRC (4)

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DRC file is ready.

Calibre – DRC (5) Input page Don’t change anything!!

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Your layout file

Cell name

Calibre – DRC (6) Output page - Don’t change anything!! Start to run DRC

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1.

2.

Calibre – DRC (7) Summary report You should need to make sure no any DRC errors before going to LVS.

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No error!!

Calibre – DRC (8) Error: the two PIMP regions are too close!! The minimum space between two PIMP region is 0.45um.

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error!!

You can highlight the error.

Calibre – LVS (1) Calibre Run LVS

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LVS starts here!!

Calibre – LVS (2)

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Cancel

Calibre – LVS (3) Rule … select “Rule.lvs” ok

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1. 2.

3.

4.

Calibre – LVS (4)

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LVS file is ready.

Calibre – LVS (5) Input page Compare Layout vs. Netlist

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Your layout file

Netlist extracted from layout

The sp file produced from the schematic.

Calibre – LVS (6) Output page - Don’t change anything!! Start to run LVS

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1.

2.

Calibre – LVS (7) LVS pass!!

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Calibre – PEX (1) Calibre Run PEX

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PEX starts here!!

Calibre – PEX (2) Rules … Rule.rce ok

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1. 2.

3.

4.

Calibre – PEX (3)

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Calibre – PEX (4) Input page

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The sp file produced from the schematic.

Calibre – PEX (5) Output page Netlist:

Extraction type: R+C Format: HSPICE Names: LAYOUT

Nets: All Nets

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1.

2.

Calibre – PEX (6) Output Result:

INV.pex.netlist INV.pex.netlist.INV.pxi INV.pex.netlist.pex

Netlist with the parasitic RC

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Post-Simulation

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Post-simulation

Simulation Results

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Pre-sim result Post-sim result

Thank you

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