hsdsl lab pcr cordic implementation on fpga one semester project winter 2013/14

HSDSL Lab

PCR CORDIC implementation on FPGA

one semester projectwinter 2013/14

Supervisor:Moni Orbach

Students:Or Rotem Malachi Levi

Project goalsImplementing cordic algorithm in VHDL environment

Investigating different acceleration methods

Testing performance and tradeoffs

What is Cordic?

The architecture – pipeline chosentop level

Compare calculation

block

Result calculation

block

Compare calculation

block

Result calculation

block

The Blocks

Work environmentC golden model – Code Blocks

VHDL – Quartus, Model SimDE2 board

Test environment – model sim

DUTCORDIC

Output txt

Golden model

Monitor-compar

e

Angles(TXT)

Generatorreal2bin

Sin(bin, txt)

Cos(bin, txt)

performance test environmentThroughput – timing analysis after synthesis in

model simLatency – timing analysis after synthesis in model

simResources – quartos compilation plot

Grant timeline

Jan 1

2 3 4 5 Feb 1

2 3 4 Mar 1

2 3 4 Apr 1

2 3

synthesis

Post syn simulation

debuggingPerformers

improvement

Book writing

end

Appendix – cordic proof 1

Appendix – cordic proof