lab4 veriistrutment 使用說明 及 fpga 使用
Post on 05-Jan-2016
116 Views
Preview:
DESCRIPTION
TRANSCRIPT
-
Lab4
VeriIstrutment FPGA**
-
**1.code()
-
**2.
-
**3. Assignment > Device
-
**4.(4)
-
**5.PIN(1/3)Assignment > Pin
-
**5.PIN(2/3)(1).
(2).
-
**5.PIN(3/3)X
-
**6.
-
**7. Download FPGA (1/2)(1)Programmer(2)Hardware Setup 23
-
**7. Download FPGA (2/2)FINISH!!!
-
**VeriInstument ( 1/6 )(New Project)Project File AlteraQuartusII Pin Info File VERILOGXXX.qsfXXXVERILOG
-
**VeriInstument ( 2/6 )PINQUARTUSPIN
-
**VeriInstument ( 3/6 )PINqsf
-
**VeriInstument ( 4/6 )
-
**VeriInstument ( 5/6 ) PINI/O(PINport)
-
**VeriInstument ( 6/6 )FPGA!!!(100~1000Hz)aboffa onb off(sum)a onb on(carry_out)
-
Lab4-1
(Download)**
-
Part 1Design & Simulation c:\logiclab\\ lab4_1
Quartus II project
working directory c:\logiclab\\lab4_1
project FPGA_practice
File -> New Verilog HDL File verilog
verilog
**
-
Part 1Design & Simulationmodule FPGA_practice (led0,led1,led2,led3, in0, in1);input in0, in1;output led0, led1, led2, led3;reg led0, led1, led2, led3;always@( in0 or in1 )begincase( {in1,in0} )2'b11: {led3,led2,led1,led0} = 4'b1110;2'b10: {led3,led2,led1,led0} = 4'b1101;2'b01: {led3,led2,led1,led0} = 4'b1011;2'b00: {led3,led2,led1,led0} = 4'b0111;endcaseendendmodule**
-
Part 1Design & Simulationmodule FPGA_practice (led0,led1,led2,led3, in0, in1);input in0, in1;output led0, led1, led2, led3;reg led0, led1, led2, led3;always@( in0 or in1 )begincase( {in1,in0} )2'b11: {led3,led2,led1,led0} = 4'b1110;2'b10: {led3,led2,led1,led0} = 4'b1101;2'b01: {led3,led2,led1,led0} = 4'b1011;2'b00: {led3,led2,led1,led0} = 4'b0111;endcaseendendmodule8. Start Analysis & Synthesis**
-
Part 2 Assign Device Device
Family Cyclone available devices EP1C6Q240C8
Device & Pin Options Device & Pin Options **
-
Part 2 ** Device & Pin Options Configuration Configuration scheme Passive Serial(can use configuration Device)
-
Part 2 ** Device & Pin Options Unused Pins unused pins As inputs,tri-stated
-
Part 2 ** Device & Pin Options Voltage LVCOMS OK
-
Part 3** Assignment -> Pins Location pin Pin
-
Part 3** pin compile
-
Part 4(Download)** jumper NorMode
-
Part 4(Download)** PowerByteBlaster download cable USB (POWER )
Quartus II Programmer
-
Part 4(Download)** Programmer Hardware Setup HardwareSetup Hardware Setting Current selected hardware ByteBlasterII [LPT1] OK21. Programmer ,Program/Configure22. start download23. Download VeriLite Switch 1~2 .
-
Lab4-2
(LED)**
-
** c:\logiclab\\ lab4_2
Quartus II project
working directory c:\logiclab\\lab4_2
project showLED
File -> New Verilog HDL File verilog
verilog Part 1Design Download
-
**Part 1Design Downloadmodule showLED (led0,led1,led2,led3, in0, in1);input in0,in1;output led0,led1,led2,led3;reg led0,led1,led2,led3;always@( in0 or in1 )begincase( {in1,in0} )2'b00: {led3,led2,led1,led0}=4'b0001;2'b01: {led3,led2,led1,led0}=4'b0010;2'b10: {led3,led2,led1,led0}=4'b0100;2'b11: {led3,led2,led1,led0}=4'b1000;endcaseendendmoduleStart Analysis & Synthesis Lab4-1 Part 2
-
**Part 1Design Download Part 3 pin pin
-
**Part 1Design Download11. Lab4-1 Part 4Download
-
**Part 212. ->->SMIMS CORPS->VeriInstrument_USB VeriInstrument
-
**Part 2
Project File c:\logiclab\\lab4_2\.dkp
Altera Quartus II Pin info File c:\logiclab\\lab4_2\showLED.qsfqsf compile pin compile
Pin Assignment pin .
-
**Part 2 I/O 4 LED
-
**Part 2 Pin input in0 in1,
-
**Part 2 output led0,led1,led2,led3 4 led GO LED
-
Lab4-3
**
-
** c:\logiclab\\ lab4_3
Quartus II project
working directory c:\logiclab\\lab4_3
project SevenSeg
File -> New Verilog HDL File verilog
verilog Part 1Design Download
-
**Part 1Design Downloadmodule SevenSeg ( dout, din);
input [3:0] din;output [6:0] dout;reg [6:0] dout;always@(din)begincase(din)4'b0000 : dout = 7'b0111111 ;4'b0001 : dout = 7'b0000110 ;4'b0010 : dout = 7'b1011011 ;4'b0011 : dout = 7'b1001111 ;4'b0100 : dout = 7'b1100110 ;4'b0101 : dout = 7'b1101101 ;4'b0110 : dout = 7'b1111101 ;4'b0111 : dout = 7'b0000111 ;4'b1000 : dout = 7'b1111111 ;4'b1001 : dout = 7'b1101111 ;4'b1010 : dout = 7'b1110111 ;4'b1011 : dout = 7'b1111100 ;4'b1100 : dout = 7'b0111001 ;4'b1101 : dout = 7'b1011110 ;4'b1110 : dout = 7'b1111001 ;4'b1111 : dout = 7'b1110001 ;default : dout = 7'b0000000 ;endcaseendendmodule
-
**Part 1Design DownloadStart Analysis & Synthesis Lab5-1 Part 2 Lb5-2, pin
-
**Part 1Design Download10. Lab4-1 Part 4Download
-
**Part 2->->SMIMS CORPS->VeriInstrument_USB VeriInstrument Project File c:\logiclab\\lab4_3\.dkpAltera Quartus II Pin info File c:\logiclab\\lab4_3\SevenSeg.qsf I/O 1 4
-
**Part 2 Pin input din[0], din[1], din[2], din[3] output PIN
-
**Part 2 dout[0], , dout[6] 7SEG_A, , 7SEG_GGO LED
-
4**
-
**4-bit
-
**clock: 28
input: 113~117, 104~108, 98~101, 93~95, 82~88, 73~79
output: 2, 4~8, 11~21, 23, 41, 233~238, 222~228, 213~219
-
** : Part 1Part 2
*********
top related