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1ARM University ProgramCopyright © ARM Ltd 2013ARM University ProgramCopyright © ARM Ltd 2013
Communication Devices
Structure and Programming
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2ARM University ProgramCopyright © ARM Ltd 2013ARM University ProgramCopyright © ARM Ltd 2013
Overview Serial communications
Concepts
Tools
Software:
polling,
interrupts and buffering
UART communications
Concepts
KL25 I2C peripheral
DMA – Direct Memory Access
Concepts
KL DMAMUX and DMA module
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3ARM University ProgramCopyright © ARM Ltd 2013ARM University ProgramCopyright © ARM Ltd 2013
SERIAL COMMUNICATION
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4ARM University ProgramCopyright © ARM Ltd 2013ARM University ProgramCopyright © ARM Ltd 2013
Why Communicate Serially?
Native word size is multi-bit (8, 16, 32, etc.)
Often it’s not feasible to support sending all the word’s bits at the
same time Cost and weight: more wires needed, larger connectors needed
Mechanical reliability: more wires => more connector contacts to fail
Timing Complexity: some bits may arrive later than others due to variations incapacitance and resistance across conductors
Circuit complexity and power: may not want to have 16 different radiotransmitters + receivers in the system
Serial Communication examples:
UART, SPI, I2C
SATA
PCIe
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5ARM University ProgramCopyright © ARM Ltd 2013ARM University ProgramCopyright © ARM Ltd 2013
Synchronous Serial Data Transmission
Use shift registers and a clock signal to convert between serial andparallel formats
Synchronous: an explicit clock signal is along with the data signal
Clk
D Q
D3
D Q
D2
D Q
D1
D Q
D0
SerialData Out
Parallel Data In
Clk
D Q
D3
D Q
D2
D Q
D1
D Q
D0
Serial
Data In
Parallel Data Out
Transmitting Device Receiving Device
Clock
Serial Data
Data Sampling Time at Receiver
Load
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6ARM University ProgramCopyright © ARM Ltd 2013ARM University ProgramCopyright © ARM Ltd 2013
Synchronous Full-Duplex Serial Data Bus
Solves a problem of two-way communication
We can use two separate serial data lines - one for reading, one forwriting.
Allows simultaneous send and receive: full-duplex communication
MCU
PeripheralDOut
Select
DInClk
PeripheralDOut
Select
DIn
PeripheralDOut
Select
DIn
PeripheralDOut
Select
DIn
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7ARM University ProgramCopyright © ARM Ltd 2013ARM University ProgramCopyright © ARM Ltd 2013
Asynchronous Serial Communication
Eliminate the clock line!
Transmitter and receiver must generate clock locally
Transmitter must add start bit (always same value) to indicate start of
each data frame Receiver detects leading edge of start bit, then uses it as a timing
reference for sampling data line to extract each data bit N at timeTbit∗∗∗∗(N+1.5)
Stop bit is also used to detect some timing errors
T b i t * 1 . 5
Databits
Data Sampling
Time at Receiver T
b i t * 2 . 5
T b i t * 3 . 5
T b i t * 4 . 5
T b i t * 5 . 5
T b i t * 6 . 5
T b i t * 7 . 5
T b i t * 8 . 5
T b i t * 9 . 5
T b i t * 1 0
. 5
T i m eZ
er o
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8ARM University ProgramCopyright © ARM Ltd 2013ARM University ProgramCopyright © ARM Ltd 2013
Serial Communication Specifics
Data frame fields Start bit (one bit) Data (LSB first or
MSB, and size – 7, 8, 9 bits)
Optional parity bit isused to make totalnumber of ones in data even or odd
Stop bit (one or two bits)
All devices must use the same communications parameters
E.g. communication speed: baud rate (300, 600, 1200, 2400, 9600, 14400,19200, 38400, 57600, 115200 bits/second)
Sophisticated network protocols have more information in eachdata frame Medium access control – when multiple nodes are on bus, they must
arbitrate for permission to transmit Addressing information – for which node is this message intended? Larger data payload Stronger error detection or error correction information Request for immediate response (“in-frame”)
Message
Databits
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Error Detection
Can send additional information to verify data was receivedcorrectly
Need to specify which parity to expect: even, odd or none.
Parity bit is set so that total number of “1” bits in data and parity iseven (for even parity) or odd (for odd parity)
01110111 has 6 “1” bits, so parity bit will be 1 for odd parity, 0 for evenparity
01100111 has 5 “1” bits, so parity bit will be 0 for odd parity, 1 for evenparity
Single parity bit detects if 1, 3, 5, 7 or 9 bits are corrupted, butdoesn’t detect an even number of corrupted bits
Stronger error detection codes (e.g. CRC - Cyclic RedundancyCheck) exist and use multiple bits (e.g. 8, 16), and can detect manymore corruptions.
Used for CAN, USB, Ethernet, Bluetooth, etc.
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10ARM University ProgramCopyright © ARM Ltd 2013ARM University ProgramCopyright © ARM Ltd 2013
Solution to Noise: Higher Voltages
Use higher voltages to improvenoise margin:+3 to +15 V, -3 to -15 V
Example IC (Maxim MAX3232) usescharge pumps to generate highervoltages from 3.3V supply rail
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11ARM University ProgramCopyright © ARM Ltd 2013ARM University ProgramCopyright © ARM Ltd 2013
ASCII communication with PC
Today USB-Serial converter isused to install COM device on a
PC
ASCII codes send as data by a
microcontroller to PC One data frame is one character
ASCII data can be viewed on anyterminal software program
e.g. HyperTerminal, Putty, etc.
Some programms can displaydata as binary also
e.g. RealTerm
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12ARM University ProgramCopyright © ARM Ltd 2013ARM University ProgramCopyright © ARM Ltd 2013
Tools for Serial Communications Development
Tedious and slow to debug serialprotocols with just an oscilloscope
Instead use a logic analyzer to decodebus traffic
Analog Discovery Logic Analyzer Plugs into PC’s USB port
Decodes UART, SPI, I2C
Use terminal software to sniff serialcommunication data e.g. ‘RealTerm’
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SIMPLE COMMUNICATION
DEVICES
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Simple low speed device
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Simple device explained The simple communication device occupies four locations in the system
memory space (starts with IO_BASE_ADDR location)
Registers are: Input Data, Output Data, Status, and Control
READY flag is used internally to recognize that a new data was sent by the
processor READY is set when processor writes to Output Data (OData) register
READY is cleared when peripheral reads OData
READY flag is unreadable by the processor
As long as the peripheral is processing/sending data, the BUSY flag in Statusregister is active
Processor can check Status register to suspend a new data
To check BUSY flag, a processor reads Status register and masks BUSY flag
Additionally CONTROL register can be used to set the peripheraltransmisson parameters (e.g. the baud rate)
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Software Structure
Communication is asynchronous to program
Don’t know what code the program will be executing …
when the next item arrives
when current outgoing item completes transmission
when an error occurs
Need to synchronize between program and serial communication interfacesomehow
Options
Polling
Wait until data is available
Simple but inefficient of processor time
Interrupt
CPU interrupts program when data is available
Efficient, but more complex
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17ARM University ProgramCopyright © ARM Ltd 2013ARM University ProgramCopyright © ARM Ltd 2013
Controlling IO device
The process can periodically check the status of an I/O device todetermine the need for service
To check if device data register is empty/full
This method is called POLLING
This is the simplest way for an I/O device programming.
The processor is totally in control and does all the work.
But processor may read the Status register many times, only to
find that the device has not yet completed a comparatively slowI/O operation
This leads to overhead in communication
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Polling for data send operation
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Advanced control of IO device
A system can use interrupts to control peripherals
Interrupt-driven I/O scheme employs interrupts to indicate to theprocessor that an I/O device needs attention.
It is used by almost all systems
I/O interrupt is asynchronous with respect to the instructionexecution
An interrupt mechanism eliminates the need for the processor topoll the device and instead allows the processor to focus onexecuting programs
Device is programmed by a CPU to generate an interrupt in acertain events
e,g, data is ready in receive buffer, transmit buffer is empty, anerror occured
To eliminate too frequent interrupt events, IO communicationdevice can use internal data buffering
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Buffering Data in Device
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Interrupt Driven Communication Example
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22ARM University ProgramCopyright © ARM Ltd 2013ARM University ProgramCopyright © ARM Ltd 2013
SOFTWARE DATA BUFFERING
FOR HANDLING ASYNCHRONOUSCOMMUNICATION
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23ARM University ProgramCopyright © ARM Ltd 2013ARM University ProgramCopyright © ARM Ltd 2013
Serial Communications and Interrupts
Want to provide multiple softwaremodules in the program
Main program (and subroutines it calls)
Transmit ISR – executes when serialinterface is ready to send anothercharacter
Receive ISR – executes when serialinterface receives a character
Error ISR(s) – execute if an error occurs
Need a way of software bufferinginformation between soft modules
Solution: circular queue with head andtail pointers
One for tx, one for rx
SerialInterface
tx_isr rx_isr
get_stringsend_string
Main Program orother threads
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24ARM University ProgramCopyright © ARM Ltd 2013ARM University ProgramCopyright © ARM Ltd 2013
Enabling and Connecting Interrupts to ISRs
ARM Cortex-M0+provides one IRQ for allof a communicationinterface’s events
Within ISR (IRQ Handler),need to determine whattriggered the interrupt,and then service it
void UART2_void UART2_void UART2_void UART2_IRQHandlerIRQHandlerIRQHandlerIRQHandler()()()() {{{{
if (if (if (if (transmitter readytransmitter readytransmitter readytransmitter ready) {) {) {) {
if (more data to send) {if (more data to send) {if (more data to send) {if (more data to send) {
get next byteget next byteget next byteget next bytesend it out transmittersend it out transmittersend it out transmittersend it out transmitter
if (if (if (if (re!eived datare!eived datare!eived datare!eived data) {) {) {) {get byte from re!eiverget byte from re!eiverget byte from re!eiverget byte from re!eiver
save itsave itsave itsave it
if (if (if (if (error o!!urrederror o!!urrederror o!!urrederror o!!urred) {) {) {) {
"andle error"andle error"andle error"andle error
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25ARM University ProgramCopyright © ARM Ltd 2013ARM University ProgramCopyright © ARM Ltd 2013
Code to Implement Queues
Enqueue at tail: tail_ptr points to next freeentry
Dequeue from head: head_ptr points to item to
remove
#define the queue size (Q_SIZE) to make it easyto change
One queue per direction
tx ISR unloads tx_q
rx ISR loads rx_q
‘Main’ routine load tx_q and unload rx_q
Need to wrap pointer at end of buffer to make itcircular,
Use % (modulus, remainder) operator if queue size is not
power of two Use & (bitwise and) if queue size is a power of two
Queue is empty if size == 0
Queue is full if size == Q_SIZE
write data
to tail
read data
from head
olderdata
newerdata
SerialInterface
tx_isr rx_isr
get_stringsend_string
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Defining the Queues
#define Q_$I%& ('2)#define Q_$I%& ('2)#define Q_$I%& ('2)#define Q_$I%& ('2)
tyedef stru!ttyedef stru!ttyedef stru!ttyedef stru!t {{{{
unsigned !"ar ata*Q_$I%&+,unsigned !"ar ata*Q_$I%&+,unsigned !"ar ata*Q_$I%&+,unsigned !"ar ata*Q_$I%&+,unsignedunsignedunsignedunsigned intintintint Head,Head,Head,Head, -- oints to oldest data element
unsignedunsignedunsignedunsigned intintintint Tail,Tail,Tail,Tail, -- oints to next free sa!e
unsignedunsignedunsignedunsigned intintintint $i.e,$i.e,$i.e,$i.e, -- /uantity of elements in /ueue
Q_T, Q_T, Q_T, Q_T,
Q_TQ_TQ_TQ_T txtxtxtx_/0 rx_/,_/0 rx_/,_/0 rx_/,_/0 rx_/,
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27ARM University ProgramCopyright © ARM Ltd 2013ARM University ProgramCopyright © ARM Ltd 2013
Initialization and Status Inquiries
void Q_Init(Q_T 1 /) {void Q_Init(Q_T 1 /) {void Q_Init(Q_T 1 /) {void Q_Init(Q_T 1 /) {
unsignedunsignedunsignedunsigned intintintint i,i,i,i,
for (i3, i4Q_$I%&, i55)for (i3, i4Q_$I%&, i55)for (i3, i4Q_$I%&, i55)for (i3, i4Q_$I%&, i55)
////66667ata*i+ 3,7ata*i+ 3,7ata*i+ 3,7ata*i+ 3, -- to simlify our lives 8"en debugging
////66667Head 3,7Head 3,7Head 3,7Head 3,////66667Tail 3,7Tail 3,7Tail 3,7Tail 3,
////66667$i.e 3,7$i.e 3,7$i.e 3,7$i.e 3,
intintintint Q_&mty(Q_T 1 /) {Q_&mty(Q_T 1 /) {Q_&mty(Q_T 1 /) {Q_&mty(Q_T 1 /) {
return /return /return /return /66667$i.e 3,7$i.e 3,7$i.e 3,7$i.e 3,
intintintint Q_9ull(Q_T 1 /) {Q_9ull(Q_T 1 /) {Q_9ull(Q_T 1 /) {Q_9ull(Q_T 1 /) {
return /return /return /return /66667$i.e Q_$I%&,7$i.e Q_$I%&,7$i.e Q_$I%&,7$i.e Q_$I%&,
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28ARM University ProgramCopyright © ARM Ltd 2013ARM University ProgramCopyright © ARM Ltd 2013
Enqueue and Dequeue
intintintint Q_Q_Q_Q_&n/ueue&n/ueue&n/ueue&n/ueue(Q_T 1 /0 unsigned !"ar d) {(Q_T 1 /0 unsigned !"ar d) {(Q_T 1 /0 unsigned !"ar d) {(Q_T 1 /0 unsigned !"ar d) {
if (:Q_9ull(/)) {if (:Q_9ull(/)) {if (:Q_9ull(/)) {if (:Q_9ull(/)) { -- ;"at if /ueue is full<////66667ata*/7ata*/7ata*/7ata*/66667Tail55+ d,7Tail55+ d,7Tail55+ d,7Tail55+ d,////66667Tail = Q_$I%&,7Tail = Q_$I%&,7Tail = Q_$I%&,7Tail = Q_$I%&, -->ust 8ra !ir!ular buffer
////66667$i.e55,7$i.e55,7$i.e55,7$i.e55,return ?,return ?,return ?,return ?, -- su!!ess else else else else
return 3,return 3,return 3,return 3, -- failure
unsigned !"ar Q_unsigned !"ar Q_unsigned !"ar Q_unsigned !"ar Q_e/ueuee/ueuee/ueuee/ueue(Q_T 1 /) {(Q_T 1 /) {(Q_T 1 /) {(Q_T 1 /) {
unsigned !"ar t3,unsigned !"ar t3,unsigned !"ar t3,unsigned !"ar t3,if (:Q_&mty(/)) {if (:Q_&mty(/)) {if (:Q_&mty(/)) {if (:Q_&mty(/)) { -- >ust !"e!@ to see if /ueue is emtyt /t /t /t /66667ata*/7ata*/7ata*/7ata*/66667Head+,7Head+,7Head+,7Head+,////66667ata*/7ata*/7ata*/7ata*/66667Head55+ 3, -- to simlify debugging7Head55+ 3, -- to simlify debugging7Head55+ 3, -- to simlify debugging7Head55+ 3, -- to simlify debugging////66667Head = Q_$I%&,7Head = Q_$I%&,7Head = Q_$I%&,7Head = Q_$I%&, --;ra !ir!ular buffer////66667$i.e7$i.e7$i.e7$i.e66666666,,,,
return t,return t,return t,return t,
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Using the Queues
Sending data:
if (:Q_9ull(if (:Q_9ull(if (:Q_9ull(if (:Q_9ull()) {)) {)) {)) {
Q_Q_Q_Q_&n/ueue&n/ueue&n/ueue&n/ueue((((0 !)0 !)0 !)0 !)
Receiving data:
ifififif (:Q_&mty((:Q_&mty((:Q_&mty((:Q_&mty()) {)) {)) {)) {
!Q_!Q_!Q_!Q_e/ueuee/ueuee/ueuee/ueue(((())))
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ASYNCHRONOUS SERIAL
(UART) COMMUNICATIONS
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Transmitter Basics
If no data to send, keep sending 1 (stop bit) – idle line
When there is a data word to send Send a 0 (start bit) to indicate the start of a word
Send each data bit in the word (use a shift register for the transmitbuffer )
Send a 1 (stop bit) to indicate the end of the word
T b i t
Databits
Data Sampling
Time at ReceiverT i m eZ e
r o
T b i t
T b i t
T b i t
T b i t
T b i t
T b i t
T b i t
T b i t
T b i t
T b i t
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Receiver Basics
Wait for a falling edge (beginning of a Start bit) Then wait ½ bit time
Do the following for as many data bits in the word Wait 1 bit time
Read the data bit and shift it into a receive buffer (shift register)
Wait 1 bit time
Read the bit if 1 (Stop bit), then OK
if 0, there’s a problem!
T b i t * 1 . 5
Databits
Data SamplingTime at Receiver
T b i t * 2 . 5
T b i t * 3 . 5
T b i t * 4 . 5
T b i t * 5 . 5
T b i t * 6 . 5
T b i t * 7 . 5
T b i t * 8 . 5
T b i t * 9 . 5
T b i t * 1 0 . 5
T i m eZ er o
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For this to work…
Transmitter and receiver must agree on several things (protocol) Order of data bits
Number of data bits
What a start bit is (1 or 0)
What a stop bit is (1 or 0)
How long a bit lasts
Transmitter and receiver clocks must be reasonably close, since the onlytiming reference is the start of the start bit
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KL25 UARTs
UART: Universal (configurable) Asynchronous Receiver/Transmitter
UART0
Low Power
Can oversample from 4x to 32x
UART1, UART2
UART T i
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UART Transmitter
UART R i
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UART Receiver
I t D t O li
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Input Data Oversampling
When receiving, UART oversamples incoming data line
Extra samples allow voting, improving noise immunity
Better synchronization to incoming data, improving noise immunity
UART0 provides configurable oversampling from 4x to 32x
Put desired oversampling factor minus one into UART0 Control Register 4,OSR bits.
UART1, UART2 have fixed 16x oversampling
B d R t G t
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Baud Rate Generator
Need to divide module clock frequency down to desired baud rate *oversampling factor
Example
24 MHz -> 4800 baud with 16x oversampling
Division factor = 24E6/(4800*16) = 312.5. Must round to closest integer value (312 or 313), will have a slight frequency error.
Using the UART
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Using the UART
When can we transmit? Transmit buffer must be empty
Can poll UARTx->S1 TDRE flag
Or we can use an interrupt, in
which case we will need to queueup data
Put data to be sent into
UARTx_D(UARTx->D in with CMSIS)
When can we receive a byte? Receive buffer must be full
Can poll UARTx->S1 RDRF flag
Or we can use an interrupt, and
again we will need to queue thedata
Get data from UARTx_D
(UARTx->D in with CMSIS)
Software for Polled Serial Comm
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Software for Polled Serial Comm.void Init_UART2(uint'2_t baud_rate) {void Init_UART2(uint'2_t baud_rate) {void Init_UART2(uint'2_t baud_rate) {void Init_UART2(uint'2_t baud_rate) {
uint'2_t divisor,uint'2_t divisor,uint'2_t divisor,uint'2_t divisor,-- enable !lo!@ to UART and Bort A$I>$I>$I>$I>66667$CDCE F $I>_$CDCE_UART2_>A$G,7$CDCE F $I>_$CDCE_UART2_>A$G,7$CDCE F $I>_$CDCE_UART2_>A$G,7$CDCE F $I>_$CDCE_UART2_>A$G,$I>$I>$I>$I>66667$CDC F $I>_$CDC_BRT&_>A$G,7$CDC F $I>_$CDC_BRT&_>A$G,7$CDC F $I>_$CDC_BRT&_>A$G,7$CDC F $I>_$CDC_BRT&_>A$G,
-- !onne!t UART to ins for BT&220 BT&2'BRT&BRT&BRT&BRT&66667BCR*22+ BRT_BCR_>UJ(E),7BCR*22+ BRT_BCR_>UJ(E),7BCR*22+ BRT_BCR_>UJ(E),7BCR*22+ BRT_BCR_>UJ(E),BRT&BRT&BRT&BRT&66667BCR*2'+ BRT_BCR_>UJ(E),7BCR*2'+ BRT_BCR_>UJ(E),7BCR*2'+ BRT_BCR_>UJ(E),7BCR*2'+ BRT_BCR_>UJ(E),-- ensure tx and rx are disabled before !onfigurationUART2UART2UART2UART266667C2 K L(UARTMB_C2_T&_>A$G F UARTMB_C2_R&_>A$G),7C2 K L(UARTMB_C2_T&_>A$G F UARTMB_C2_R&_>A$G),7C2 K L(UARTMB_C2_T&_>A$G F UARTMB_C2_R&_>A$G),7C2 K L(UARTMB_C2_T&_>A$G F UARTMB_C2_R&_>A$G),
-- $et baud rate to EN33 bauddivisor OU$_CMCG-(baud_rate1?P),divisor OU$_CMCG-(baud_rate1?P),divisor OU$_CMCG-(baud_rate1?P),divisor OU$_CMCG-(baud_rate1?P),UART2UART2UART2UART266667OH UART_OH_$OR(divisor77N),7OH UART_OH_$OR(divisor77N),7OH UART_OH_$OR(divisor77N),7OH UART_OH_$OR(divisor77N),UART2UART2UART2UART266667OM UART_OM_$OR(divisor7OM UART_OM_$OR(divisor7OM UART_OM_$OR(divisor7OM UART_OM_$OR(divisor),),),),
-- o arity0 N bits0 t8o sto bits0 ot"er settings,UART2UART2UART2UART266667C? 7C? 7C? 7C? UART2UART2UART2UART266667$2 7$2 7$2 7$2 UART2UART2UART2UART266667C' 37C' 37C' 37C' 3,,,,
-- &nable transmitter and re!eiverUART2UART2UART2UART266667C2 UART_C2_T&_>A$G F UART_C2_R&_>A$G7C2 UART_C2_T&_>A$G F UART_C2_R&_>A$G7C2 UART_C2_T&_>A$G F UART_C2_R&_>A$G7C2 UART_C2_T&_>A$G F UART_C2_R&_>A$G,,,,
Software for Polled Serial Comm
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41ARM University ProgramCopyright © ARM Ltd 2013ARM University ProgramCopyright © ARM Ltd 2013
Software for Polled Serial Comm.
void UART2_Transmit_Boll(uintN_t data)void UART2_Transmit_Boll(uintN_t data)void UART2_Transmit_Boll(uintN_t data)void UART2_Transmit_Boll(uintN_t data) {{{{-- 8ait until transmit data register is emty
8"ile8"ile8"ile8"ile (:(UART2(:(UART2(:(UART2(:(UART266667$? K UART_$?_TR&_>A$G)),7$? K UART_$?_TR&_>A$G)),7$? K UART_$?_TR&_>A$G)),7$? K UART_$?_TR&_>A$G)),
UART2UART2UART2UART266667 data,7 data,7 data,7 data,
uintN_t UART2_Re!eive_Boll(void)uintN_t UART2_Re!eive_Boll(void)uintN_t UART2_Re!eive_Boll(void)uintN_t UART2_Re!eive_Boll(void) {{{{
-- 8ait until re!eive data register is full
8"ile8"ile8"ile8"ile (:(UART2(:(UART2(:(UART2(:(UART266667$? K UART_$?_RR9_>A$G)),7$? K UART_$?_RR9_>A$G)),7$? K UART_$?_RR9_>A$G)),7$? K UART_$?_RR9_>A$G)),
returnreturnreturnreturn UART2UART2UART2UART266667,7,7,7,
Example Transmitter
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42ARM University ProgramCopyright © ARM Ltd 2013ARM University ProgramCopyright © ARM Ltd 2013
Example Transmitter
!"ar text*+!"ar text*+!"ar text*+!"ar text*+Hello 8orld SSSHello 8orld SSSHello 8orld SSSHello 8orld SSS,,,,
8"ile (?) {8"ile (?) {8"ile (?) {8"ile (?) {
for (!for (!for (!for (!3333, !4, !4, !4, !4strlenstrlenstrlenstrlen(text)(text)(text)(text), !55) {, !55) {, !55) {, !55) {
UART2_Transmit_Boll(UART2_Transmit_Boll(UART2_Transmit_Boll(UART2_Transmit_Boll(text*!+text*!+text*!+text*!+),),),),
Example Receiver: Display Data on LCD
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43ARM University ProgramCopyright © ARM Ltd 2013ARM University ProgramCopyright © ARM Ltd 2013
Example Receiver: Display Data on LCD
!ol!ol!ol!ol 3, 3, 3, 3,
8"ile (?) {8"ile (?) {8"ile (?) {8"ile (?) {
! UART2_Re!eive_Boll(),! UART2_Re!eive_Boll(),! UART2_Re!eive_Boll(),! UART2_Re!eive_Boll(),l!dl!dl!dl!d____ut!"arut!"arut!"arut!"ar(!(!(!(!0000 !ol!ol!ol!ol),),),),
!ol!ol!ol!ol55,55,55,55,
if (if (if (if (!ol!ol!ol!ol7777EEEE)))) !ol!ol!ol!ol 3, 3, 3, 3,
Software for Interrupt-Driven Serial Comm
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44ARM University ProgramCopyright © ARM Ltd 2013ARM University ProgramCopyright © ARM Ltd 2013
Software for Interrupt-Driven Serial Comm.
Use interrupts
First, initialize peripheral to generate interrupts
Second, create single ISR with three sections corresponding to causeof interrupt
Transmitter
Receiver
Error
Peripheral Initialization
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45ARM University ProgramCopyright © ARM Ltd 2013ARM University ProgramCopyright © ARM Ltd 2013
Peripheral Initialization
void Init_UART2(uint'2_t baud_rate) {void Init_UART2(uint'2_t baud_rate) {void Init_UART2(uint'2_t baud_rate) {void Init_UART2(uint'2_t baud_rate) {
IC_IC_IC_IC_$etBriority$etBriority$etBriority$etBriority(UART2_(UART2_(UART2_(UART2_IRQnIRQnIRQnIRQn0 ?2N),0 ?2N),0 ?2N),0 ?2N),
IC_IC_IC_IC_ClearBendingIRQClearBendingIRQClearBendingIRQClearBendingIRQ(UART2_(UART2_(UART2_(UART2_IRQnIRQnIRQnIRQn),),),),
IC_IC_IC_IC_&nableIRQ&nableIRQ&nableIRQ&nableIRQ(UART2_(UART2_(UART2_(UART2_IRQnIRQnIRQnIRQn),),),),
UART2UART2UART2UART266667C2 F UART_C2_TI&_>A$G F7C2 F UART_C2_TI&_>A$G F7C2 F UART_C2_TI&_>A$G F7C2 F UART_C2_TI&_>A$G F
UART_C2_RI&_>A$GUART_C2_RI&_>A$GUART_C2_RI&_>A$GUART_C2_RI&_>A$G,,,,UART2UART2UART2UART266667C2 F UART_C2_RI&_>A$G,7C2 F UART_C2_RI&_>A$G,7C2 F UART_C2_RI&_>A$G,7C2 F UART_C2_RI&_>A$G,
Q_Init(KQ_Init(KQ_Init(KQ_Init(KTxQTxQTxQTxQ),),),),
Q_Init(KQ_Init(KQ_Init(KQ_Init(KRxQRxQRxQRxQ),),),),
Interrupt Handler: Transmitter
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46ARM University ProgramCopyright © ARM Ltd 2013ARM University ProgramCopyright © ARM Ltd 2013
Interrupt Handler: Transmitter
void UART2_void UART2_void UART2_void UART2_IRQHandlerIRQHandlerIRQHandlerIRQHandler(void) {(void) {(void) {(void) {
IC_IC_IC_IC_ClearBendingIRQClearBendingIRQClearBendingIRQClearBendingIRQ(UART2_(UART2_(UART2_(UART2_IRQnIRQnIRQnIRQn),),),),
if (UART2if (UART2if (UART2if (UART266667$? K UART_$?_TR&_>A$G) {7$? K UART_$?_TR&_>A$G) {7$? K UART_$?_TR&_>A$G) {7$? K UART_$?_TR&_>A$G) {
-- !an send anot"er !"ara!ter-- !an send anot"er !"ara!ter-- !an send anot"er !"ara!ter-- !an send anot"er !"ara!ter
if (:Q_&mty(Kif (:Q_&mty(Kif (:Q_&mty(Kif (:Q_&mty(KTxQTxQTxQTxQ)) {)) {)) {)) {
UART2UART2UART2UART266667 Q_7 Q_7 Q_7 Q_e/ueuee/ueuee/ueuee/ueue(K(K(K(KTxQTxQTxQTxQ),),),), else { else { else { else {
-- /ueue is emty so disable-- /ueue is emty so disable-- /ueue is emty so disable-- /ueue is emty so disable txtxtxtx
UART2UART2UART2UART266667C2 K LUART_C2_TI&_>A$G,7C2 K LUART_C2_TI&_>A$G,7C2 K LUART_C2_TI&_>A$G,7C2 K LUART_C2_TI&_>A$G,
Interrupt Handler: Receiver
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47ARM University ProgramCopyright © ARM Ltd 2013ARM University ProgramCopyright © ARM Ltd 2013
Interrupt Handler: Receiver
void UART2_void UART2_void UART2_void UART2_IRQHandlerIRQHandlerIRQHandlerIRQHandler(void) {(void) {(void) {(void) {
if (UART2if (UART2if (UART2if (UART266667$? K UART_$?_RR9_>A$G) {7$? K UART_$?_RR9_>A$G) {7$? K UART_$?_RR9_>A$G) {7$? K UART_$?_RR9_>A$G) {
-- re!eived a !"ara!ter
if (:Q_9ull(Kif (:Q_9ull(Kif (:Q_9ull(Kif (:Q_9ull(KRxQRxQRxQRxQ)) {)) {)) {)) {
Q_Q_Q_Q_&n/ueue&n/ueue&n/ueue&n/ueue(K(K(K(KRxQRxQRxQRxQ0 UART20 UART20 UART20 UART266667),7),7),7),
else { else { else { else {
-- error 6 /ueue full8"ile (?),8"ile (?),8"ile (?),8"ile (?),
Interrupt Handler: Error Cases
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48ARM University ProgramCopyright © ARM Ltd 2013ARM University ProgramCopyright © ARM Ltd 2013
Interrupt Handler: Error Cases
void UART2_void UART2_void UART2_void UART2_IRQHandlerIRQHandlerIRQHandlerIRQHandler(void) {(void) {(void) {(void) {
if (UART2if (UART2if (UART2if (UART266667$? K (UART_$?_R_>A$G7$? K (UART_$?_R_>A$G7$? K (UART_$?_R_>A$G7$? K (UART_$?_R_>A$G FFFF
UART_$?_9_>A$GUART_$?_9_>A$GUART_$?_9_>A$GUART_$?_9_>A$G FFFF
UART_$?_9&_>A$G FUART_$?_9&_>A$G FUART_$?_9&_>A$G FUART_$?_9&_>A$G F
UART_$?_B9_>A$GUART_$?_B9_>A$GUART_$?_B9_>A$GUART_$?_B9_>A$G)) {)) {)) {)) {
-- "andle t"e error-- "andle t"e error-- "andle t"e error-- "andle t"e error
-- !lear t"e flag-- !lear t"e flag-- !lear t"e flag-- !lear t"e flag
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49ARM University ProgramCopyright © ARM Ltd 2013ARM University ProgramCopyright © ARM Ltd 2013
DIRECT MEMORY ACCESS
OVERVIEW
Transferring data with DMA
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50ARM University ProgramCopyright © ARM Ltd 2013ARM University ProgramCopyright © ARM Ltd 2013
Transferring data with DMA
For high-bandwidth devices, the transfers consist primarily of relatively largeblocks of data
overhead could still be intolerable, since it could consume a large fraction of theprocessor time
direct memory access (DMA) is a mechanism that provides the ability totransfer data directly to/from the memory without involving the processor
Provided by the device controller
Provided by the central DMA device
DMA device must be a bus master
Basic Concepts
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51ARM University ProgramCopyright © ARM Ltd 2013ARM University ProgramCopyright © ARM Ltd 2013
Basic Concepts
Special hardware to read datafrom a source and write it toa destination
Various configurable options
Number of data items to copy
Source and destination addresses canbe fixed or change (e.g. increment,decrement)
Size of data item When transfer starts
Operation
Initialization: Configure controller
Transfer: Data is copied
Termination: Channel indicates transfer has completed
Example System with DMA engine
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52ARM University ProgramCopyright © ARM Ltd 2013ARM University ProgramCopyright © ARM Ltd 2013
a p e Syste t e g e
Central or IO DMA engines are possible
DMA basics
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53ARM University ProgramCopyright © ARM Ltd 2013ARM University ProgramCopyright © ARM Ltd 2013
Direct memory access (DMA) is used in order to provide high-speedperipherals - memory and memory- memory data transfer.
Each DMA transfer must have Transfer Control Descriptor (TCD) assigned
TCD consist of
SAR – Source Address Register, DAR - Destination Address Register, DSR -Status Register, BCR -Byte Count Register
DMA controller can provide multiple channels and it can service multiplesources / stereams
Each channel has seperate TDC
Channels have different priority
Each peripheral is connected to DMA module using separate stream
Each channel request can be selected among possible stream requests
Central DMA structure example
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54ARM University ProgramCopyright © ARM Ltd 2013ARM University ProgramCopyright © ARM Ltd 2013
p
DMA Status and Control flags
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55ARM University ProgramCopyright © ARM Ltd 2013ARM University ProgramCopyright © ARM Ltd 2013
g
DMA procedure
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56ARM University ProgramCopyright © ARM Ltd 2013ARM University ProgramCopyright © ARM Ltd 2013
p
The processor sets up the DMA by supplying: the identity of the device,
the operation to perform on the device,
the memory address that is the source or destination of the data to be transferred,
and the number of bytes to transfer
The DMA starts the operation on the device and arbitrates for the bus.
DMA unit can complete an entire transfer, which may be thousands of bytes inlength, without bothering the processor
Once the DMA transfer is complete, the controller interrupts the processor
Transfer Requests
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57ARM University ProgramCopyright © ARM Ltd 2013ARM University ProgramCopyright © ARM Ltd 2013
The DMA channel supports software-initiated or peripheral-initiated requests. A software request is issued by setting DCR:START
Peripheral request are initiated by asserting DMA Request (DREQ) signal whenDCR:ERQ is set. Setting DCR:ERQ enables recognition of the peripheral DMA.
The hardware can be programmed to automatically clear DCR:ERQ, disablingthe peripheral request, when BCR reaches zero.
Cycle-steal and continuous modes
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58ARM University ProgramCopyright © ARM Ltd 2013ARM University ProgramCopyright © ARM Ltd 2013
Cycle-steal mode (DCR:CS = 1) Only one complete transfer from source to destination occurs for each request.
Continuous mode (DCR:CS = 0)
After a software-initiated or peripheral request, the DMA continuously transfers datauntil BCR reaches zero.
The DMA performs the specified number of transfers, then retires the channel.
Channel prioritization
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59ARM University ProgramCopyright © ARM Ltd 2013ARM University ProgramCopyright © ARM Ltd 2013
Many DMA channels can be prioritized based on number, with channel 0having the highest priority and the last channel having the lowest priority.
Another scenario can assume the priority register to allow a programmers toset channel priorities according their need.
Priorities between DMA stream requests are software-programmable (e.g. 4 levels
consisting of very high, high, medium, low) or hardware in case of equality (request0 has priority over request 1, etc.)
DMA termination
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60ARM University ProgramCopyright © ARM Ltd 2013ARM University ProgramCopyright © ARM Ltd 2013
Interrupt If DCR:EINT is set, the DMA drives the appropriate interrupt request signal. The
processor can read DSR to determine whether the transfer terminated successfullyor with an error.
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61ARM University ProgramCopyright © ARM Ltd 2013ARM University ProgramCopyright © ARM Ltd 2013
DMA MULTIPEXER AND
MODULE IN KINETIS L
DMA Controller Features
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62ARM University ProgramCopyright © ARM Ltd 2013ARM University ProgramCopyright © ARM Ltd 2013
4 independent channels Channel 0 has highest priority
8-, 16- or 32-bit transfers, data size can differ between source anddestination
Modulo addressable
Can trigger with hardware signal or software
Can run continuously or periodically (“cycle-stealing”)
Hardware acknowledge/done signal
Kinetis L family Crossbar Switch
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63ARM University ProgramCopyright © ARM Ltd 2013ARM University ProgramCopyright © ARM Ltd 2013
DMA request multiplexer
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64ARM University ProgramCopyright © ARM Ltd 2013ARM University ProgramCopyright © ARM Ltd 2013
The direct memory access multiplexer (DMAMUX) routes DMA sources,called slots, to any of the four DMA channels
allows up to 63 DMA request signals
Kinteis L DMA Controller
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65ARM University ProgramCopyright © ARM Ltd 2013ARM University ProgramCopyright © ARM Ltd 2013
Registers
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66ARM University ProgramCopyright © ARM Ltd 2013ARM University ProgramCopyright © ARM Ltd 2013
DMA_SARn Source address register,
Valid values 0 to 0x000f ffff
DMA_DARn Destination address register
Valid values 0 to 0x000f ffff
Status Register/Byte Count Register DMA_DSR_BCRn
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67ARM University ProgramCopyright © ARM Ltd 2013ARM University ProgramCopyright © ARM Ltd 2013
Status flags: 1 indicates error
CE: Configuration error
BES: Bus error on source
BED: Bus error on destination
REQ: A transfer request is pending (more transfers to perform)
BSY: DMA channel is busy DONE: Channel transfers have completed or an error occurred. Clear this bit in
an ISR.
Byte Count Register
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68ARM University ProgramCopyright © ARM Ltd 2013ARM University ProgramCopyright © ARM Ltd 2013
BCR: Bytes remaining to transfer
Decremented by 1, 2 or 4 after completing write (determined by
destination data size)
DMA Control Register (DMA_DCRn)
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69ARM University ProgramCopyright © ARM Ltd 2013ARM University ProgramCopyright © ARM Ltd 2013
EINT: Enable interrupt on transfer completion
ERQ: Enable peripheral request to start transfer
CS: Cycle steal
0: Greedy - DMA makes continuous transfers until BCR == 0
1: DMA shares bus, performs only one transfer per request
AA: Autoalign
DMA Control Register (DMA_DCRn)
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70ARM University ProgramCopyright © ARM Ltd 2013ARM University ProgramCopyright © ARM Ltd 2013
EADRQ – Enable asynchronous DMA requests when MCU is in Stopmode
SINC/DINC – Increment SAR/DAR (by 1,2 or 4 based on SSIZE/DSIZE)
SSIZE/DSIZE – Source/Destination data size.
Don’t need to match – controller will perform extra reads or writes as needed(e.g. read one word, write two bytes).
00: longword (32 bits) 01: byte (8 bits)
10: word (16 bits)
START – Write 1 to start transfer
DMA Control Register (DMA_DCRn)
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71ARM University ProgramCopyright © ARM Ltd 2013ARM University ProgramCopyright © ARM Ltd 2013
SMOD, DMOD – Source/Destination address modulo When non-zero, supports circular data buffer – address wraps around after 2n+3 bytes (16
bytes to 64 kilobytes)
When zero, circular buffer is disabled D_REQ: If 1, then when BCR reaches zero ERQ bit will be cleared
LINKCC: Enables this channel to trigger another channel 00: Disabled
01: Two stages: Link to channel LCH1 after each cycle-steal transfer
Link to channel LCH2 after BCR reaches 0
10: Link to channel LCH1 after each cycle-steal transfer
11: Link to channel LCH1 after BCR reaches 0
LCH1, LCH2: Values 00 to 11 specify linked DMA channel (0 to 3)
Basic Use of DMA
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72ARM University ProgramCopyright © ARM Ltd 2013ARM University ProgramCopyright © ARM Ltd 2013
Enable clock to DMA module (in SIM register SCGC7)
Initialize control registers
Load SARn with source address
Load DARn with destination address
Load BCRn with number of bytes to transfer
Clear DSRn[DONE]
Start transfer by setting DCRn[START]
Wait for end of transfer Interrupt generated if DCRn[EINT] is set (DMAn_IRQHandler)
Poll DSRn[DONE]
Demonstration: Memory Copy
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73ARM University ProgramCopyright © ARM Ltd 2013ARM University ProgramCopyright © ARM Ltd 2013
Software-triggered
void Copy_Longwords(uint32_t * source, uint32_t * dest, uint32_tcount)
Could use as a fast version of memcpy function, but need to handleall cases
Alignment of source and destination
Data size
Detecting overlapping buffers
Memory to memory DMA Initialization
####i l di l di l di l d tdi ttdi ttdi ttdi t """"
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74ARM University ProgramCopyright © ARM Ltd 2013ARM University ProgramCopyright © ARM Ltd 2013
####in!ludein!ludein!ludein!lude 4444stdintstdintstdintstdintS"7S"7S"7S"7
####in!ludein!ludein!ludein!lude 4>GM2%ES"74>GM2%ES"74>GM2%ES"74>GM2%ES"7
void Initvoid Initvoid Initvoid Init_>A_To__>A_To__>A_To__>A_To_CoyCoyCoyCoy((((voidvoidvoidvoid) {) {) {) {
$I>$I>$I>$I>66667$CDC F $I>_$CDC_>A_>A$G,7$CDC F $I>_$CDC_>A_>A$G,7$CDC F $I>_$CDC_>A_>A$G,7$CDC F $I>_$CDC_>A_>A$G,>A3>A3>A3>A366667>A*3+SCR 7>A*3+SCR 7>A*3+SCR 7>A*3+SCR >A_CR_$IC_>A$G F>A_CR_$IC_>A$G F>A_CR_$IC_>A$G F>A_CR_$IC_>A$G F
>A_CR_$$I%&(3) F>A_CR_$$I%&(3) F>A_CR_$$I%&(3) F>A_CR_$$I%&(3) F>A_CR_IC_>A$G F>A_CR_IC_>A$G F>A_CR_IC_>A$G F>A_CR_IC_>A$G F
>A_CR_$I%&(3),>A_CR_$I%&(3),>A_CR_$I%&(3),>A_CR_$I%&(3),-- $i.eV 3 long8ord0 ? byte0 2 8ord
Memory to memory copy using DMAvoid Coyvoid Coyvoid Coyvoid Coy Mong8ordsMong8ordsMong8ordsMong8ords(((( uint'2 t 1uint'2 t 1uint'2 t 1uint'2 t 1sour!esour!esour!esour!e
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75ARM University ProgramCopyright © ARM Ltd 2013ARM University ProgramCopyright © ARM Ltd 2013
void Coyvoid Coyvoid Coyvoid Coy____Mong8ordsMong8ordsMong8ordsMong8ords(((( uint'2_t 1uint'2_t 1uint'2_t 1uint'2_t 1sour!esour!esour!esour!e0000uint'2_t 1uint'2_t 1uint'2_t 1uint'2_t 1 destdestdestdest0000uint'2_tuint'2_tuint'2_tuint'2_t !ount!ount!ount!ount) {) {) {) {
-- initiali.e sour!e and destination ointers
>A3>A3>A3>A366667>A*3+S$AR >A_$AR_$AR((uint'2_t)7>A*3+S$AR >A_$AR_$AR((uint'2_t)7>A*3+S$AR >A_$AR_$AR((uint'2_t)7>A*3+S$AR >A_$AR_$AR((uint'2_t) sour!esour!esour!esour!e),),),),
>A3>A3>A3>A366667>A*3+SAR >A_AR_AR((uint'2_t)7>A*3+SAR >A_AR_AR((uint'2_t)7>A*3+SAR >A_AR_AR((uint'2_t)7>A*3+SAR >A_AR_AR((uint'2_t) destdestdestdest),),),),-- byte !ount
>A3>A3>A3>A366667>A*3+S$R_OCR >A_$R_OCR_OCR(7>A*3+S$R_OCR >A_$R_OCR_OCR(7>A*3+S$R_OCR >A_$R_OCR_OCR(7>A*3+S$R_OCR >A_$R_OCR_OCR(!ount!ount!ount!ount1E),1E),1E),1E),
-- verify done flag is !leared
>A3>A3>A3>A366667>A*3+S$R_OCR K L>A_$R_OCR_&_>A$G,7>A*3+S$R_OCR K L>A_$R_OCR_&_>A$G,7>A*3+S$R_OCR K L>A_$R_OCR_&_>A$G,7>A*3+S$R_OCR K L>A_$R_OCR_&_>A$G,
-- start transfer
>A3>A3>A3>A366667>A*3+SCR F >A_CR_$TART_>A$G,7>A*3+SCR F >A_CR_$TART_>A$G,7>A*3+SCR F >A_CR_$TART_>A$G,7>A*3+SCR F >A_CR_$TART_>A$G,
-- 8ait until it is done
8"ile8"ile8"ile8"ile (:(>A3(:(>A3(:(>A3(:(>A366667>A*3+S$R_OCR K >A_$R_OCR_&_>A$G))7>A*3+S$R_OCR K >A_$R_OCR_&_>A$G))7>A*3+S$R_OCR K >A_$R_OCR_&_>A$G))7>A*3+S$R_OCR K >A_$R_OCR_&_>A$G))
,,,,
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