r 644-mhz sdr lvds トランスミッタ...
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XAPP622 (v1.7) 2004 4 27 www.xilinx.co.jp 1
2003 Xilinx, Inc. All rights reserved. Xilinx http://www.xilinx.co.jp/legal.htm
: Xilinx Xilinx Xilinx
1 16 17 (LVDS) 644 MHz (SDR) Virtex-II Virtex-II Pro Virtex-II Virtex-II Pro 12 Virtex-II XC2V3000-FF1152 -5 EDIF Verilog
SDR 1 / 1 500 Mb/s 500 MHz SDR LVDS XSBI (10 16
SDR Virtex-II (DCM) (420 MHz) Virtex-II AC DCM SDR
2 Virtex-II SDR SDR Virtex-II SDR LVDS LVPECL 2 SDR (QDR) Virtex-II SDR
: Virtex-II
XAPP622 (v1.7) 2004 4 27
644-MHz SDR LVDS /R
1 : SDR
word_0DATA
CLK
word_1 word_2 word_3
x622_01_043002
http://www.xilinx.co.jp/http:www.xilinx.com/legal.htmhttp://www.xilinx.co.jp/legal.htmhttp://www.xilinx.co.jp/legal.htm
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2 www.xilinx.co.jp XAPP622 (v1.7) 2004 4 27
Virtex-II R
Virtex-II
3 TX_CLOCK TX_SDR_16D_4TO1 RX_SDR_16D_4TO1 3 Vietex-II SDR
Virtex-II FPGA RX_SDR_16D_4TO1 TX_SDR_16D_4TO1 TX_CLOCK
TX_CLOCK High SDR 2 (REFCLK) (QDR) /
2 : SDR x622_02_051002
Virtex-II DeviceDevice
withSDR
CLK
DATA
CLK
DATA
Reference Clock
REFCLK_P
REFCLK_N
3 : Virtex-II SDR
RX_SDR_16D_4TO1
IBUFDS_LVDS_DIFF
TX_SDR_16D_4TO1TX_CLOCK
CLK_qdr
Design DataLogic Path
REFCLK_NREFCLK_P
RXP_clkRXN_clk
RXP_dataRXN_data
TXP_clkTXN_clk
TXP_dataTXN_data
x622_03_050503
http://www.xilinx.co.jp
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Virtex-II
XAPP622 (v1.7) 2004 4 27 www.xilinx.co.jp 3
R
TX_CLOCK 5% IBUFDS_DIFF_OUT ( 4) High High Low High 2 DCM ( 5) 1 TX_CLOCK
1 : TX_CLOCK
I/O
REFCLK_PREFCLK_N
IBUFDS_F_DIFF SDR
RST High
CLK_sdr_pCLK_sdr_n
High SDR
High SDR
CLK_qdr High QDR
4 : IBUFDS_DIFF_OUT
5 : TX_CLOCK
x622_04_101703
I
IB
O
OB
IBUFDS_DIFF_OUT
x622_05_051402
CLKINCLKFB
PSCLKPSENPSINCDEC
RST
CLK0CLK90
CLK180CLK270CLKDVCLK2X
CLK2X180
LOCKEDPSDONE
LOCKRST
BUFG
BUFG
DCM
CLK_sdr_n
CLK_sdr_p
CLK_qdr
BUFGREFCLK_N
REFCLK_P
REFCLKNREFCLKP
TX_CLOCK
http://www.xilinx.co.jp
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4 www.xilinx.co.jp XAPP622 (v1.7) 2004 4 27
Virtex-II R
2 High SDR DCM QDR Virtex-II DCM (CLKIN) DCM DCM CLKIN_DIVIDE_BY_2 TRUE SDR AC DCM 6
4:1 (TX_SDR_16D_4TO1) (TX_SDR_16D_4TO1) OUTSTAGE_DATA OUTSTAGE_CLK 2 2 TX_SDR_16D_4TO1
7 High SDR OUTSTAGE_CLK IOB CLK_sdr_p CLK_sdr_n
6 : TX_CLOCK
2 : TX_SDR_16D_4TO1
I/O
64 LSW MSW
CLK_sdr_pCLK_sdr_n
High SDR
High SDR
CLK_qdr High QDR RST High
TXP_dataTXN_data
16
TXP_clkTXN_clk
TXP_clk TXN_clk
x622_06_051302
REFCLK_P
REFCLK_N
CLK_sdr_p
CLK_sdr_n
CLK_qdr
http://www.xilinx.co.jp
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Virtex-II
XAPP622 (v1.7) 2004 4 27 www.xilinx.co.jp 5
R
(OUTSTAGE_DATA) (OUTSTAGE_DATA) ( 8) 4:1 QDR 4 4 3
QDR SDR OUTSTAGE_DAT 2 9 QDR SDR
7 : TX_SDR_16D_4TO1
8 : OUTSTAGE_DATA
3 : OUTSTAGE_DATA
I/O
CLK_qdr High QDR CLK_sdr High SDR
TXP TXN LVDS ( )
x622_07_051002
OUTSTAGE_D15
OUTSTAGE_CLK
OUTSTAGE_D0
DATA
CLK_sdr_pRST
CLK_sdr_n
CLK_qdr
TXN_data
TXP_data
TXP_clkTXN_clk
DATA
CLK_qdr
CLK_sdr
TXP
TXN
x622_08_051002
http://www.xilinx.co.jp
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6 www.xilinx.co.jp XAPP622 (v1.7) 2004 4 27
Virtex-II R
RLOC_ORIGIN
2 3 OUTSTAGE_DATA IOB 2 CLB CLB 3 RLOC_ORIGIN UCF
INST "U_tx/OUTSTAGE_D1 RLOC_ORIGIN = X108Y66 ;NET "TXP_data LOC = U8;NET "TXN_data LOC = U9;INST "U_tx/OUTSTAGE_D2 RLOC_ORIGIN = X108Y68;NET "TXP_data LOC = U6;NET "TXN_data LOC = T6;
9 : OUTSTAGE_DATA
10 : OUTSTAGE_DATA
1TXP
CLK_sdr
CLK_qdr
2 3 0
Next WordLast Word
x622_09_051302
x622_10_051002
MU
LT18
X18
_X5Y
10
RA
MB
16_X
5Y10
X108
Y67
Y66
Y69
Y68
Y67
Y66
Y69
Y68
U9
U8
U2
U1
T6
U6
TXN_data
TXP_data
TXN_data
TXP_data
N/C
N/C
X109 X110 X111
http://www.xilinx.co.jp
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Virtex-II
XAPP622 (v1.7) 2004 4 27 www.xilinx.co.jp 7
R
(OUTSTAGE_CLK) (OUTSTAGE_CLK) SDR ( 11) D0 1 D1 0 DDR 4
4:1 (RX_SDR_16D_4TO1) (RX_SDR_16D_4TO1) (HSRX_16D_4TO1) FIFO 5 12 HSRX FIFO
11 : OUTSTAGE_CLK
4 : OUTSTAGE_CLK
I/O
CLK_sdr_p High SDR
CLK_sdr_n High SDR
TXP TXN LVDS
5 :
I/O
RXP_dataRXN_data
16
REFCLK SDR RX_sync SYSCLK FIFO
RE High FIFO RST High
DATA SYSCLK FIFO 64
BUFSTAT FIFO READY High
CLK_qdr QDR
D0D1C0C1CERS
Q
FDDRRSE
CLK_sdr_nCLK_sdr_p
TXP
TXN
x622_11_050902
http://www.xilinx.co.jp
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8 www.xilinx.co.jp XAPP622 (v1.7) 2004 4 27
Virtex-II R
HSRX_16D_4TO1 DCM 2 HSRX_16D_4TO1 REFCLK RX_sync 13 REFCLK RX_sync SDR RXP_clk RXN_clk DCM SDR SDR REFCLK SDR
14 REFCLK RX_sync SDR RXP_clk RXN_clk RX DCM SDR SDR
15 2
HSRX_16D_4TO1 HSRX_16D_4TO1
12 : HSRX_16D_4TO1
13 : REFCLK
14 :
RXP_dataRXN_data
REFCLK
RX_sync
DATA
SYSCLK
BUFSTAT
READY
CLK_qdrRE
RST
x622_12_051002
x622_13_051402
RX_SDR_16D_4TO1
RXP_data DATA
READYBUFSTAT
CLK_qdr
RXN_dataREFCLK
RX_syncSYSCLK
RE
RST
RXN_clkRXP_clk
REFCLKP
x622_14_051402
RX_SDR_16D_4TO1
RXP_data DATA
READYBUFSTAT
CLK_qdr
RXN_dataREFCLK
RX_syncSYSCLK
RE
RST
RXN_clkRXP_clk
http://www.xilinx.co.jp
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Virtex-II
XAPP622 (v1.7) 2004 4 27 www.xilinx.co.jp 9
R
LVDS FIFO ()
CLK_qdr CLK_qdr (BUFG)
FIFO ( BUFSTAT = 1101) ( : BUFSTAT = 0010) SYSCLK CLK_qdr FIFO Verilog
//// RX FIFO control logic//always @ (posedge SYSCLK)begin if (RST_i == 1b1 || BUFSTAT < 4b0010 ) READ_ENABLE = 1b0; else if (READY == 1b1 && BUFSTAT == 4b1101 ) READ_ENABLE = 1b1;end
(HSRX_16D_4TO1)16 (HSRX_16D_4TO1) 16 (QDR_REG) 1 (CLKGEN)
6 16 HSRX
15 : x622_15_051402
HSRX_16D_4TO1 FIFO
RXP_data DATA DATA DATA
BUFSTATWCLK
RCLK
RE
RST
WCLK
CLK_qdr
RXN_dataREFCLK
RX_syncSYSCLK
RST
RE
READY
CLK_qdr
READY
http://www.xilinx.co.jp
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10 www.xilinx.co.jp XAPP622 (v1.7) 2004 4 27
Virtex-II R
(QDR_REG) IOB DDR DDR SDR 4:1 DDR SDR (CLK_ddr) CLK_ddr SDR
6 : HSRX
I/O
RXP_dataRXN_data
LVDS
REFCLK SDR
RX_sync
SYSCLK
DATA
WCLK FIFO REFCLK
READY High ready
CLK_qdr QDR
16 : HSRX_16D_4TO1 x622_16_051402
QDR_D15
QDR_D14
QDR_D13
QDR_D12
CLKGEN
QDR_D3
QDR_D2
QDR_D1
QDR_D0
RXP_dataRXN_data
RX_syncREFCLK
DATA
WCLKRST
READYCLK_qdr
http://www.xilinx.co.jp
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Virtex-II
XAPP622 (v1.7) 2004 4 27 www.xilinx.co.jp 11
R
17 7
6 7 QDR_REG IOB 2 CLB 2 CLB RLOC_ORIGIN 18 XC2V3000-FF1152 2 UCF
INST "U_rx/QDR_D8 RLOC_ORIGIN = X0Y80;NET "RXP_data LOC = N30;NET "RXN_data LOC = P30;INST "U_rx/QDR_D9 RLOC_ORIGIN = X0Y82;NET "RXP_data LOC = R25;NET "RXN_data LOC = P25;
17 : QDR_REG
7 : QDR_REG
I/O
RXPRXN
LVDS
CLK_ddr DDR
CE_rCE_f
Q
RXPRXN
Q
CE_rCE_f
CLK_ddr
x622_17_051002
http://www.xilinx.co.jp
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12 www.xilinx.co.jp XAPP622 (v1.7) 2004 4 27
Virtex-II R
(CLKGEN) Virtex-II DCM CLKGEN 19 8
18 :
19 : CLKGEN
MU
LT18
X18
_X0Y
10
RA
M16
_X0Y
10
Y81
Y80
Y83
Y82
Y81
Y80
Y83
Y82
P30
N30
N/C
N/C
P25
R25
RXN_data
RXP_data
RXN_data
RXP_data
M34
L34
x622_18_101703
X0 X1 X2 X3 X4 X5
REFCLKRX_sync
SYSCLK
CLK_ddrCE_rCE_f
WCLKCLK_qdrREADY
CLKGEN
RST
x622_19_051302
http://www.xilinx.co.jp
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Virtex-II
XAPP622 (v1.7) 2004 4 27 www.xilinx.co.jp 13
R
20 CLKGEN DCM CLKIN_DIVIDE_BY_2 SDR DCM (CLK0) BUFG DDR RX_sync IOB DDR CLK_ddr DDR
21 RX_sync REFCLK 3 CLK_ddr RX_sync SDR 2 CLKGEN DCM REFCLK
DCM RX_sync DDR DDR 0 (ps_count) (zero_end) (ones_start)
96 SDR 75% (ps_compare) (zero_end + ones_start)/2 - 64 96 0 (ps_compare) (ones_start + zero_end)/2
8 : CLKGEN
I/O
REFCLK SDR RX_sync
RST SYSCLK
CLK_ddr 1/2 CLK_qdr 1/4
CE_r, CE_f DDR WCLK FIFO READY High ready
http://www.xilinx.co.jp
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14 www.xilinx.co.jp XAPP622 (v1.7) 2004 4 27
Virtex-II R
(ps_compare) ps_compare
20 : CLKGEN
21 :
BUFG
CLKRSTLOCKEDPS_DONE
SYNC1SYNC0
CLKINCLKFB
RST
PS_CLKPS_ENPS_INCDEC
CLK0CLK2XCLKDV
LOCKEDPS_DONE
DCM
RST
PS_CLKPS_EN
PS_INCDECPS_LOCK
CLK_ddr
READY
RX_sync
REFCLK
IOB
IOB
CLK_qdr
x622_20_051002
RX_sync
REFCLK
CLK_ddr
1 0 1 0 1 0 1 0
RX_data Word_0 Word_1 Word_2 Word_3
x622_21_042403
http://www.xilinx.co.jp
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Virtex-II
XAPP622 (v1.7) 2004 4 27 www.xilinx.co.jp 15
R
FIFO (FIFO) 512 x 64 FIFO (BUFSTAT) FIFO 16 64
High RST 22 FIFO 23 FIFO 10
FIFO ( BUFSTAT = 1101) ( : BUFSTAT = 0010) SYSCLK CLK_qdr FIFO Verilog
//// RX FIFO control logic//always @ (posedge SYSCLK)begin if (RST_i == 1b1 || BUFSTAT < 4b0010 ) READ_ENABLE = 1b0; else if (READY == 1b1 && BUFSTAT == 4b1101 ) READ_ENABLE = 1b1;end
FIFO 1 SelectRAM 4
RX_data FIFOBLK0RX_data FIFOBLK1RX_data FIFOBLK2RX_data FIFOBLK3
SelectRAM NCF LOC IOB 18
INST U_fifo/FIFOBLK1 LOC = RAMB16_X0Y10;
22 : FIFO
WDATA
WCLK
RCLKRERST
RDATA
BUFSTAT
x622_22_050902
http://www.xilinx.co.jp
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16 www.xilinx.co.jp XAPP622 (v1.7) 2004 4 27
Virtex-II R
FULL_MT 24 Full/Empty FULL_MT (WCLK) 25 FULL_MT 10
23 : FIFO
CE
RST
WCLK
WRADDR
C
RST
Q
CE
C
RST
QWADDR
FULL_MT
WDATA
RADDR
RCLK
BUFSTATBUFSTAT
RDADDR
RCLKRE
x622_23_050902
WEB
ENBCLKBADDRBDIB
WEA
ENACLKAADDRADIA
DOA
DOBRDATA
9 : FIFO
I/O
WDATA
WCLK CLK
RCLK CLK ( )
RE High
RST High FIFO
RDATA
BUFSTAT
24 : FULL_MT
WADDRRADDR
RCLK
BUFSTAT
RST
x622_24_051002
http://www.xilinx.co.jp
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PCB
XAPP622 (v1.7) 2004 4 27 www.xilinx.co.jp 17
R
PCB
PCB DCM PCB XAPP233
500 MHz 2% TXP TXN 26 0.1 F 1 K AC DC PCB LVDS
Verilog EDIF FTP
http://www.xilinx.co.jp/bvdocs/appnotes/xapp622.zip
readme.txt
25 : FULL_MT
10 : FULL_MT
I/O
WADDR 4
RADDR 4
RCLK CLK
RST
BUFSTAT
DIFF_S1 DIFF_S2Q
WADDR
RADDR
RCLK
EQ
x622_25_061802
26 : AC DC
SDR Receiver
100
1K Clock
Data
Virtex-IIFPGA
x622_26_051002
100
0.1 F
http://www.xilinx.com/bvdocs/appnotes/xapp233.pdfhttp://www.xilinx.co.jphttp://www.xilinx.com/bvdocs/appnotes/xapp622.zip
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18 www.xilinx.co.jp XAPP622 (v1.7) 2004 4 27
R
Virtex-II Virtex-II Pro 16 LVDS Virtex-II 644 MHz Virtex-II Pro 700 MHz 12
A (IBUFDS_DIFF_OUT) IBUFDS_DIFF_OUT
LVDS 11
2 2 (BUFG) BUFG
FF896 4 LVDS
Verilog IBUFDS_DIFF_OUT IB_refclk (.I( REFCLKP ), .IB( REFCLKN ), .O( REFCLK_in_p ), .OB(REFCLK_in_n ));BUFG BG_sdr_p ( .I( REFCLK_in_p ) , .O( CLK_sdr_p ) );BUFG BG_sdr_n ( .I( REFCLK_in_n ) , .O( CLK_sdr_n ) );
Verilog 11 UCF
INST IB_refclk/IBUFDS LOC = AE15; # This constraint uses input pins AE15 and AD15, where AE15 is + LVDS pinINST BG_sdr_p LOC = BUFGMUX2P; # This constraint is for the positive output of the primitiveINST BG_sdr_n LOC = BUFGMUX3S; # This constraint is for the negative output of the primitive
11 : Virtex-II
: Pos* Neg : Pos* Neg
BUFGMUX (By Pin Pair) Pos* Neg
FF896 Bank 0 G16* H16 6S* 7P
C16* C17 4S* 5P
Bank 1 C14* C15 2S* 3P
F14* F15 0S* 1P
Bank 4 AE15* AD15 2P* 3S
AH15* AH14 0P* 1S
Bank 5 AH17* AH16 6P* 7S
AD16* AE16 4P* 5S
http://www.xilinx.co.jp
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A
XAPP622 (v1.7) 2004 4 27 www.xilinx.co.jp 19
R
FF1152 Bank 0 J18* K18 6S* 7P
E18* E19 4S* 5P
Bank 1 E16* E17 2S* 3P
H16* H17 0S* 1P
Bank 4 AG17* AF17 2P* 3S
AK17* AK16 0P* 1S
Bank 5 AK19* AK18 6P* 7S
AF18* AG18 4P* 5S
FF1517 Bank 0 J20* H20 6S* 7P
D21* C21 4S* 5P
Bank 1 F20* F19 2S* 3P
H18* H19 0S* 1P
Bank 4 AM20* AL20 2P* 3S
AT19* AU19 0P* 1S
Bank 5 AP20* AP21 6P* 7S
AN22* AN21 4P* 5S
BF957 Bank 0 E16* E17 6S* 7P
A17* A18 4S* 5P
Bank 1 C15* C16 2S* 3P
H15* H16 0S* 1P
Bank 4 AL15* AL14 2P* 3S
AJ15* AH15 0P* 1S
Bank 5 AH17* AJ16 6P* 7S
AD17* AD16 4P* 5S :
1. * LVDS
11 : Virtex-II (Continued)
: Pos* Neg : Pos* Neg
BUFGMUX (By Pin Pair) Pos* Neg
http://www.xilinx.co.jp
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20 www.xilinx.co.jp XAPP622 (v1.7) 2004 4 27
A R
SFI-4 XSBI Virtex-II Virtex-II Pro SFI-4 Implementation Agreement revision 1.0 IEEE P802.3ae draft 4.1 XSBI Virtex-II Virtex-II Pro 12
13 14 Virtex-II
12 :
Virtex-II XC2V3000 -5, -6 644 MHz
Virtex-II Pro XC2VP50 -5 622 MHz
-6 644 MHz
-7 700 MHz
:
1. 8.2pF 10 FR4 LVDSEXT 85 -5%)
2. Virtex-II Virtex-II Pro I/O
13 : Virtex-II SFI-4 LVDS SDR TX
SFI-4 XSBI Virtex-II LVDS SDR
1/(622.08 MHz) 1/(644.53 MHz) 1/(622.08 MHz) for SFI-41/(644.53 MHz) for XSBI
= CLK
40/60 40/60 45/55
/ 1 20%-80% 100 - 250 ps 100 - 250 ps 400 ps
2 400 ps 400 ps 242 ps
: 1. Virtex-II SFI-4
Virtex-II SFI-4 2.
TX = (Jitter + TCKSSKEW + TPKGSKEW)
http://www.xilinx.co.jp
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XAPP622 (v1.7) 2004 4 27 www.xilinx.co.jp 21
R
14 : Virtex-II SFI-4 LVDS SDR RX
SFI-4 XSBI Virtex-II LVDS SDR
1/(622.08 MHz) 1/(644.53 MHz) 1/(622.08 MHz) for SFI-41/(644.53 MHz) XSBI
= CLK
45/55 45/55 45/55
/ 1 20%-80% 100 - 300 ps 100 - 300 ps 400 ps
2 Setup = 300 psHold = 300 ps
= 600ps
= 600 ps590 ps2
: 1. Virtex-II SFI-4
Virtex-II SFI-4 2.
RX = (TSAMP + TCKSKEW + TPKGSKEW). TSAMP 500 ps (Virtex-II ) TCKSSKEW 50 ps SDR 2 PCB 40 ps
2002/05/17 1.0 2002/05/30 1.1 2 2002/07/02 1.2 25 A 2003/05/05 1.3 2003/08/05 1.4 IBUFDS_LVDS_DIFF IBUFDS_DIFF_OUT 2003/11/05 1.5 12 18 2004/02/02 1.6 12 2004/04/27 1.7 11 CS144 FG256 FG456 FG676
BG575BG728 12 Verilog INST IB_refclk/IBUFDS LOC
http://www.xilinx.co.jp
644-MHz SDR LVDS /Virtex-II 4:1 (TX_SDR_16D_4TO1) (OUTSTAGE_DATA) (OUTSTAGE_CLK)4:1 (RX_SDR_16D_4TO1) (HSRX_16D_4TO1) (QDR_REG) (CLKGEN) FIFO (FIFO)FULL_MT
PCB A (IBUFDS_DIFF_OUT)Verilog
SFI-4 XSBI
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