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SSCP 3323 – Advanced Electronics
EXAMPLES Example 1 (h-parameter) The transistor circuit parameters of the amplifier shown in Figure 1 are RB = 226 kΩ, RC = 1.5 kΩ, RL = 2 kΩ and Rs = 500 Ω. The transistor used in the circuit has the following h-parameters: hie = 1.1 kΩ, hre = 6 x 10-4, hfe = 80 and hoe = 25 μA/V. Draw the amplifier equivalent circuit and calculate (a) Current gain, Ais = io/is (b) Voltage gain Avs = vo/vs (c) Input impedance, Zi = vi/is (d) Output impedance, Zo = vo/io
Vcc=12V RB RC C2
Rs
Vs C1 RL
Figure 1
Solution Steps to draw the equivalent circuit: i. Short all dc voltage source ii. Short all capacitors (valid in midband region only) iii. Replace the transistor symbol with an equivalent h-
parameter circuit. The resulting small-signal equivalent circuit of the amplifier is:
43
SSCP 3323 – Advanced Electronics
Rs hie i1 hfei1 i2 is iovs RB v1 hrev2 hfe 1/hoe v2 RC RL
Figure 2 - Small-signal equivalent circuit
(a) Calculation of current gain
⎟⎟⎠
⎞⎜⎜⎝
⎛⎟⎟⎠
⎞⎜⎜⎝
⎛==
s
o
s
ois i
iii
iiA 1
1
Also,
⎟⎟⎠
⎞⎜⎜⎝
⎛⎟⎟⎠
⎞⎜⎜⎝
⎛=
1
2
21 ii
ii
ii oo
So, Ais can be written as
⎟⎟⎠
⎞⎜⎜⎝
⎛⎟⎟⎠
⎞⎜⎜⎝
⎛⎟⎟⎠
⎞⎜⎜⎝
⎛==
s
o
s
ois i
iii
ii
iiA 1
1
2
2
But, it has been proof that Loe
feZh
hii
+=
11
2
ZL is the parallel combination of RC and RL, i.e.
857.085720001500
)2000)(1500(// =Ω=+
=+
==LC
LCLCL RR
RRRRZ
44
SSCP 3323 – Advanced Electronics
So, 3.7885710251
801 61
2 =××+
=+
=−Loe
feZh
hii
At the output stage, i2 divides into currents flow in RC and RL.
i2 io
RC RL
Figure 3 – The output stage
Applying the current division rule at the output stage gives
)( 2iRRRi
LC
Co −
+=
So, 4285.025.1
5.12
−=+
−=
iio
The equivalent circuit at the input stage is
Rs i1 hie
is Vs RB hre
Zi Figure 4 – The input stage
45
SSCP 3323 – Advanced Electronics
Applying the current division rule at the input stage gives
siB
B iZR
Ri+
=1
So, iB
B
s ZRR
ii
+=1
Zi for the transistor is
Ω=×+
×−=
+−=
−
−k 058.1
)85)(1025(1)857.0)(80)(106(1.1
1 6
4
Loe
Lfereiei Zh
ZhhhZ
So, 995.0k 226 k 1.058
k) 226(1 =+
=+
=iB
B
s ZRR
ii
Therefore, current gain,
4.33)995.0)(3.78)(4285.0(1
1
2
2−=−=⎟⎟
⎠
⎞⎜⎜⎝
⎛⎟⎟⎠
⎞⎜⎜⎝
⎛⎟⎟⎠
⎞⎜⎜⎝
⎛==
s
o
s
ois i
iii
ii
iiA
(b) Calculation of voltage gain
Voltage gain, ⎟⎟⎠
⎞⎜⎜⎝
⎛=⎟⎟
⎠
⎞⎜⎜⎝
⎛⎟⎟⎠
⎞⎜⎜⎝
⎛=⎟⎟⎠
⎞⎜⎜⎝
⎛⎟⎟⎠
⎞⎜⎜⎝
⎛==
sv
ss
o
s
ovs v
vAvv
vv
vv
vv
vvA 11
1
21
1
where vo = v2 and Av = v2/v1. Av is the voltage gain of the transistor and is given as
46
SSCP 3323 – Advanced Electronics
i
LI
i
LLv Z
ZAZiZi
vvA ==≡
11
2
where Lo
fI Zh
hiiA
+−=−≡
11
2 and Lo
Lfrii Zh
ZhhhivZ
+−==
11
1
Thus,
34.63)857()]106)(80()1025)(1100[(1100
85780)(
46
−=×−×+
×−=
−+−
==
−−
Lrefeoeieie
Lfe
i
LIv Zhhhhh
ZhZZAA
To calculate v1/vs, consider the input stage of the amplifier
Rs
vs RB v1 Zi
Figure 5 – Voltage divider at the input stage
ssBi
Bi vRRZ
RZv ×+
=)//(
)//(1
where Ω=+
= 1054226001058
)22600)(1058(// Bi RZ
47
SSCP 3323 – Advanced Electronics
So, 678.05001054
1054)//(
)//(1 =+
=+
=sBi
Bi
s RRZRZ
vv
Therefore,
95.42)678.0)(4.63(1 −=−=⎟⎟⎠
⎞⎜⎜⎝
⎛==
sv
s
ovs v
vAvvA
(c) Calculation of input impedance Input impedance,
Ω===== 1054//)//(1iB
s
iBs
ssi
i ZRi
ZRiiv
ivZ
(d) Calculation of output impedance, Zo Output impedance is the impedance seen at the output terminal when the input is short circuit (vs = 0), as shown in the figure below:
Rs hie i1 hfei1 i2 iovs=0 RB v1 hrev2 hfe 1/hoe v2 RC RL vo
Figure 6 – Circuit used to calculate output impedance
48
SSCP 3323 – Advanced Electronics
Applying KVL to the input stage:
21])//[(0 vhihRR reieBs ++= gives
27
1 1075.3 vi −×−= Applying KVL to the output stage and substituting v2 = vo :
⎥⎦
⎤⎢⎣
⎡×−++=
⎥⎦
⎤⎢⎣
⎡×−++=
×−++=
++=−
−
−
−
)1075.3(801
)1075.3(801
)1075.3(
7
72
27
22
122
oeC
o
oeC
feoeC
feoeC
o
hR
v
hR
v
vhvhRv
ihvhRvi
Therefore,
Ω=×−+×+
−==−−
1511)1075.3(8010251500
176o
oo i
vZ
49
SSCP 3323 – Advanced Electronics
Example 2 (hybrid-π at mid-frequency range) Calculate the small-signal voltage gain of the bipolar transistor circuit shown in Figure 7. Assume the transistor circuit parameters are β = 100, VCC = 12 V, VBE = 0.7 V, RC = 6 kΩ, RB = 50 kΩ, and VBB = 1.2 V.
Figure 7
DC Solution
ARVV
IB
onBEBBBQ μ10
507.02.1)( =
−=
−=
so that
mA 1)10)(100( === AII BQCQ μβ Then
50
SSCP 3323 – Advanced Electronics
V6)6)(1(12 =−=−= CCQCCCEQ RIVV Therefore, the transistor is biased in the forward-active mode. AC Solution The small-signal hybrid-π parameters are
Ω=== k 6.21
)026.0)(100(CQ
TIVr β
π
and
mA / V 5.38026.01
===T
CQm V
Ig
The small-signal voltage gain is determined using the small-signal equivalent circuit shown below:
Figure 8
51
SSCP 3323 – Advanced Electronics
Cmceo RVgVV )( π−==
sB
VRr
rV ⎟⎟⎠
⎞⎜⎜⎝
⎛+
=π
ππ
The small-signal voltage gain is then
4.11 506.2
6.2)6)(5.38(
)(
−=
⎟⎠⎞
⎜⎝⎛
+−=
⎟⎟⎠
⎞⎜⎜⎝
⎛+
−==B
Cms
ov Rr
rRgVVA
π
π
52
SSCP 3323 – Advanced Electronics
Example 3 (hybrid-π at high-frequency range) Determine the 3dB frequency of the current gain for the circuit shown in Figure 9, both with and without the effect of Cμ. The circuit parameters are RC = RL = 4 kΩ, rπ = 2.6 kΩ, RB = rs//R1//R2 = 200 kΩ, Cπ = 4 pF, Cμ = 0.2 pF, and gm = 38.5 mA/V.
Figure 9
Solution The small-signal equivalent circuit with simplified hybrid-π model is shown in Figure 10.
Figure 10
53
SSCP 3323 – Advanced Electronics
The small-signal equivalent circuit, including the equivalent Miller capacitance is shown in Figure 11.
Figure 11
The output voltage is
)//( LCmo RRVgV π−= So, voltage gain is
)//( LCmo
i
ov RRg
VV
VVA −===
π
The Miller capacitance is
)]//(1[
))]//((1[
)1(
LCm
LCm
vM
RRgC
RRgC
ACC
+=
−−=
−=
μ
μ
μ
Applying current division rule at the output stage allows the output current to be written as
54
SSCP 3323 – Advanced Electronics
⎟⎟⎠
⎞⎜⎜⎝
⎛+
−=LC
Cmo RR
RVgI π
Also, the input voltage is
⎥⎦
⎤⎢⎣
⎡++
=
⎥⎦
⎤⎢⎣
⎡⎟⎟⎠
⎞⎜⎜⎝
⎛⎟⎟⎠
⎞⎜⎜⎝
⎛=
))(//(1//
1//1////
MB
Bs
MBs
CCrRjrRI
CjCjrRIV
ππ
π
πππ
ω
ωω
Therefore, the current gain is
⎥⎦
⎤⎢⎣
⎡++⎟⎟
⎠
⎞⎜⎜⎝
⎛+
−==))(//(1
//
MB
B
LC
Cm
s
oi CCrRj
rRRR
RgIIA
ππ
πω
The 3 dB frequency is
))(//(21
3MB
dB CCrRf
+=
πππ
Neglecting the effect of Cμ (CM = 0), we find that
MHz 5.15 )104()]106.2//()10[(2002
1
))(//(21
1233
3
=×××
=
+=
−π
π ππ MBdB CCrR
f
The Miller capacitance is
55
SSCP 3323 – Advanced Electronics
pF 6.15 )]4//4)(5.38(1)[2.0(
)]//(1[
=+=
+= LCmM RRgCC μ
Taking into account the Miller capacitance, the 3 dB frequency is
MHz 16.3 )10](6.154[)]106.2//()10[(2002
1
))(//(21
1233
3
=+××
=
+=
−π
π ππ MBdB CCrR
f
56
SSCP 3323 – ELEKTRONIK LANJUTAN SESI 2012/13 SEM 1 TUGASAN 1
Soalan 1
Lukis kan litar setara a.t. dan litar setara a.u. bagi litar-litar amplifier dalam Rajah 1(a) dan Rajah 1(b).
(a)
(b)
Rajah 1
Soalan 2 Lukiskan model hibrid bagi litar amplifier dalam Rajah 2.
+VCC
RL
vs
B
C
E
RB
vo
Rajah 2 Dengan menggunakan model itu dapatkan (i) persamaan input dan output, (ii) impedans input dan output, (iii) gandaan voltan, (iv) gandaan arus bagi litar amplifier itu.
SSCP 3323 – ELEKTRONIK LANJUTAN SESI 2012/13 SEM 1 TUGASAN 2 Soalan 1 Lukis model hibrid bagi litar CE dengan rintangan pemancar yang ditunjukkan dalam Rajah 3. Dengan menggunakan model hybrid itu, tentukan (i) impedans input litar (ii) impedans output litar (iii) gandaan voltan litar (iv) gandaan arus litar
+VCC
RL
vs
BC
E
RB
vo
RE
Rajah 3
1
Soalan 2 Lukis model hibrid bagi litar yang ditunjukkan dalam Rajah 4. Dengan menggunakan model hibrid litar itu, tentukan (i) impedans input litar (ii) impedans output litar (iii) gandaan voltan litar (iv) gandaan arus litar
+VCC
RC
vs
BC
E
R1
C1
C2
RER2 RL
2
1
SSCP 3323 – ELEKTRONIK LANJUTAN SESI 2013/14 SEM 1 ASSIGNMENT 3
Question 1
Figure 1 shows an RC-coupled two-stage cascade amplifier. For each stage, hie
= 1 k and hfe = 100. The values of hre, hoe and the biasing network can be neglected. If this amplifier is operated in its mid-band range, (a) draw the small signal model, and (b) calculate the voltage gain, of the amplifier.
+ VCC
R11
R12
RC1
RE
CE
C1
C2100 k 1 k
10 k
RS
1 k
R21
R22
100 k
10 k
RC2
RE
1 k
vO
vs
CE
Figure 1
2
Question 2 a) Describe the following parameter in a differential amplifier
(i) Common-mode gain (ii) Differential-mode gain (iii) Common mode rejection ratio (CMRR)
(b) For the circuit in Figure 2, the transistor parameters are =100, VA = and IQ = 2 mA. Determine the CMRR value of the diff-amp.
+15V
10K 10K
2K 2K V1 V2
5K
-15V
Figure 2
SSCP3323 Exercise 1 Sem I 2014/15
1. For the amplifier circuit shown in Figure 1,
h parameters for the transistor are hie =
11.4K, hfe = 200, hoe = 0, hre = 0. Draw the
ac equivalent circuit for the amplifier and
determine;
i) Ai = io/ii and Ais = io/is
ii) Av = vo/vi and Avs = vo/vs
iii) Zib = vi/ii and Zi = vi/is
iv) Zo = vo/io when vs = 0.
2. Draw the ac equivalent circuit for the amplifier shown in figure 2. With hie=1.0K,
hfe = 50 while hoe and hre can be ignored, determine the voltage gain, vo/vs and
input impedance, vi/is.
3. The parameters of the transistor in the circuit in Figure 3 are = 100, and VA =
.
a) Determine R1 and R2 to obtain a bias-stable circuit with the Q-point in the
center of the load line.
b) Determine the voltage gain, Av = vo/vs.
4. Consider the circuit shown in Figure 4. The transistor parameters are =100 and
VA=100V. Determine the input impedance Zi = vi/is, voltage gain Av = vo/vs and
current gain Ai = io/is.
vs
27K
15K
2.2K
1.2K
VCC=9V
Fig. 4
10K
is
vi
i0
2K
vo
R1
R2
RC=2K
RE=1K
+12V
Fig. 3
vs
vo
vs
100k
680
1k
VCC
Fig. 2
200
is
vi
ii
2k vo
195k
35k
6k
1k
VCC
Fig. 1
200
vs
is
vi
ii i0
10k vo
5. Referring to the circuit in Figure 5, parameters for transistor Q1 are hie = 1.43K
and hfe =100 and parameters for transistor Q2 are hie = 0.95K and hfe =100.
With hoe and hre can be ignored, find vo/vs and io/is.
6. For the circuit in Figure 6, the transistor has parameters of hie = 1.5K, hfe =
200, hoe = 25x10-6
S and hre = 2.5x10-5
. Estimate the current gain, io/ii, input
impedance, vi/is and overall voltage gain, vo/vs.
Fig.6
46K
9K
1.5K
470
VCC
150
vs
is
vi
ii
80
i0 vo
5 : 1
vs
620K
3.3K
VCC
1K
is Q1
io
2.2K
Q2
68K
220
50K
Fig. 5
10K
vo
SSP3323 Integrator and Differentiator
1
1) If the square wave, Vi is the input to the OPAM, draw the shape the output
voltage, Vo.
2) If the input voltage to the differential amplifier is shown in Figure 2, draw the
shape of the output voltage. Vi
5V 0 1 2 3 4 5 6 7 time, t (sec) -5V
1
SSCP 3323 – ELEKTRONIK LANJUTAN SESI 2013/14 SEM 1 ASSIGNMENT 4
Question 1
(a) Explain the term loading effect which occurs when two circuits or electronic equipments are connected together.
(b) State the condition for impedance matching between the two circuits or electronic equipments.
(c) Suggest a method to solve the problem of impedance mismatch using an operational amplifier.
Question 2 Figure 1 shows an operational amplifier circuit built to operate as an inverting amplifier.
+ V
- V
R2
R1
vi v
o
Figure 1
(a) If R1 = 1k , and R2 = 2 k , calculate the output voltage when (i) the input voltage is + 0.5 V (ii) the input voltage is – 1.0 V
(b) Given R1 = 1 k . Calculate the necessary value of R2 in order for the output to be ten times the input voltage.
(c) The gain is required to be fully variable between a minimum of -1 and a
maximum of -11. Suggest how this might be achieved, sketching a suitable circuit and calculating component values.
What restrictions are there for the input signal voltage when the amplifier is at maximum gain?
Name: I/C:
From Boolean expression :
YDCBADCBADCBA
DCBADCBADCBADCBADCBADCBA
=⋅⋅⋅+⋅⋅⋅+⋅⋅⋅
+⋅⋅⋅+⋅⋅⋅+⋅⋅⋅+⋅⋅⋅+⋅⋅⋅+⋅⋅⋅
(i) ii)
Draw logic circuit for the Boolean expression. Construct a truth table for the expression
D C B A Y D C B A Y 0 0 0 0 1 0 0 0 0 0 0 1 1 0 0 1 0 1 1 1 1 1 1 1 1
Name: I/C:
(iii) Simplify the expression using Karnaugh map 00 01 11 10 00 01 11 10
(iv) (iv)
Draw a circuit of the simplified Boolean expression using logic gates Draw circuit to solve this problem using 1-of-8 data selector
1
SSCP 3323 – ELEKTRONIK LANJUTAN SESI 2013/14 SEM 1 TUGASAN 5
1. Construct logic circuits using AND, OR and NOT gates for the following
minterm Boolean expressions:
(a) YBABA
(b) YCBACA
(c) YDCDBDA
2. Construct logic circuits using AND, OR and NOT gates for the following
Boolean expressions:
(a) YBABA )()(
(b) YCBA )(
(c) YCADCBA )()()(
3. (a) Using the truth table in Figure 1
for an electronic lock, write the minterm Boolean expression for this truth table
(b) From the Boolean expression developed in part (a), draw a logic symbol diagram for the electronic lock problem
Figure 1 4. Simplify the Boolean expression
YCBACBACBACBA
by (i) Plotting 1s on a three-variable Karnaugh map (ii) Looping groups of two or four 1s (iii) Eliminating variables whose complement appears within the loop(s) (iv) Writing the simplified minterm Boolean expression 5. Simplify the Boolean expression
YCBACBACBACBA
by (i) Plotting 1s on a three-variable Karnaugh map (ii) Looping groups of two or four 1s (iii) Eliminating variables whose complement appears within the loop(s) (iv) Writing the simplified minterm Boolean expression
INPUT SWITCHES OUTPUT
C B A Y
0 0 0 0
0 0 1 0
0 1 0 1
0 1 1 0
1 0 0 0
1 0 1 1
1 1 0 0
1 1 1 0
1
SSCP 3323 – ELEKTRONIK LANJUTAN SESI 2013/14 SEM 1 ASSIGNMENT 6
Question 1 Consider an oven along with the associated input and output signals, shown in Figure 1.
The operation of the oven is as follows:
(i) The heater (H) will be ON when the power switch (P) is ON, the door (D) is closed,
and the temperature (T) is below the limit.
(ii) The fans (F) will be turned ON when the heater (H) is ON or when the temperature
(T) is above the limit and the door (D) is closed
(iii) The light (L) will be turned ON if the light switch (S) is ON or whenever the door
(D) is opened
Write the Boolean expressions for the heater (H), the fans (F) and the light (L) which
govern the operation of the oven and construct the logic circuit to accomplish the
operation.
Figure 1
2
Question 2 Design a mod-10 ripple counter using NAND gates. Draw the circuit diagram of your design and explain how the counter works. Draw a table and the relevant timing diagram to illustrate the counting sequence. Simplify your design by using a 7493 IC, a 4-bit binary counter as shown in Figure 2.
Figure 2
Assignment - Digital SSP3323
1 a) Draw the circuit for the function YXYXF using
i. 2-input AND and OR gates, and a NOT.
ii. 2-input NAND gate only.
b) Prepare a truth table for the following Boolean expression, zyxF
c) Table 1 is a part of the truth table for a 2-bit comparator circuit. The input to
the comparator is number 2 bits, A = {A1, A0} and B = {B1, B0}. Comparator
output is G and L which will show whether the two numbers A and B is
greater or smaller. If A> B then G = 1 and if B> A then L = 1. If A = B then
G = L = 0.
i) Complete the truth table.
ii) Write the Boolean expression for G and L from the truth table.
iii) Simplify the expression for G and L using Karnaugh map
iii) Draw the logic circuit for the expression of G and L
Table 1
2). a) Explain the following flip-flops (Truth table, logic symbol and its
operation):
i) RS Flip-Flop
ii) D Flip-Flop
iii) JK Flip-Flop
A1 A0 B1 B0 G L
0 0 0 0 0 0
0 0 0 1 0
0 0 1 0 0
0 0 1 1 0 1
0 1 0 0 0
0 1 0 1 0 0
0 1 1 0 1
0 1 1 1 0
1 0 0 0 1 0
1 0 0 1 0
1 0 1 0 0
1 0 1 1 0
1 1 0 0 1 0
1 1 0 1 0
1 1 1 0 0
1 1 1 1 0 0
2-bit Comparator
A=A1A0 B=B1B0
G L
Assignment - Digital SSP3323
b) Sketch the waveform of the output Y against the input X of figure 2(a).
c) Explain the followings (Truth table, logic diagram and its operation):
i) Decade counter (Modulo 10 counter)
ii) Step down counter
d) Sketch the output waveforms, A, B and C after each clock pulse for the
shift register shown in Figure 2(b).
A
B
C
Figure 2(b)
Figure 2(a)
SSP3323
2
1) i) By using suitable flip-flops, draw a logic diagram of a mod-6 ripple up
counter.
ii) Figure 1 shows a logic diagram of a counter. Complete its counting sequence
in Table 1.
Figure 1
Number of
Pulse sequence
Binary counting
sequence
Decimal Count
C B A
0 1 1 1 7
1
2
3
4
5
6
7
9
9
10
11
Table 1.
2). (a) (i) Draw a logic symbol diagram of a 3 bits serial load shift-right register.
(ii) Explain how you would clear to 000 the 3-bit you drew in (i).
(iii) After clearing the 3-bit register, explain how you would enter 010 into
the register you drew in (i).
(iv) With the original output = 010 (A=0, B=1 and C=0), list the contents of
the register you drew in (i) after one, two and three clock pulses.
SSP3323
3
3). a) Describe the classification of shift registers.
b) Figure 2 shows the wiring diagram of a 4-bit parallel load recirculating
shift register. Table 2 shows the operation of this shift register. Complete
the values of output A, B, C and D.
Figure 2
Table 2
SSP3323
4
Input Output
A B S C
0 0
0 1
1 0
1 1
A + B Co
Input Output
A B D B
0 0
0 1
1 0
1 1
A - B Di Bo
4) a) Complete the truth tables for HA (Half Adder) and HS (Half Subtractor) in
Table 3 and draw their logic circuit using gates .
Table 3
b) Draw the full adder and Co outputs for each set of input pulses
shown in Figure 3.
Figure 3
Co
5. a) Figure 4 shows full-adders and XOR gates are connected to form an
arithmetic circuit. Study the circuit carefully and answer the following;
i) Complete the truth table of the full-adder below.
Input Output
Cin A B Co
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
SSP3323
5
ii) Complete the table below.
M B N
0 0
0 1
1 0
1 1
iii) For each input A, B and M given in the table below find the output W,
X, Y and Z.
Input Output
A3 A2 A1 A0 B3 B2 B1 B0 M W X Y Z
0 1 0 0 0 0 1 1 0
0 1 0 1 1 1 0 0 0
0 1 1 1 0 0 1 1 1
1 0 0 0 1 1 0 1 1
1 1 0 0 0 0 1 0 1
iv) Explain briefly the arithmetic function of the circuit in Figure 4.
b) Convert the following signed decimal numbers to their 4-bit 2s compliment
form:
+1, -1, +7, -7.
c) Do the binary addition, subtraction and multiplication problems below.
(i) 1010 + 0110 =
(ii) 0100 + 1010 =
(iii) 0110 – 0101 =
(iv) 1100 – 1011 =
(v) 110 × 111 =
(vi) 1100 × 1010 =
d) (i) Show a table of 2’s complement for all 4-bit positive and negative
numbers.
(ii) Calculate the sum of the 2’s complement number 0110 and 1001. Give
the answer in 2’s complement and decimal.
SSP3323
6
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Figure 4
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