verilog tutorial (structure, test) level showing the data flow between registers gate level...

Digital Circuit Design and Language

Verilog Tutorial(Structure, Test)

Chang, Ik JoonKyunghee University

Hierarchical Design

Top-down Design Methodology Bottom-up Design Methodology

Module

Example)→ END

→ START

Module (Example: Full Adder)

Module becomes a template for instantiation

Port Declaration and Assignment Rule

Input, Output and Inout declaration → can be regarded as wire To store data in output, the output port should be declared as ‘reg’

Abstraction Modeling Levels in Verilog Behavioral or Algorithmic Level Most upper level Similar to C language

Dataflow Level Showing the data flow between registers

Gate Level Describing Gate-to-Gate connection

Switch Level

RTL Level Design = Behavioral + Dataflow

Abstraction Modeling Levels in Verilog Behavioral or Algorithmic Level Most upper level Similar to C language

Dataflow Level Showing the data flow between registers

Gate Level Describing Gate-to-Gate connection

Switch Level

RTL Level Design = Behavioral + Dataflow

Gate Level Modeling

Built-in Primitive

Combinational logic Tri State MOS

GatesCMOS Gates

Bi-Directional Gates Pull Gates

and nand

ornorxor

xnorbufnot

bufif0bufif1notif0notif1

nmospmosrnmosrpmos

cmosrcmos

trantranif0tranif1rtran

rtranif0rtranif1

pulluppulldown

Built-in Primitive

User-Defined Primitive (UDP)primitive UDP_02467 (D, A, B, C);

output D;input A, B, C;// Truth table for D = f (A, B, C) = ??(0, 2, 4, 6, 7);table// A B C : D

0 0 0 : 1;0 0 1 : 0;0 1 0 : 1;0 1 1 : 0;1 0 0 : 1;1 0 1 : 0;1 1 0 : 1;1 1 1 : 1;

endtableendprimitive Truth table

UDP can be defined using a truth table

Example: Gate Level Modeling

- butif0 #(5) a1(out, i1, i2) // rising, falling and turn-off delay = 5- butif0 #(4, 6) a1(out, i1, i2) // rising=4, falling=6, turn-off=4- burif0 #(3,4,5) a1(out, i1, i2) // rising=4, falling=6, turn-off=5 - and #(4:5:6) a1(out, i1, i2) // min : typical : max delay = 4 : 5 : 6

Delay operator will be removed in logic synthesis For logic simulation, min/typical/max delay should be selected

Gate-level Example: 4-bit RCAmodule half_adder (output S, C, input x, y);

xor (S, x, y);and (C, x, y);

endmodule

module full_adder (output S, C, input x, y, z);wire S1, C1, C2;half_adder HA1 (S1, C1, x, y);half_adder HA2 (S, C2, S1, z);or G1 (C, C2, C1);

endmodule

module ripple_carry_4_bit_adder ( output [3: 0] Sum, output C4, input [3:0] A, B, input C0);wire C1, C2, C3; // Intermediate carries

// Instantiate chain of full addersfull_adder FA0 (Sum[0], C1, A[0], B[0], C0),

FA1 (Sum[1], C2, A[1], B[1], C1),FA2 (Sum[2], C3, A[2], B[2], C2),FA3 (Sum[3], C4, A[3], B[3], C3);

endmodule

Abstraction Modeling Levels in Verilog Behavioral or Algorithmic Level Most upper level Similar to C language

Dataflow Level Showing the data flow between registers

Gate Level Describing Gate-to-Gate connection

Switch Level

RTL Level Design = Behavioral + Dataflow

Dataflow Level Modeling Using Continuous Assignment or Operator Continuous Assignment

ex. assign #10 out = in1 & in2 //delay 10 t.u. for input change

Example: Dataflow Level Modeling// 4:1 Multiplexer using dataflow level modeling

module mux4_to_1 (out, in, sel);

// I/O port declarationoutput out; input [3:0] in; input [1:0] sel;

wire out; wire [3:0] in; wire [1:0] sel;

assign out = (~sel[1] & ~sel[0] & in[0]) | (~sel[1] & sel[0] & in[1]) | (sel[1] & ~sel[0] & in[2]) | (sel[1] & sel[0] & in[3])

endmodule

Abstraction Modeling Levels in Verilog Behavioral or Algorithmic Level Most upper level Similar to C language

Dataflow Level Showing the data flow between registers

Gate Level Describing Gate-to-Gate connection

Switch Level

RTL Level Design = Behavioral + Dataflow

Procedure What is procedure? Can be expressed in two types of statements: ‘initial’ or

‘always’ Every procedure is executed in parallel

‘initial’ statement They execute only once

‘always’ statement They execute forever until the simulation is completed

Module can contain any number of procedures

Procedure: ‘initial’ statement

Procedure: ‘always’ statement

Procedural Assignment

Example: Blocking vs. Non-blocking Assignment

always @ (posedge clock)a = b;

always @ (posedge clock)b = a;

What is the first?→ Race Condition

always @ (posedge clock)a <= b;

always @ (posedge clock)b <= a;

always @ (posedge clock)begin

temp_a = a;temp_b = b;a = temp_b;b = temp_a;

end

Timing Control: Delay-based (using ‘#’)

Example: Delay-based Timing ControlIn the following Verilog Code, tell the simulation time of (a), (b), (c), (d) and (e).

reg x, y, p, a, b, c, d;initial

beginx = 1’b0;#5 y = 1’b1; // (a)fork

#10 p = x; //(b)begin

#20 a = x; // (c)b = y; // (d)

endjoin

endinitial

#30 c = 1’b0; // (e)

Timing Control: Event-based (using ‘@’)

event OR control

regular event control (positive-edge)

regular event control (negative-edge)

What is ‘named event control’?

Timing Control: Level-sensitive (using ‘wait’)

alwayswait (count_table) #20 count = count + 1;

If count_table ==1, increase count by 20 t.u. else, no action

Procedural Statement: If

Procedural Statement: Case

Procedural Statement: For

Procedural Statement: While

Procedural Statement: Repeat

Procedural Statement: Forever

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Test Bench For Functional Verification

instantiation

Test bench : Applying stimulus to test HDL and observe its response

In the test module, no input and output

reg-inputs, wire-output

Test Bench for Functional Verification

2-to-1 Multiplexer

System Task

Display and Monitor String Format

HDL Example: D-Latch & D Flip-Flop

HDL Example: T and J-K Flip-Flop

T Flip-Flop using D Flip-Flop

J-K Flip-Flop using D Flip-Flop