An Effective DFM Strategy Requires Accurate Process and IP Pre-Characterization

An Effective DFM Strategy Requires Accurate Process and IP Pre-Characterization

Carlo Guardiani, Massimo Bertoletti, Carlo Guardiani, Massimo Bertoletti, Nicola Dragone, Marco Malcotti, and Nicola Dragone, Marco Malcotti, and Patrick McNamaraPatrick McNamaraPDF Solutions Inc.PDF Solutions Inc.

DAC 2005, Anaheim, CADAC 2005, Anaheim, CA

Technology Roadmap Challenges Technology Roadmap Challenges

65nm Lithography

OPC/PSM integr. w/

photo-window

Front-end/Transistor

Layout dependent

performance

Parametric variation

65nm Lithography

OPC/PSM integr. w/

photo-window

Front-end/Transistor

Layout dependent

performance

Parametric variation

45nm Lithography

Layout pattern

dependence

Immersion litho,

OPC/PSM integration

w/ photo window

Front end/Transistor

New gate/oxide

architectures

Reliability

45nm Lithography

Layout pattern

dependence

Immersion litho,

OPC/PSM integration

w/ photo window

Front end/Transistor

New gate/oxide

architectures

Reliability

90nm Back-end integration

Low-k

CMP

Product ramp issues

Yield vs.

performance

90nm Back-end integration

Low-k

CMP

Product ramp issues

Yield vs.

performance

Random defects are no longer the Random defects are no longer the dominant yield loss mechanismdominant yield loss mechanism– Yields are limited by design featuresYields are limited by design features

Yield Limiters by Technology Node

40%

50%

60%

70%

80%

90%

100%

Technology

Yie

ld

Random Defect Limited Yield

Design Feature Limited Yield

Total Yield

The Evolution of Product YieldsThe Evolution of Product Yields

From Reactive to Proactive DFM: A Copernican Revolution…From Reactive to Proactive DFM: A Copernican Revolution…

Accurate Yield Models Accurate Yield Models CharacterizedCharacterizedin Siliconin Silicon

Fully integrated in standard Fully integrated in standard design tools and flowsdesign tools and flows

Design rules guarantee yield!…Design rules guarantee yield!…well, not really…well, not really…

……then recommended rules then recommended rules ……and opportunistic design data and opportunistic design data

base post-processing to enforce base post-processing to enforce themthem

Yield Revolved Around Rules

Yield Models are the driving force in the DFM universe

Rule-based DFM?Rule-based DFM?

MUX4X1AFY_Y1 - 20 tracks

MUX4X1AFY_COY4 - 25 tracksMUX4X1AFY_PMSY4 - 21 tracks

MUX4X1AFY1_Y16 - 27 tracks

32 FPB32 FPB

19 FPB19 FPB

20 FPB20 FPB25 FPB25 FPB

Reactive vs. Proactive DFMReactive vs. Proactive DFM

DRM

Synthesis Place&route

DesignDesignDesignDesign

IP lib. Design

Floorplan

SPICE

DesignDesignDesignDesign VerificationVerificationVerificationVerification

VerificationVerificationVerificationVerification

Timing & SI

PhysicalFormal

DFM sign-offDFM

sign-off

DFM & ManufacturingDFM & ManufacturingDFM & ManufacturingDFM & Manufacturing

OPC/RET

Dummy Fill

MDP

DFM Optimizations

DFM Optimizations

Mask Making

DRM

Yield –awareSynthesis

Yield –awareSynthesis

Yield-aware Place&routeYield-aware Place&route

DesignDesignDesignDesign

IP lib. DesignIP lib. Design

Yield Aware Floorplan

Yield Aware Floorplan

SPICE

DesignDesignDesignDesign VerificationVerificationVerificationVerification

DFM & ManufacturingDFM & ManufacturingDFM & ManufacturingDFM & Manufacturing

OPC/RET

Dummy Fill

MDP

DFM TuningDFM

Tuning

Mask Making

Manufacturing FacilityManufacturing FacilityManufacturing FacilityManufacturing Facility

VerificationVerificationVerificationVerification

Statistical Timing & SIStatistical

Timing & SI

PhysicalFormal

DFM sign-offDFM

sign-off

Proactive DFMProactive DFM

Designer access to process data is limitedDesigner access to process data is limited– DFM today is Reactive DFM today is Reactive – Increased design cycle timeIncreased design cycle time– Risky design feature changesRisky design feature changes– Misaligned mask GDSII and design databaseMisaligned mask GDSII and design database

DFM needs to be ProactiveDFM needs to be Proactive– Up-front accurate process characterization Up-front accurate process characterization – Occurring early in the design flowOccurring early in the design flow– Model based IP characterizationModel based IP characterization– Manufacturable-by-constructionManufacturable-by-construction designs designs

Designer access to process data is limitedDesigner access to process data is limited– DFM today is Reactive DFM today is Reactive – Increased design cycle timeIncreased design cycle time– Risky design feature changesRisky design feature changes– Misaligned mask GDSII and design databaseMisaligned mask GDSII and design database

DFM needs to be ProactiveDFM needs to be Proactive– Up-front accurate process characterization Up-front accurate process characterization – Occurring early in the design flowOccurring early in the design flow– Model based IP characterizationModel based IP characterization– Manufacturable-by-constructionManufacturable-by-construction designs designs

DFM characterization Of IP librariesDFM characterization Of IP libraries

Characterize IP library for yield (.pdfm)Characterize IP library for yield (.pdfm)– Extract design attributes of yield modelsExtract design attributes of yield models– Include random, design systematic andInclude random, design systematic and

litho effectslitho effects New yield library view (.pdfm)New yield library view (.pdfm) Enable hierarchical large capacity DFM chip analysis Enable hierarchical large capacity DFM chip analysis

Library GDS

Process FR

(D0,)

Yield Extractions

Yield Extractions

Design Attributes

ACCACC

.pdfm

Library GDS

Process Margins and Litho calibration data

Lithography Simulator

Lithography Simulator

Library

YIMP

ACCACC.pdfm

Context Generation

Context Generation

Golden OPC/RET

Golden OPC/RET

RANDOM

Design SYSTEMATIC

Litho Process Window

Process Margin

0

0.2

0.4

0.6

0.8

1

1.2

0

0.02

0.04

0.06

0.08 0.

1

0.12

0.14

0.16

0.18 0.

2

Spacing

Yie

ld

0

0.05

0.1

0.15

0.2

0.25

0.3

p(s

pac

ing

)

Random Yield Loss: Physical MechanismsRandom Yield Loss: Physical Mechanisms

Contact and via opens due to formation Contact and via opens due to formation defectivitydefectivity

Active, poly and metal shorts and opens due Active, poly and metal shorts and opens due to particle defectsto particle defects

RandomRandomYield Loss MechanismsYield Loss MechanismsTypeType

Material Material opensopens

Material Material shortsshorts

Random Yield Loss: Test StructuresRandom Yield Loss: Test Structures

Extract Metal layer open Extract Metal layer open and short defectivityand short defectivity

Extract Metal layer open and Extract Metal layer open and short Defect Size Distribution short Defect Size Distribution (DSD)(DSD)

Systematic Yield Loss: Physical MechanismsSystematic Yield Loss: Physical Mechanisms

Misalignment, line-ends/bordersMisalignment, line-ends/borders

Contact/via opens due to local neighborhood Contact/via opens due to local neighborhood effects (e.g. pitch/hole size)effects (e.g. pitch/hole size)

Leakage from STI related stressLeakage from STI related stress

Impact of micro/macro loading design rule Impact of micro/macro loading design rule marginalitiesmarginalities

SystematiSystematicc

Yield Loss MechanismsYield Loss MechanismsTypeType

Failure Rate

020406080

100120140160

0.4 1.8 4.2 9

Pitch (um)

Via

Fai

lure

Rat

e (f

pb

)

Systematic Yield Loss: Test StructuresSystematic Yield Loss: Test Structures

Without Neighborhood With Neighborhood

STI

M1To Pad A To Pad B To Pad C

N+

PWL

N+ P+

Printability Yield Loss: Physical MechanismsPrintability Yield Loss: Physical Mechanisms

Material opensMaterial opens

Poor contact coverage due to misalignment and Poor contact coverage due to misalignment and defocus/pull backdefocus/pull back

SystematicSystematicYield Loss MechanismsYield Loss MechanismsTypeType

Poly/Metal shortsPoly/Metal shorts

Printability Yield Loss: ModelingPrintability Yield Loss: Modeling

Process Margin

0

0.2

0.4

0.6

0.8

1

1.2

0

0.02

0.04

0.06

0.08 0.

1

0.12

0.14

0.16

0.18 0.

2

Spacing

Yie

ld0

0.05

0.1

0.15

0.2

0.25

0.3

p(s

pac

ing

)

Layo

utLa

yout

Met

ricM

etric

MisalignmentMisalignment

Mask Error

Mask Error

Defocus

Defocus

ExposureExposure

Yield Loss

Defocus

0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

Misalignment

0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

- 3.0 s- 2.5 s

- 2.0 s- 1.5 s

- 1.0 s- 0.5 s

0.0 s0.5 s

1.0 s1.5 s

2.0 s2.5 s

3.0 s

Exposure

0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

coverage

The .pdfm ViewThe .pdfm View

Library characterized to Library characterized to generate generate manufacturability view manufacturability view (.pdfm)(.pdfm)– Random and design Random and design

systematic yieldsystematic yield– Litho process window Litho process window

Using calibrated yield Using calibrated yield modelsmodels

Multi-layer litho process Multi-layer litho process window incorporated window incorporated

Cell Cell CharacteristicCharacteristic

Library Library ViewView

Lay outLay out GDSGDS

SchematicSchematic SPICE SPICE NetlistNetlist

P&R FootprintP&R Footprint LEFLEF

PerformancePerformance .lib.lib

Logic FunctionLogic Function VerilogVerilog

PowerPower

Noise Noise …… ……

ManufacturabilitManufacturabilityy

..pDFMpDFM

Application: IP library DFM Quality AnalysisApplication: IP library DFM Quality Analysis

Yield sensitivity Yield sensitivity analysis analysis

Optimal design Optimal design depends on process depends on process cornercorner– Ex NAND2: Y5, Y6, Ex NAND2: Y5, Y6,

Y1, Y4Y1, Y4 Best becomes worst at Best becomes worst at

different process cornerdifferent process corner– Ex NAND2: Ex NAND2:

Y1_m1opens vs. Y1_m1opens vs. Y1_m1shortsY1_m1shorts

DFM Sensitivity DFM Sensitivity depends on layout depends on layout attributes attributes – M1 more sensitive M1 more sensitive

than Polythan Poly Identify redundant Identify redundant

layout implementationslayout implementations– Ex AOI: Y4, Y5Ex AOI: Y4, Y5

Dominant Process Effect

COAO3BTC2NOR2XC_R2

-6

-4

-2

0

2

4

6

8

10

Process Corner

Cel

l F

R I

mp

rove

men

t (p

pb

)

orig

Y1

Y2

Y3

Y4

Y5

Y6

Poly Open Poly Short M1 Open M1 Short

NAND2 CELL

COAO3BTC2SDFFQXC_R2

-2

0

2

4

6

8

10

12

Process Corner

Cel

l F

R I

mp

rove

men

t (p

pb

)

orig

Y1

Y2

Y3

Y4

Y5

Y6

Process CornerPoly Open Poly Short M1 Open M1 Short

AOI CELL

Yield aware synthesys and place&route Yield aware synthesys and place&route

Proactive DFMProactive DFM Maximize manufacturability by constructionMaximize manufacturability by construction

RTL Design

Hierarchical Floorplan

Physical Synthesis

Chip Assembly

Sign-off

VER

IFIC

ATI

ON

ModelsYield Gap Estimator

Yield Optimizer Extended IP

Yield ModelsYield Estimation

Yield Optimization

DFM SW plug-ins Yield View (.pdfm)

DFM LIBRARIES

Standard Libraries

ConclusionsConclusions

Impact of design systematic and lithography Impact of design systematic and lithography yield loss mechanisms crossed over random yield loss mechanisms crossed over random phenomenaphenomena

Rule-based, reactive DFM is impracticalRule-based, reactive DFM is impractical

Model-based, proactive DFM is the answerModel-based, proactive DFM is the answer– Early in the design flowEarly in the design flow– Find the best trade-off based on actual Find the best trade-off based on actual

process capabilitiesprocess capabilities– Before verificationBefore verification