Application of Silicon-Germanium in the Fabrication of Ultra-shallow

Extension Junctions of Sub-100 nm PMOSFETs

P. Ranade, H. Takeuchi, W.-H. Lee, V. Subramanian, and T.-J. King

IEEE Trans, Electron Devices, vol. 49, pp.1436-1443, Aug. 2002

C.-F. Huang ( 黃靖方 )05/26/2004

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Outline Introduction Si1-xGex/Si Heterojunctions: Electrical

and Materials Characterization A ： Ge+ Implantation B ： Selective Ge Deposition and Interdiffusion Si1-xGex S/D PMOSFETs Formed By Ge+

and B+ Implantation Elevated S/D PMOSFETs Formed By S

elective Ge Deposition Summary

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Introduction

For scaling of CMOS technology, the short channel performance is of significant consideration.

According to the ITRS, bulk-Si CMOS with Lg ≤ 50 nm will require ultra-shallow S/D extension junctions. (xj ≤ 30 nm )

Junctions will be heavily-doped to reduce Rs (≤ 200Ω/□) and improve ID.

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ITRS Roadmap

year 2005 2006 2007 2008 2009 2010 Rule(nm) 80 70 65 57 50 45 LOPEOT(Å) 14 13 12 11 10 9 HiPEOT(Å) 11 10 9 8 8 7 LOP (nA/um) 1 1 1.67 1.67 1.67 2.33 HiP(nA/um) 170 170 230 230 230 330 Solution Exist Solution are known No Known Solutions

(2003 ITRS )LpLp HiP +HiP +

metalmetaltarget

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Introduction (continued)

Scaling(Improve SCE)

Heavily Doped RS ≤ 200Ω/□

Improve Drive CurrentExtremely abrupt

Ultra-shallow Junctions(Xj ≤ 30 nm)

Limitations: Solid solubility Diffusion of dopants in Si

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Introduction (continued)

Why PMOS ? Higher diffusivity Lower solid solubility of B in Si (as compared to As and P)

More Challenging

This paper discusses two simple approaches to incorporate Ge in the S/D regions which greatly improve the SCE.

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Techniques to Fabricate Ultra-shallow Junctions

Ion implantation with ultralow energy Typical kinetic energy: 10~30 keV Ultralow energy: ≤ 1 keV

Disadvantages:High concentration of dopant atoms is achievable, but it is difficult to achieve a high concentration of electrically active dopants.

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Spike and laser annealing to achieve abrupt junctions

With very high active dopant concentrations.

Disadvantages:Rely on extremely high temperatures. (near melting)Thermal instability in the gate.(Replacement of high-K dielectrics constrains on max. annealing temp. The excess, super-saturated dopants inactive clusters )

Techniques to Fabricate Ultra-shallow Junctions

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Outline Introduction Si1-xGex/Si Heterojunctions: Electrical

and Materials Characterization A ： Ge+ Implantation B ： Selective Ge Deposition and Interdiffusion Si1-xGex S/D PMOSFETs Formed By Ge+

and B+ Implantation Elevated S/D PMOSFETs Formed By S

elective Ge Deposition Summary

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1.LOCOS isolation2.Thermal oxidation (~6 nm SiO2)3.Ge+ implantation (6 keV, 1e16 cm-2)4.Annealing5.Thin Si1-xGex layer was produced (~25 nm)6.B implantation (5 keV, 3e15 cm-2)

Fabrication sequence of p+/n Si1-xGex/Si junction diodes

A ： Ge+ Implantation

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SIMS Concentration-depth Profiles (Annealing at 900oC)

Peak Ge concentration of ~14%

At the surface, a steep profile and a high peak concentration of B are obtained. (5x1020 cm-

3)

The B profile is markedly shallower with the Ge present

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Comparison of Leakage Currents for Heterojunction and Control Devices

The excess leakage is due to residual physical damage produced by Ge implant.The leakage can be minimized via C implantation into SiGe.

The sheet resistance: p+ Si1-xGex 376 Ω/□ p+ Si layer 2826 Ω/□ Significant reduction !!

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B ： Selective Ge Deposition and Interdiffusion

1.Thin poly-crystalline films of Ge (60 nm) were selectively deposited.2.Boron was implanted into the Ge film.3.Co-diffusion to form hetero- junction diodes.

Fabrication sequence of doped Si1-xGex/Si

heterojunction diodes

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Comparison of SIMS Profiles Indicating Interdiffusion Across Si/Ge Interfaces

Interdiffusion between Si and Ge is significantly enhanced

Undoped Ge/Si interfaces

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The B profile is contained within the Ge profile

in-situ formation of a heavily doped junction.

SIMS Profiles Indicating Interdiffusion Across Si/Ge Interfaces

Selective Ge deposition followed by the co-diffusion of Ge and B atoms can lead to the formation of shallow and highly doped Si1-x/Gex heterojunction

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Comparison of Leakage Currents for Heterojunction and Control Devices

The higher leakage seen in heterojunction diodes is due to higher density of defects around the Si1-xGex/Si interface.It can be reduced by optimization of implantation and annealing conditions.

The sheet resistance: heterojunction 350 Ω/□ (1min) 300 Ω/□ (2min) homojunction 748 Ω/□ (1min)

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Outline Introduction Si1-xGex/Si Heterojunctions: Electrical

and Materials Characterization A ： Ge+ Implantation B ： Selective Ge Deposition and Interdiffusion Si1-xGex S/D PMOSFETs Formed By Ge+

and B+ Implantation Elevated S/D PMOSFETs Formed By S

elective Ge Deposition Summary

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Si1-xGex S/D PMOSFETs Formed By Ge+ and B+ Implantation

1.LOCOS isolation 2.High-energy implantation to form a retrograde cannel doping profile. 3.To grow 2.5 nm gate oxide and 150 nm undoped poly-Si. 4.E-beam lithography 5.Ge implantation (10 keV, 1x1016 cm-2) (Rp=6 nm,ΔRp=4 nm, peak=20%) 6.Annealing to recrystallize 7.Dummy sidewall spacers 8.B implantation (5keV, 3x1015 cm-2) 9.Spacer was removed by H2O2

10.RTA

Process Sequence:

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SiGe layer as sink for diffusing B atoms to form very shallow extensions

Si1-xGex S/D PMOSFETs Formed By Ge+ and B+ Implantation

The S/D extensions were formed purely by lateral diffusion of B during the RTA steps

The Control device (w/o Ge implant) received an additional LDD B implant (BF2

+ at 5 keV, 3x1015 cm-2)

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Comparison of Short-channel Characteristics of PMOSFETs

Short-channel effects are effectively suppressed with the proposed Ge implant process, indicating that more abrupt and shallow junctions are achieved.

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Comparison of I-V Characteristics

The drive current was enhanced compared with the device fabricated by the conventional LDD process

DIBL effect reduces significantly!!

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Outline Introduction Si1-xGex/Si Heterojunctions: Electrical

and Materials Characterization A ： Ge+ Implantation B ： Selective Ge Deposition and Interdiffusion Si1-xGex S/D PMOSFETs Formed By Ge+

and B+ Implantation Elevated S/D PMOSFETs Formed By S

elective Ge Deposition Summary

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Elevated S/D PMOSFETs Formed By Selective Ge Deposition

1.LOCOS isolation 2.High-energy implantation to form a retrograde cannel doping profile. 3.To grow 2 nm gate oxide and 150 nm undoped poly-Si0.8Ge0.2. 4.20 nm SiO2 deposition (hard mask) 5.E-beam lithography & RIE 6.25 nm wide sidewall spacers formed 7.HF dip and 60 nm of Ge selectively implanted (LPCVD) 8.20 nm capping layer of SiO2 deposition. 9.B+ implantation (5keV, 6x1015 cm-2)10.RTA (900oC, 7min)11.Ge and B co-diffusion into Si to from S/D extensions during the annealing steps.

Process Sequence:

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I-V Characteristics (turn-off state)

Lg=80 nm w/o halo implant Elevated S/D structure Low subthreshold swing (82 mV/decade)

Lg=60 nm w/ halo implant Elevated S/D structure Acceptable short channel performance (84 mV/decade)

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Comparison of Short-channel Characteristics of PMOSFETs

Elevated S/D structure with Si1-xGex S/D extensions effectively suppresses SCE

Drive current:

Control device: 178μA/ μm Elevated S/D: 128μA/ μm

40% Improvement!!

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Outline Introduction Si1-xGex/Si Heterojunctions: Electrical

and Materials Characterization A ： Ge+ Implantation B ： Selective Ge Deposition and Interdiffusion Si1-xGex S/D PMOSFETs Formed By Ge+

and B+ Implantation Elevated S/D PMOSFETs Formed By S

elective Ge Deposition Summary

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Summary

This work reports on the potential applications of Si1-xGex in the fabrication of ultra-shallow S/D extensions in PMOSFET devices.

It is shown to result in excellent suppression of short channel effects.

Si1-xGex allows for the fabrication with high concentrations of electrically active dopant atoms and low sheet resistance.

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Summary

Relatively low annealing temperatures is advantageous for integration of high-k dielectrics and metal gate electrodes.

These techniques can enable the scaling into the sub-50 nm gate length regimes