arm lab3 - core peripherals

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ARM Lab3 CORE PERIPHERALS 碩碩 碩碩碩 碩碩碩 碩碩碩 碩碩碩 碩碩碩 碩碩碩

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ARM Lab3 - CORE PERIPHERALS. 碩二 醫工所:葉昱甫 碩一 電子所:謝博鈞 碩一 電信所:王欣平. 大網. 說明 習題 Timer/Interrupt RTC/Interrupt 問題與討論. Timer/Interrupt Block Diagram. Device. Timer Status. Interrupt Controller. Vector Table 0x18. Timer Status. Branch to ISR. Device. 代表未執行 interrupt 的 Timer 相關暫存器狀態. - PowerPoint PPT Presentation

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Page 1: ARM   Lab3 -  CORE PERIPHERALS

ARM Lab3- CORE PERIPHERALS

碩二 醫工所:葉昱甫碩一 電子所:謝博鈞碩一 電信所:王欣平

Page 2: ARM   Lab3 -  CORE PERIPHERALS

大網 說明 習題

Timer/Interrupt RTC/Interrupt

問題與討論

Page 3: ARM   Lab3 -  CORE PERIPHERALS

TIMERx_CTRL TIMERx_LOAD

Prescaler Down-counter

TIMERx_VALUE

Read/WriteRead/Write

Clock

Divisor Mode

Interrupt

Read

Timer/Interrupt Block Diagram

Page 4: ARM   Lab3 -  CORE PERIPHERALS

Timer0/Interrupt(程式流程圖 )

Device InterruptController

TimerStatus

Vector Table0x18

Branch toISR

TimerStatusDevice

代表已執行 interrupt的 Timer相關暫存器狀態代表未執行 interrupt的 Timer相關暫存器狀態

Page 5: ARM   Lab3 -  CORE PERIPHERALS

Timer0/Interrupt

Page 6: ARM   Lab3 -  CORE PERIPHERALS

Timer0/Interrupt

Page 7: ARM   Lab3 -  CORE PERIPHERALS

Timer0/Interrupt

Page 8: ARM   Lab3 -  CORE PERIPHERALS

3.2.3 Timer/Interrupt The example must be run on the integrato

r to work. Using Armulator will not be able to show the correct results.

Should be: Using Armulator is totally MEANINGLES

S!

Page 9: ARM   Lab3 -  CORE PERIPHERALS

void WriteTimerCtrl(int writevalue){int TIMER0_CTRL_ADDR = 0x13000008;int *TIMER0_CTRL;

TIMER0_CTRL = (int *)TIMER0_CTRL_ADDR;

*TIMER0_CTRL = writevalue;printf("Timer Message>>> Timer0 control register ch

anged!!\n");}

void ClearTimer(void){int TIMER0_CLEAR_ADDR = 0x1300000C;int *TIMER0_CLEAR;

TIMER0_CLEAR = (int *)TIMER0_CLEAR_ADDR;

*TIMER0_CLEAR = 1;printf("Timer Message>>> Timer0 cleared!!\n");

}

int main(void) {int IRQ0_STATUS_ADDR = 0x14000000;int IRQ0_RAWSTAT_ADDR = 0x14000004;int IRQ0_ENABLESET_ADDR = 0x14000008;int IRQ0_ENABLECLR_ADDR = 0x1400000C;

int *IRQ0_STATUS, *IRQ0_RAWSTAT, *IRQ0_ENABLESET, *IRQ0_ENABLECLR;

int b_num[22];int i;unsigned *irqvec = (unsigned *)0x18;

Install_Handler( (unsigned)myIRQHandler, irqvec ); /* Install user’s IRQ Handler */enable_IRQ(); /* DR added - ENABLE IRQs */

IRQ0_STATUS = (int *) IRQ0_STATUS_ADDR;IRQ0_RAWSTAT = (int *) IRQ0_RAWSTAT_ADDR;IRQ0_ENABLESET = (int *) IRQ0_ENABLESET_ADDR;IRQ0_ENABLECLR = (int *) IRQ0_ENABLECLR_ADDR;

*IRQ0_ENABLESET = 0x0021;

Page 10: ARM   Lab3 -  CORE PERIPHERALS

d2b(*IRQ0_STATUS,22,b_num);printf("IRQ0_STATUS: ");printB(*IRQ0_STATUS,22,b_num);

d2b(*IRQ0_RAWSTAT,22,b_num);printf("IRQ0_RAWSTAT: ");printB(*IRQ0_RAWSTAT,22,b_num);

d2b(*IRQ0_ENABLESET,22,b_num);printf("IRQ0_ENABLESET: ");printB(*IRQ0_ENABLESET,22,b_num);

d2b(*IRQ0_ENABLECLR,22,b_num);printf("IRQ0_ENABLECLR: ");printB(*IRQ0_ENABLECLR,22,b_num);

LoadTimer(64); /* set Timer0 reload value to 64 */WriteTimerCtrl(0xC4); /* Enable the timer */// wait for a whilefor(i=0;i<1000000000;i++){

;}printf("\nEND\n");return 0;

}

Page 11: ARM   Lab3 -  CORE PERIPHERALS

#include <stdio.h>

unsigned Install_Handler( unsigned routine, unsigned *vector ){

unsigned vec, oldvec;vec = ((routine - (unsigned)vector - 0x8) >> 2 ); /*->routine is the pointer point to the IRQ handler. *//*->shift right 2 is for address word aligned. *//*->subtract 8 is due to the pipeline *//*since PC will be fetching the 2nd instruction *//* after the instruction currently being executed. */vec = 0xea000000 | vec; /* to implement the instruction B <address> *//* 0xea is the Branch operation */oldvec = *vector; /* the IRQ address or FIQ address */*vector = vec;

/* the contents of IRQ address is now the branch instruction */return (oldvec);

}

__irq void myIRQHandler (void){

printf("\nFrom IRQ Handler>>HIHI!!\n");ClearTimer(); /* Clear the timer’s IRQ */

}

// this function is used to set the I bit in CPSR__inline void enable_IRQ(void) { int tmp; __asm { MRS tmp, CPSR

BIC tmp, tmp, #0x80 MSR CPSR_c, tmp }}

ADS_DeveloperGuide.pdf: 5.3

ADS_DeveloperGuide.pdf: 5.5

Page 12: ARM   Lab3 -  CORE PERIPHERALS

d2b(*IRQ0_STATUS,22,b_num);printf("IRQ0_STATUS: ");printB(*IRQ0_STATUS,22,b_num);

d2b(*IRQ0_RAWSTAT,22,b_num);printf("IRQ0_RAWSTAT: ");printB(*IRQ0_RAWSTAT,22,b_num);

d2b(*IRQ0_ENABLESET,22,b_num);printf("IRQ0_ENABLESET: ");printB(*IRQ0_ENABLESET,22,b_num);

d2b(*IRQ0_ENABLECLR,22,b_num);printf("IRQ0_ENABLECLR: ");printB(*IRQ0_ENABLECLR,22,b_num);

LoadTimer(64); /* set Timer0 reload value to 64 */WriteTimerCtrl(0xC4); /* Enable the timer */// wait for a whilefor(i=0;i<1000000000;i++){

;}printf("\nEND\n");return 0;

}

Page 13: ARM   Lab3 -  CORE PERIPHERALS

必看文件 DUI_0098B_AP_UG.pdf: Ch3 Ch4 ADS_DeveloperGuide.pdf: 5.3 5.5 將參考文件加註於程式碼

Page 14: ARM   Lab3 -  CORE PERIPHERALS

Introduction of RTC “Real” in Real Time Clock means

“authentic” not “simultaneous.” It is triggered per second, like a clock on

your watch. As a system application clock (like watch)

Page 15: ARM   Lab3 -  CORE PERIPHERALS

RTC的介紹

Page 16: ARM   Lab3 -  CORE PERIPHERALS

RTC Block Diagram

RTC_DR

1 Hz

By System FPGA

RTC_LR

Page 17: ARM   Lab3 -  CORE PERIPHERALS

問題與討論

TIMER0/COUNTER0

TIMER1/COUNTER1

TIMER2/COUNTER2

Event B

Event C

Event E

Event D

Event A

Timer 0&

Counter 0

Timer 1&

Counter 1

Timer 2&

Counter 2

Event A

Event C

Event B

Event D

Event E Event F Event G

Timer串用 Timer並用

Page 18: ARM   Lab3 -  CORE PERIPHERALS

參考資料 ADS_CompilerLinkerUtil_C.pdf ADS_DeveloperGuide_C.pdf DUI0098B_AP_UG.pdf

Page 19: ARM   Lab3 -  CORE PERIPHERALS

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