asic programming2_2003

8/8/2019 ASIC programming2_2003

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PresentationOn

ASIC Programming

By,

Nayan Prajapati (10MEEC13)

Rakesh Prajapati (10MEEC14)

MEEC, Sem-I, KIT&RC.


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Contents:

Introduction to VHDL

VHDL Versions and Capabilities

Configuration and Package declaration

Functions and Procedures

VHDL and Verilog : Comparison

Sample program of Verilog

Sample Program of SystemC


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What is ASIC Programming ?

Application Specific Integrated Circuits

Entire systems on a single chip.

ASIC Programming is part of ASIC Design flow.

RTL Description

Register Transfer Level. RTL description.

Describes the design in terms registers.

Verilog and VHDL are two most popular hardware

description languages.

Functional Simulation/Verification:

Synthesis:

Design Verification:

Layout:


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Introduction to VHDL :

VHSIC hardware description language;

describe digital and mixed-signal systems

VHDL was originally developed at the US Department of Defense

an alternative to huge, complex manuals which were subject toimplementation-specific details.

VHDL borrows heavily from the Ada .

Like Ada, VHDL is strongly typed and is not case sensitive.

There are many features of VHDL which are not found in Ada, such as an

extended set of Boolean operators including NAND and NOR,


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The VHDL language can be regarded as an integrated amalgamation of the following

languages:

sequential language +

concurrent language +

net-list language +

timing specifications +

waveform generation language => VHDL

Express the concurrent or sequential behavior of a digital system with or without

timing.

It also allows you to model the system as an interconnection of components.

Test waveforms can also be generated using the same constructs.


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VHDL Versions :

A team of three companies, IBM, Texas Instruments, and Intermetrics, werefirst awarded the contract.

Version 7.2 of VHDL in 1985

IEEE for standardization in 1986

IEEE Std 1076-1987.

also been recognized as an American National Standards Institute (ANSI)

standard.


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Capabilities :

An exchange medium between chip vendors and CAD tool users.

Supports flexible design methodologies: top-down, bottom-up, or mixed.

Supports both synchronous and asynchronous timing models

Supports three basic different description styles: structural, dataflow, andbehavioral.

There is no need to learn a different language for simulation control. Test benches

can be written using the same language to test other VHDL models.

Nominal propagation delays, min-max delays, setup and hold timing, timingconstraints, and spike detection can all be described very naturally


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To describe an entity, VHDL provides five different types of primary constructs, called"

design units.

They are

1. Entity declaration

2. Architecture body

3. Configuration declaration

4. Package declaration

5. Package body


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Configuration Declaration :

library CMOS_LIB, MY_LIB;

configuration HA_BINDING of HALF_ADDER is

for HA-STRUCTURE

for X1:XOR2

use entity CMOS_LIB.XOR_GATE(DATAFLOW);

end for;

for A1:AND2

use configuration MY_LIB.AND_CONFIG;

end for;

end for;

end HA_BINDING;


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Package Declaration

package EXAMPLE_PACK is

type SUMMER is (MAY, JUN, JUL, AUG, SEP);

component D_FLIP_FLOP

port (D, CK: in BIT; Q, QBAR: out BIT);

End component;

constant PIN2PIN_DELAY: TIME := 125 ns;

function INT2BIT_VEC (INT_VALUE: INTEGER)

return BIT_VECTOR;

end EXAMPLE_PACK;


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Functions:

function LARGEST (TOTAL_NO: INTEGER; SET: PATTERN)

return REAL is-- PATTERN is defined to be atype of 1-D array of

-- floating-point values, elsewhere.

variable RETURN_VALUE: REAL := 0.0;

begin

for K in 1 to TOTAL_NO loopif SET(K) > RETURN_VALUE then

RETURN_VALUE := SET(K);

end if;

end loop;

return RETURN_VALUE;

end LARGEST;


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Procedure:

type OP_CODE is (ADD, SUB, MUL, DIV, LT, LE, EQ);

. . .procedure ARITH_UNIT (A, B: in INTEGER; OP: in OP_CODE;

Z: out INTEGER; ZCOMP: out BOOLEAN) is

begin

case OP is

when ADD=>Z:=A+B;when SUB=>Z:=A-B;

when MUL=>Z:=A*B;

when DIV => Z := A/B;

when LT => ZCOMP := A < B;

when LE => ZCOMP := A ZCOMP := A = B;end case;

end ARITH_UNIT;


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Difference between VHDL and Verilog.

Compilation:

VHDL : Multiple design-units (entity/architecture pairs), that reside in the same

system file, may be separately compiled.

Verilog : Multiple design-units (entity/architecture pairs), that reside in the same

system file, are not separately compiled.

Design reusability

VHDL. Procedures and functions may be placed in a package so that they are avail

able to any design-unit that wishes to use them.

Verilog: There is no concept of packages in Verilog.

Easiest to Learn

Starting with zero knowledge of either language, Verilog is probably the easiest to

grasp and understand.


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Language Extensions

VHDL : Foreign attributes allows architectures and subprograms to bemodeled in another language.

Verilog : PLI an interface mechanism between Verilog models and Verilog

software tools. For example, a designer, or more likely, a Verilog tool

vendor, can specify user defined tasks or functions in the C

programming language, and then call them from the Verilog source

description.

Libraries

VHDL. A library is a store for compiled entities, architectures, packages and

configurations. Useful for managing multiple design projects.

Verilog. There is no concept of a library in Verilog. This is due to it's origins

as an interpretive language.


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Managing large designs

VHDL. Configuration, generate, generic and package statements all helpmanage large design structures.

Verilog. There are no statements in Verilog that help manage large designs.


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Verilog sample programe :

An example counter circuit follows:

module Div20x (rst, clk, cet, cep, count,tc);parameter size = 5;

parameter length = 20;

input rst;

input clk;

input cet;input cep;

output [size-1:0] count;

output tc;

reg [size-1:0] count;wire tc;

always @ (posedge clk or posedge rst)

if (rst)

count


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if (count == length-1)

count


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SystemC sample program:

#include "systemc.h"

#define WIDTH 4

SC_MODULE(adder)

{

sc_in a, b;

sc_out sum;

void do_add()

{

sum.write(a.read() + b.read());

}

SC_CTOR(adder){

SC_METHOD(do_add);

sensitive


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References :

[I] J. Bhaskar, A VHDL Primer ,P T R Prentice Hall.

[2] www.doulos.com

[3] www.verilog.net


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