Beyond the Red Brick Wall: Physical Design Beyond the Red Brick Wall: Physical Design Challenges at 50nm and BelowChallenges at 50nm and Below

Andrew B. KahngAndrew B. Kahng

UC San Diego, Depts. of CSE and ECEUC San Diego, Depts. of CSE and ECEabkabk@ucsd.edu@ucsd.edu

http://vlsicad.ucsd.http://vlsicad.ucsd.eduedu ( (http://vlsicad.cs.ucla.eduhttp://vlsicad.cs.ucla.edu ) )

2ASPDAC’2001

What is NOT a Physical Design Challenge?What is NOT a Physical Design Challenge?

Problems that are beyond PD scope / controlProblems that are beyond PD scope / controlFinding high-k dielectric materialsFinding high-k dielectric materialsCreativity (e.g., AMS/RF circuit innovations)Creativity (e.g., AMS/RF circuit innovations)

We are in the “automation” (not the creativity) businessWe are in the “automation” (not the creativity) business

Problems whose instance sizes and solution times Problems whose instance sizes and solution times scale with power of available computing platformsscale with power of available computing platformsMost analyses (static timing, SI, dynamic simulation, …)Most analyses (static timing, SI, dynamic simulation, …)

Assumption: “methodology” will be applied (filtering, incr / Assumption: “methodology” will be applied (filtering, incr / ECO, hierarchy, divide/conquer, abstracts, guardbanding, …)ECO, hierarchy, divide/conquer, abstracts, guardbanding, …)

In future, In future, commoditycommodity syntheses synthesesScalable Engines = (free) Commodities Scalable Engines = (free) Commodities (multilevel paradigm:) Place, Perf Opt, Logic Synth, Route, …(multilevel paradigm:) Place, Perf Opt, Logic Synth, Route, …

3ASPDAC’2001

PrimaryPrimary Driver at 50nm: System Driver at 50nm: System CostCost

NRE Cost for DesignNRE Cost for DesignTAT = driver for TAT = driver for MethodologyMethodology

http://www.eda.org/edps

CostCost of Design Technology of Design Technology = not so well- = not so well-understoodunderstood

Application-Specific CADApplication-Specific CAD (e.g., high-volume custom vs. SOC) (e.g., high-volume custom vs. SOC)Design Design TechnologyTechnology Productivity: Roadmaps, Reuse, Productivity: Roadmaps, Reuse, MetricsMetrics

IEEE Design and Test Special Issue, Nov-Dec 2001; ITRS-2001 effort

NRE Cost for ManufacturingNRE Cost for ManufacturingManufacturing CostManufacturing CostDesign for Cost-of-ManufacturingDesign for Cost-of-Manufacturing

VariabilityVariability and and Die-Package-Board interactionsDie-Package-Board interactions

4ASPDAC’2001

ComplementaryComplementary Driver at 50nm: System Driver at 50nm: System ValueValue

Quality of Design = Value of DesignQuality of Design = Value of DesignSpeed, Reliability, Parametric Yield, …Speed, Reliability, Parametric Yield, …Key Issue #1: Power Key Issue #1: Power

Speed-power = fundamental tradeoffSpeed-power = fundamental tradeoffStatic power dissipation, power distribution, …Static power dissipation, power distribution, …

How to avoid battery weight, use of advanced forced-air and chilling, …Key Issue #2: Synchronization and Global SignalingKey Issue #2: Synchronization and Global Signaling

Fundamental clocking limits, latency-insensitive design Fundamental clocking limits, latency-insensitive design methodology, …methodology, …

Issues that are NOT driving PD: Issues that are NOT driving PD: ““Litany” UDSM = T+SI+IR+GB+L+EM+SH+HE+EMI+SEU…”Litany” UDSM = T+SI+IR+GB+L+EM+SH+HE+EMI+SEU…”

5ASPDAC’2001

1. TAT: Closing the Synthesis-Analysis Loop1. TAT: Closing the Synthesis-Analysis Loop

How we handle this loop == the heart of “methodology” How we handle this loop == the heart of “methodology” E.g., “Correct by Construction” (assume/enforce, predict/enforce, …)E.g., “Correct by Construction” (assume/enforce, predict/enforce, …) E.g., “Construct by Correction” (tool, data model, DB for tight S/A loop)E.g., “Construct by Correction” (tool, data model, DB for tight S/A loop) Syntheses must have true estimation capabilities Syntheses must have true estimation capabilities

Syntheses must be driven by Syntheses must be driven by most-appropriatemost-appropriate abstractions or approximations of Analysesabstractions or approximations of Analyses

How much is left on the table depends on two things:How much is left on the table depends on two things:How well do we make methodology choices? (Space / shield / How well do we make methodology choices? (Space / shield /

rpt / size …? Optimization / layout / synthesis loop structure?)rpt / size …? Optimization / layout / synthesis loop structure?)How well do we identify objectives for engines in PD? (e.g., FP, How well do we identify objectives for engines in PD? (e.g., FP,

GPlace)GPlace)Greatest leverage: Chip planning (block shaping/placement, Greatest leverage: Chip planning (block shaping/placement,

interconnect planning)interconnect planning)Very important to work on right problems with right goalsVery important to work on right problems with right goals

Cf. ISPD-2000 talk on floorplanningCf. ISPD-2000 talk on floorplanning

6ASPDAC’2001

2. Cost: Closing the Design-Manufacturing Loop2. Cost: Closing the Design-Manufacturing Loop

Silicon mindsetSilicon mindsetECAD / Mask / Mfg merged infrastructuresECAD / Mask / Mfg merged infrastructuresVariability: improved taxonomy and criteriaVariability: improved taxonomy and criteria

7ASPDAC’2001

What does EDA know about process today?What does EDA know about process today?

Process

Develop.:•Lithography

•Device

Device models

Design rules

TCAD

Design

ECAD

GDSII

“Clean Abstraction” = As Little as Possible = Next to Nothing

8ASPDAC’2001

What Must EDA Know Tomorrow?What Must EDA Know Tomorrow?

Mask

Process

Develop.:•Lithography

•Device

Device models

Design rules

TCAD Production

Fab

Design

Process

Requirements

Devl. Fab

ECAD

Semi

suppliers

GDSII, tolerances,...

tolerances...

“Useful Abstraction” = As Much as Possible

9ASPDAC’2001

PSM in 180nm Library CellPSM in 180nm Library Cell

10ASPDAC’2001

Field-Dependent AberrationField-Dependent Aberration

Cell A

Cell A

Cell A

(X 1 , Y 1)

(X 0 , Y 0)

(X 2 , Y 2)

F ie ld-dependentaberrationsaffect the fide lityand p lacem entof critica l c ircu itfeatures.

Big C hip

Field-dependent aberrations cause placement errors Field-dependent aberrations cause placement errors

and distortionsand distortions),(A_CELL),(A_CELL),(A_CELL 220011 YXYXYX

Center: Minimal Aberrations

Edge: High Aberrations

Tow

ard

s Le

ns

Wafer Plane

Lens

R. Pack, Cadence

11ASPDAC’2001

Example ChallengesExample ChallengesFunction-awareFunction-aware OPC/PSM/Fill insertion (corrections) OPC/PSM/Fill insertion (corrections)

Layout corrections are for predictable circuit performance, Layout corrections are for predictable circuit performance, functionfunction

Tools should understand functional intent, make only the Tools should understand functional intent, make only the corrections that win $$$, reduce performance variationcorrections that win $$$, reduce performance variation

Applies to mask inspection alsoApplies to mask inspection also

Cost-awareCost-aware corrections corrections Don’t make corrections that can’t be manufactured or verifiedDon’t make corrections that can’t be manufactured or verifiedUnderstand costs of each correction (data volume, yield costs, Understand costs of each correction (data volume, yield costs,

verificationverification costs, etc.) costs, etc.)

Solutions to (difficult) flow issuesSolutions to (difficult) flow issueshow to avoid making same correction 3x (lib, router, PV tool)how to avoid making same correction 3x (lib, router, PV tool)

12ASPDAC’2001

Some Variability Analysis NeedsSome Variability Analysis Needs

Taxonomy:Taxonomy:Static:Static: t_ox, V_t, L_eff, … t_ox, V_t, L_eff, …Dynamic:Dynamic: V_dd, rho, … V_dd, rho, … Instance:Instance: interconnection topology and embedded length interconnection topology and embedded length

distribution, …distribution, …Correctable vs. uncorrectableCorrectable vs. uncorrectable

Distinguish primary vs. derived variabilities, e.g., dopant / Idsat Distinguish primary vs. derived variabilities, e.g., dopant / Idsat

Model back to root causes, e.g., registration error, microloadingModel back to root causes, e.g., registration error, microloading

Model the context, e.g., vias, dielectrics, critical pathsModel the context, e.g., vias, dielectrics, critical paths

Model correlations and anti-correlations (e.g., dimensions of line vs. Model correlations and anti-correlations (e.g., dimensions of line vs. space, line vs. ILD)space, line vs. ILD)

13ASPDAC’2001

3. Closing the Design 3. Closing the Design TechnologyTechnology Productivity GapProductivity Gap

Design Productivity Gap Design Productivity Gap huge cost to semiconductor industryhuge cost to semiconductor industry

Traditional perspective: change the Design Traditional perspective: change the Design Problem, invent new algorithms, ... Problem, invent new algorithms, ...

New perspective: Design Productivity Gap == New perspective: Design Productivity Gap == Design Design TechnologyTechnology Productivity Gap Productivity GapProblem: Improve Time-To-Market and Quality-of-Result for Problem: Improve Time-To-Market and Quality-of-Result for

Design Design TechnologyTechnologyNew goal: Improve how we New goal: Improve how we specifyspecify, , developdevelop, and , and measuremeasure andand

improveimprove Design Technology Design Technology (PD is a good place to start)(PD is a good place to start)

14ASPDAC’2001

Aspects of the Design Technology GapAspects of the Design Technology GapNo RoadmapNo RoadmapTime-to-Market: 5-7 yr to get new algorithm into production Time-to-Market: 5-7 yr to get new algorithm into production

Time-to-Market: No reuse in design technology Time-to-Market: No reuse in design technology Lack of “Foundation CAD-IP”Lack of “Foundation CAD-IP”Over-resourcing of non-strategic technologyOver-resourcing of non-strategic technology

QOR: difficult to evaluate impact of new tools, new QOR: difficult to evaluate impact of new tools, new research on overall design process research on overall design process

Lack of standard metrics (especially cost metrics) for design Lack of standard metrics (especially cost metrics) for design technology, design processtechnology, design processIf you can’t measure it, you can’t improve it !!!If you can’t measure it, you can’t improve it !!!

15ASPDAC’2001

New Infrastructure is Needed to Answer:New Infrastructure is Needed to Answer: Improved vision and design technology planning (“specify”): Improved vision and design technology planning (“specify”):

What will the design problem look like? What will the design problem look like? Accurate roadmapping for Design Technology Accurate roadmapping for Design Technology Application-Specific Design Technology (cost-driven)Application-Specific Design Technology (cost-driven)

Improved execution (“develop”): Improved execution (“develop”): How can we quickly develop the right technology (TTM)?How can we quickly develop the right technology (TTM)?Reusable, commodity, Foundation CAD-IPReusable, commodity, Foundation CAD-IP

Improved measurement (“measure and improve”):Improved measurement (“measure and improve”):Did we solve the problem (QOR)? Did the design process improve? Did we solve the problem (QOR)? Did the design process improve? Design tool/process metrics, design process instrumentationDesign tool/process metrics, design process instrumentation

Design Technology Productivity will improve Design ProductivityDesign Technology Productivity will improve Design Productivity